JP5053919B2 - 表面実装デバイスの実装構造体 - Google Patents

表面実装デバイスの実装構造体 Download PDF

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Publication number
JP5053919B2
JP5053919B2 JP2008110464A JP2008110464A JP5053919B2 JP 5053919 B2 JP5053919 B2 JP 5053919B2 JP 2008110464 A JP2008110464 A JP 2008110464A JP 2008110464 A JP2008110464 A JP 2008110464A JP 5053919 B2 JP5053919 B2 JP 5053919B2
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JP
Japan
Prior art keywords
land
resist
rectangular
semiconductor device
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008110464A
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English (en)
Japanese (ja)
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JP2009239240A (ja
JP2009239240A5 (enExample
Inventor
誠治 時井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2008110464A priority Critical patent/JP5053919B2/ja
Publication of JP2009239240A publication Critical patent/JP2009239240A/ja
Publication of JP2009239240A5 publication Critical patent/JP2009239240A5/ja
Application granted granted Critical
Publication of JP5053919B2 publication Critical patent/JP5053919B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP2008110464A 2008-03-07 2008-04-21 表面実装デバイスの実装構造体 Expired - Fee Related JP5053919B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008110464A JP5053919B2 (ja) 2008-03-07 2008-04-21 表面実装デバイスの実装構造体

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008058263 2008-03-07
JP2008058263 2008-03-07
JP2008110464A JP5053919B2 (ja) 2008-03-07 2008-04-21 表面実装デバイスの実装構造体

Publications (3)

Publication Number Publication Date
JP2009239240A JP2009239240A (ja) 2009-10-15
JP2009239240A5 JP2009239240A5 (enExample) 2011-05-12
JP5053919B2 true JP5053919B2 (ja) 2012-10-24

Family

ID=41252793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008110464A Expired - Fee Related JP5053919B2 (ja) 2008-03-07 2008-04-21 表面実装デバイスの実装構造体

Country Status (1)

Country Link
JP (1) JP5053919B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9345148B2 (en) * 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
JP5776373B2 (ja) * 2011-06-29 2015-09-09 株式会社デンソー 電子装置
JP5980634B2 (ja) 2012-09-14 2016-08-31 富士通コンポーネント株式会社 プリント基板
JP2024153955A (ja) * 2021-07-13 2024-10-30 株式会社村田製作所 回路基板及び電子部品

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297889A (ja) * 1998-04-16 1999-10-29 Sony Corp 半導体パッケージおよび実装基板、ならびにこれらを用いた実装方法
CN100482041C (zh) * 2002-05-17 2009-04-22 日本电气株式会社 印刷布线板
JP2007005452A (ja) * 2005-06-22 2007-01-11 Renesas Technology Corp 半導体装置

Also Published As

Publication number Publication date
JP2009239240A (ja) 2009-10-15

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