JP5043563B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP5043563B2
JP5043563B2 JP2007222917A JP2007222917A JP5043563B2 JP 5043563 B2 JP5043563 B2 JP 5043563B2 JP 2007222917 A JP2007222917 A JP 2007222917A JP 2007222917 A JP2007222917 A JP 2007222917A JP 5043563 B2 JP5043563 B2 JP 5043563B2
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JP
Japan
Prior art keywords
terminal
wiring board
terminal pad
mounting surface
terminal pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007222917A
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English (en)
Japanese (ja)
Other versions
JP2009054969A5 (https=
JP2009054969A (ja
Inventor
泰志 横田
章夫 堀内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007222917A priority Critical patent/JP5043563B2/ja
Publication of JP2009054969A publication Critical patent/JP2009054969A/ja
Publication of JP2009054969A5 publication Critical patent/JP2009054969A5/ja
Application granted granted Critical
Publication of JP5043563B2 publication Critical patent/JP5043563B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
JP2007222917A 2007-08-29 2007-08-29 配線基板及びその製造方法 Expired - Fee Related JP5043563B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007222917A JP5043563B2 (ja) 2007-08-29 2007-08-29 配線基板及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007222917A JP5043563B2 (ja) 2007-08-29 2007-08-29 配線基板及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012155863A Division JP5399539B2 (ja) 2012-07-11 2012-07-11 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2009054969A JP2009054969A (ja) 2009-03-12
JP2009054969A5 JP2009054969A5 (https=) 2010-07-29
JP5043563B2 true JP5043563B2 (ja) 2012-10-10

Family

ID=40505745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007222917A Expired - Fee Related JP5043563B2 (ja) 2007-08-29 2007-08-29 配線基板及びその製造方法

Country Status (1)

Country Link
JP (1) JP5043563B2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5342422B2 (ja) * 2009-12-10 2013-11-13 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN102378484B (zh) * 2010-08-13 2017-02-08 雅达电子有限公司 提高焊点可靠性方法、印刷电路板、封装器件及封装模块
CN105357900A (zh) * 2015-12-03 2016-02-24 北京浩瀚深度信息技术股份有限公司 消除异形smd元器件回流焊接位移的pad设计方法
KR102519736B1 (ko) * 2018-01-17 2023-04-11 주식회사 루멘스 Led 디스플레이 모듈
US20210035898A1 (en) * 2019-07-30 2021-02-04 Powertech Technology Inc. Package structure and manufacturing method thereof
CN212303653U (zh) 2020-03-26 2021-01-05 北京小米移动软件有限公司 芯片、电路板、电路板组件及电子设备
CN113921491A (zh) * 2020-07-08 2022-01-11 北京小米移动软件有限公司 芯片、电路板及电子设备

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0846079A (ja) * 1994-07-28 1996-02-16 Matsushita Electric Ind Co Ltd 半導体装置
JPH11204570A (ja) * 1998-01-08 1999-07-30 Sumitomo Metal Smi Electron Devices Inc 外部入出力端子
JP4366777B2 (ja) * 1999-09-01 2009-11-18 パナソニック株式会社 電子部品
JP2004200187A (ja) * 2002-12-16 2004-07-15 Nikon Corp プリント配線板
JP4541763B2 (ja) * 2004-01-19 2010-09-08 新光電気工業株式会社 回路基板の製造方法
JP2005244149A (ja) * 2004-01-26 2005-09-08 Kyocera Corp 配線基板

Also Published As

Publication number Publication date
JP2009054969A (ja) 2009-03-12

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