JP5020623B2 - パワーオンシステムリセット回路 - Google Patents
パワーオンシステムリセット回路 Download PDFInfo
- Publication number
- JP5020623B2 JP5020623B2 JP2006346016A JP2006346016A JP5020623B2 JP 5020623 B2 JP5020623 B2 JP 5020623B2 JP 2006346016 A JP2006346016 A JP 2006346016A JP 2006346016 A JP2006346016 A JP 2006346016A JP 5020623 B2 JP5020623 B2 JP 5020623B2
- Authority
- JP
- Japan
- Prior art keywords
- power
- signal
- system reset
- memory system
- sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001514 detection method Methods 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 3
- 230000004044 response Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000007257 malfunction Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/20—Initialising; Data preset; Chip identification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
20 論理計数部
30 電圧検知部
40 制御部
41 トリガーパルス発生回路(トリガーパルス発生部)
42 メモリシステム制御手段(メモリシステム制御部)
43 システムリセット発生回路(システムリセット手段)
50 不揮発性メモリシステム
OSC クロック信号
COUNTER カウンター信号
PONRST 電圧検知信号
PONRST2 内部信号
TRG トリガー信号
HVCEN ステータス信号
system reset システムリセット信号
Claims (2)
- 半導体メモリシステムにおける電源投入時のパワーオンシステムリセット回路であって、
電源投入時から電源電圧が所定の電圧に達するまでの間、前記メモリシステム内で発生している動作シーケンスを終了させる処理を繰り返し行うシーケンス終了手段と、
前記動作シーケンスが終了したとき、前記メモリシステムのシステムリセットを行うシステムリセット手段と、を備え、
前記シーケンス終了手段が前記動作シーケンスを示すステータス信号を、前記システムリセット手段に出力し、
前記システムリセット手段は、前記電源電圧が所定の電圧に達したときにシステムリセットを解除することを特徴とするパワーオンシステムリセット回路。 - 前記シーケンス終了手段は、
基準クロックを発生する基準クロック発生部と、
前記基準クロックを計数して、カウンター信号を発生する論理計数部と、
前記電源投入後の電源電圧を検知して、電圧検知信号を発生する電圧検知部と、
前記論理計数部のカウンター信号と前記電圧検知信号とに基づいてトリガーパルス信号を周期的に発生するトリガーパルス発生回路と、
前記トリガーパルス信号に応じて前記メモリシステムの動作シーケンスを終了するメモリシステム制御部と、
を有することを特徴とする請求項1に記載のパワーオンシステムリセット回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006346016A JP5020623B2 (ja) | 2006-12-22 | 2006-12-22 | パワーオンシステムリセット回路 |
KR1020070133486A KR20080059049A (ko) | 2006-12-22 | 2007-12-18 | 반도체 메모리 장치의 파워 온 시스템 리셋 회로 및 그것의파워 온 리셋 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006346016A JP5020623B2 (ja) | 2006-12-22 | 2006-12-22 | パワーオンシステムリセット回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008160399A JP2008160399A (ja) | 2008-07-10 |
JP5020623B2 true JP5020623B2 (ja) | 2012-09-05 |
Family
ID=39660826
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006346016A Active JP5020623B2 (ja) | 2006-12-22 | 2006-12-22 | パワーオンシステムリセット回路 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP5020623B2 (ja) |
KR (1) | KR20080059049A (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101145113B1 (ko) * | 2010-07-19 | 2012-05-14 | 국방과학연구소 | 컨트롤러를 위한 리셋회로 및 이를 이용한 리셋 방법 |
EP3480608B1 (en) * | 2017-09-19 | 2021-01-13 | Shenzhen Goodix Technology Co., Ltd. | Method and system for measuring power-on reset time |
JP6522201B1 (ja) | 2018-05-14 | 2019-05-29 | ウィンボンド エレクトロニクス コーポレーション | 半導体装置 |
JP6811265B2 (ja) | 2019-02-07 | 2021-01-13 | ウィンボンド エレクトロニクス コーポレーション | 基準電圧発生回路、パワーオン検出回路および半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62145411A (ja) * | 1985-12-20 | 1987-06-29 | Fujitsu Ltd | システムリセツト制御方式 |
JP4024812B2 (ja) * | 1995-08-21 | 2007-12-19 | 松下電器産業株式会社 | パワーオン・オフリセット回路及び半導体装置 |
JP2001142792A (ja) * | 1999-11-17 | 2001-05-25 | Ricoh Co Ltd | リセット信号発生回路 |
JP2003050647A (ja) * | 2001-08-08 | 2003-02-21 | Mitsubishi Electric Corp | メモリ装置及びその保護方法 |
JP3998452B2 (ja) * | 2001-10-19 | 2007-10-24 | 三洋電機株式会社 | 不揮発性メモリの制御回路 |
-
2006
- 2006-12-22 JP JP2006346016A patent/JP5020623B2/ja active Active
-
2007
- 2007-12-18 KR KR1020070133486A patent/KR20080059049A/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR20080059049A (ko) | 2008-06-26 |
JP2008160399A (ja) | 2008-07-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102468728B1 (ko) | 리프레쉬 제어 회로, 반도체 메모리 장치 및 그의 동작 방법 | |
JP5852537B2 (ja) | 半導体装置 | |
JP4750564B2 (ja) | リセット信号生成回路 | |
JP4464451B2 (ja) | マイクロコントローラ | |
KR100880831B1 (ko) | 시스템 및 그것의 부트 코드 로딩 방법 | |
US9672893B2 (en) | Semiconductor device configured to generate a refresh pulse for executing a refresh operation in response to the decoded count signal and temperature code | |
JP5020623B2 (ja) | パワーオンシステムリセット回路 | |
JP5037086B2 (ja) | 温度検出装置 | |
KR20160041318A (ko) | 스트로브 신호 인터벌 검출 회로 및 이를 이용한 메모리 시스템 | |
JP2001256790A (ja) | 低電源電圧検知回路 | |
JP4847695B2 (ja) | 不揮発性メモリ素子での電源検出装置及びその検出方法 | |
JP2008310896A (ja) | 不揮発性記憶装置、不揮発性記憶システムおよび不揮発性記憶装置の制御方法 | |
KR101039878B1 (ko) | 전압 발생 회로 | |
US9384794B2 (en) | Semiconductor device and method of operating the same | |
KR100782942B1 (ko) | 일정한 소거수행시간을 제공하는 소거전압 발생회로 및이를 포함하는 불휘발성 반도체 메모리 장치 | |
JP2013030244A (ja) | 半導体装置 | |
TW202238579A (zh) | 半導體記憶體及資料保護方法 | |
JP2012027984A (ja) | 半導体メモリ | |
TWI665681B (zh) | 脈衝產生器、記憶體裝置、具有該記憶體裝置的記憶體系統及該記憶體裝置的內部電源控制方法 | |
JP2005078489A (ja) | マイクロコントローラ装置及びその制御方法 | |
TWI795266B (zh) | 半導體裝置和操作方法 | |
JP5856461B2 (ja) | データ読出装置 | |
CN106297875B (zh) | 一种静态随机存储器的读取方法及系统 | |
JP2005353149A (ja) | 不揮発性半導体記憶装置 | |
KR100924347B1 (ko) | 컬럼 선택 신호 제어 장치 및 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091126 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101025 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120117 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120416 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120605 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120613 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5020623 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150622 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |