JP5020539B2 - フラッシュメモリ素子のフローティングゲート形成方法 - Google Patents
フラッシュメモリ素子のフローティングゲート形成方法 Download PDFInfo
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- JP5020539B2 JP5020539B2 JP2006133229A JP2006133229A JP5020539B2 JP 5020539 B2 JP5020539 B2 JP 5020539B2 JP 2006133229 A JP2006133229 A JP 2006133229A JP 2006133229 A JP2006133229 A JP 2006133229A JP 5020539 B2 JP5020539 B2 JP 5020539B2
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- floating gate
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- 238000000034 method Methods 0.000 title claims description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 229920005591 polysilicon Polymers 0.000 claims description 43
- 238000005530 etching Methods 0.000 claims description 36
- 150000004767 nitrides Chemical class 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000011800 void material Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241001274216 Naso Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Description
110:スクリーン酸化膜
112:ハードマスク用窒化膜
114:ハードマスク用酸化膜
116:ハードマスク用シリコン膜
118:反射防止膜
120:フォトレジストパターン
122:HDP酸化膜
124:トンネル酸化膜
126:フローティングゲート用ポリシリコン膜
Claims (12)
- 半導体基板上にスクリーン酸化膜、ハードマスク用窒化膜、ハードマスク用酸化膜、及びハードマスク用シリコン膜を順次蒸着してパターニングする段階と、
上記パターニングにより露出された上記半導体基板をエッチングしてトレンチを形成すると共に上記ハードマスク用シリコン膜を除去する段階と、
上記トレンチを含む全体構造の上部に酸化膜を蒸着した後、上記ハードマスク用窒化膜をエッチングストッパにして上記酸化膜と上記ハードマスク用酸化膜を除去して平坦化させる段階と、
NH 4 F/HFケミカル溶液を用いて上記ハードマスク用窒化膜をエッチングした後、H 3 PO 4 ケミカル溶液を用いて上記ハードマスク用窒化膜をエッチングするか、またはこれを反復して上記ハードマスク用窒化膜を除去する段階と、
上記スクリーン酸化膜を除去した後にトンネル酸化膜を蒸着し、上記トンネル酸化膜を含む全体構造の上部にフローティングゲート用ポリシリコン膜を蒸着して平坦化させる段階と、
上記トレンチ内の酸化膜をリセスさせた後に上記リセスにより露出された上記フローティングゲート用ポリシリコン膜の上部の角部を丸くエッチングする段階を含むフラッシュメモリ素子のフローティングゲート形成方法。 - さらに、上記スクリーン酸化膜を除去した後にプリ−クリーニングを行う段階を含むことを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- 上記ハードマスク用窒化膜を1000Åの厚さで蒸着することを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- 上記ハードマスク用シリコン膜としてアン−ドープされたアモルファスシリコンを用いることを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- 上記ハードマスク用シリコン膜のエッチングガスとしてCl2、HBr、O2を組み合わせて用いることを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- 上記ハードマスク用窒化膜のスロープ角度が85度以上維持されるように上記ハードマスク用窒化膜をエッチングすることを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- 上記トレンチのスロープ角度が87度以下に維持されるように上記トレンチを形成することを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- HBrとO2を組み合わせたガスをエッチングガスにして上記半導体基板をエッチングして上記トレンチを形成することを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- 上記フローティングゲート用ポリシリコン膜の上部の角部をブランクエッチングすることを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- 上記フローティングゲート用ポリシリコン膜の上部の角部のエッチング時にエッチングガスとしてHBr、Cl2、O2を組み合わせて用いることを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- 上記フローティングゲート用ポリシリコン膜の上部の角部のエッチング時にエッチング選択比は酸化膜:ポリシリコン膜=1:5以上であることを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
- 上記フローティングゲート用ポリシリコン膜の上部の角部をケミカル特性よりスパッタリング特性を強化させたケミカルスパッタリングエッチングすることを特徴とする請求項1に記載のフラッシュメモリ素子のフローティングゲート形成方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2005-0050266 | 2005-06-13 | ||
KR1020050050266A KR100784083B1 (ko) | 2005-06-13 | 2005-06-13 | 플래시 메모리 소자의 플로팅 게이트 형성방법 |
Publications (2)
Publication Number | Publication Date |
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JP2006352091A JP2006352091A (ja) | 2006-12-28 |
JP5020539B2 true JP5020539B2 (ja) | 2012-09-05 |
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JP2006133229A Expired - Fee Related JP5020539B2 (ja) | 2005-06-13 | 2006-05-12 | フラッシュメモリ素子のフローティングゲート形成方法 |
Country Status (4)
Country | Link |
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US (1) | US7297593B2 (ja) |
JP (1) | JP5020539B2 (ja) |
KR (1) | KR100784083B1 (ja) |
CN (1) | CN100407376C (ja) |
Families Citing this family (14)
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KR100645195B1 (ko) * | 2005-03-10 | 2006-11-10 | 주식회사 하이닉스반도체 | 플래쉬 메모리 소자의 제조방법 |
KR100799024B1 (ko) * | 2006-06-29 | 2008-01-28 | 주식회사 하이닉스반도체 | 낸드 플래시 메모리 소자의 제조방법 |
KR101402890B1 (ko) | 2007-11-30 | 2014-06-27 | 삼성전자주식회사 | 비휘발성 기억 소자 및 그 형성 방법 |
US7659569B2 (en) * | 2007-12-10 | 2010-02-09 | Spansion Llc | Work function engineering for FN erase of a memory device with multiple charge storage elements in an undercut region |
KR20090070338A (ko) * | 2007-12-27 | 2009-07-01 | 주식회사 동부하이텍 | 반도체 소자의 플로팅 게이트 제조 방법 |
CN102543697B (zh) * | 2010-12-22 | 2014-02-26 | 中芯国际集成电路制造(上海)有限公司 | 制作电擦除可编程存储器中的隧道氧化层窗口的方法 |
TWI463551B (zh) * | 2012-09-04 | 2014-12-01 | Winbond Electronics Corp | 快閃記憶體的製作方法 |
CN103715146B (zh) * | 2012-10-09 | 2016-08-10 | 华邦电子股份有限公司 | 闪存的制作方法 |
CN104979172B (zh) * | 2014-04-01 | 2018-10-30 | 北京兆易创新科技股份有限公司 | 一种etox结构的闪存的浮栅及其制作方法 |
CN105097681A (zh) * | 2014-05-06 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制备方法、电子装置 |
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CN105789035B (zh) * | 2014-12-24 | 2019-03-26 | 上海格易电子有限公司 | 一种浮栅及其制作方法 |
CN107887390B (zh) * | 2017-11-09 | 2020-06-16 | 上海华力微电子有限公司 | 一种改善闪存单元的工艺集成方法 |
CN113223996A (zh) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Etox结构闪存浮栅填充的方法及其闪存 |
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KR100603249B1 (ko) * | 2003-12-31 | 2006-07-20 | 동부일렉트로닉스 주식회사 | 플래시 메모리의 플로팅 게이트 형성방법 |
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- 2006-05-12 JP JP2006133229A patent/JP5020539B2/ja not_active Expired - Fee Related
- 2006-05-15 US US11/434,414 patent/US7297593B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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CN100407376C (zh) | 2008-07-30 |
JP2006352091A (ja) | 2006-12-28 |
US7297593B2 (en) | 2007-11-20 |
CN1881534A (zh) | 2006-12-20 |
KR100784083B1 (ko) | 2007-12-10 |
KR20060129668A (ko) | 2006-12-18 |
US20060281261A1 (en) | 2006-12-14 |
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