JP5014632B2 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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JP5014632B2
JP5014632B2 JP2006005956A JP2006005956A JP5014632B2 JP 5014632 B2 JP5014632 B2 JP 5014632B2 JP 2006005956 A JP2006005956 A JP 2006005956A JP 2006005956 A JP2006005956 A JP 2006005956A JP 5014632 B2 JP5014632 B2 JP 5014632B2
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copper alloy
barrier metal
metal film
alloy wiring
film
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JP2006005956A
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Japanese (ja)
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JP2007189061A (ja
JP2007189061A5 (enExample
Inventor
健志 古澤
大介 児玉
雅弘 松本
博史 宮崎
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2006005956A priority Critical patent/JP5014632B2/ja
Priority to TW096100146A priority patent/TWI440135B/zh
Priority to KR1020070003795A priority patent/KR20070076465A/ko
Priority to CN2011100673949A priority patent/CN102157489B/zh
Priority to US11/622,767 priority patent/US7700487B2/en
Priority to CN2007100022053A priority patent/CN101000905B/zh
Priority to CN2010101941593A priority patent/CN101872756B/zh
Publication of JP2007189061A publication Critical patent/JP2007189061A/ja
Publication of JP2007189061A5 publication Critical patent/JP2007189061A5/ja
Priority to US12/714,039 priority patent/US7816268B2/en
Priority to US12/880,520 priority patent/US8097948B2/en
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Publication of JP5014632B2 publication Critical patent/JP5014632B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47L—DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL
    • A47L15/00—Washing or rinsing machines for crockery or tableware
    • A47L15/42—Details
    • A47L15/4285—Water-heater arrangements
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47L—DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL
    • A47L15/00—Washing or rinsing machines for crockery or tableware
    • A47L15/0076—Washing or rinsing machines for crockery or tableware of non-domestic use type, e.g. commercial dishwashers for bars, hotels, restaurants, canteens or hospitals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47L—DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL
    • A47L2501/00—Output in controlling method of washing or rinsing machines for crockery or tableware, i.e. quantities or components controlled, or actions performed by the controlling device executing the controlling method
    • A47L2501/06—Water heaters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2006005956A 2006-01-13 2006-01-13 半導体装置および半導体装置の製造方法 Active JP5014632B2 (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP2006005956A JP5014632B2 (ja) 2006-01-13 2006-01-13 半導体装置および半導体装置の製造方法
TW096100146A TWI440135B (zh) 2006-01-13 2007-01-03 半導體裝置及半導體裝置之製造方法
CN2011100673949A CN102157489B (zh) 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法
US11/622,767 US7700487B2 (en) 2006-01-13 2007-01-12 Semiconductor device and manufacturing method of semiconductor device
CN2007100022053A CN101000905B (zh) 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法
CN2010101941593A CN101872756B (zh) 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法
KR1020070003795A KR20070076465A (ko) 2006-01-13 2007-01-12 반도체 장치 및 반도체 장치의 제조 방법
US12/714,039 US7816268B2 (en) 2006-01-13 2010-02-26 Semiconductor device and manufacturing method of semiconductor device
US12/880,520 US8097948B2 (en) 2006-01-13 2010-09-13 Semiconductor device and manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006005956A JP5014632B2 (ja) 2006-01-13 2006-01-13 半導体装置および半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012108616A Division JP5485333B2 (ja) 2012-05-10 2012-05-10 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2007189061A JP2007189061A (ja) 2007-07-26
JP2007189061A5 JP2007189061A5 (enExample) 2009-02-19
JP5014632B2 true JP5014632B2 (ja) 2012-08-29

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US (3) US7700487B2 (enExample)
JP (1) JP5014632B2 (enExample)
KR (1) KR20070076465A (enExample)
CN (3) CN101872756B (enExample)
TW (1) TWI440135B (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5014632B2 (ja) * 2006-01-13 2012-08-29 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
DE102007004867B4 (de) * 2007-01-31 2009-07-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erhöhen der Zuverlässigkeit von kupferbasierten Metallisierungsstrukturen in einem Mikrostrukturbauelement durch Anwenden von Aluminiumnitrid
US20090001584A1 (en) * 2007-06-26 2009-01-01 Sang-Chul Kim Semiconductor device and method for fabricating the same
JP2010087094A (ja) * 2008-09-30 2010-04-15 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP5622433B2 (ja) * 2010-04-28 2014-11-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6300533B2 (ja) * 2014-01-15 2018-03-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US11164970B2 (en) 2014-11-25 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact field plate
US10756208B2 (en) 2014-11-25 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated chip and method of forming the same
US9590053B2 (en) 2014-11-25 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Methodology and structure for field plate design
US10411068B2 (en) 2015-11-23 2019-09-10 Intel Corporation Electrical contacts for magnetoresistive random access memory devices
US9799605B2 (en) 2015-11-25 2017-10-24 International Business Machines Corporation Advanced copper interconnects with hybrid microstructure
US9704804B1 (en) * 2015-12-18 2017-07-11 Texas Instruments Incorporated Oxidation resistant barrier metal process for semiconductor devices
US10923393B2 (en) * 2018-09-24 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts and interconnect structures in field-effect transistors
US11227794B2 (en) * 2019-12-19 2022-01-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for making self-aligned barrier for metal vias In-Situ during a metal halide pre-clean and associated interconnect structure
US12230552B2 (en) * 2021-11-18 2025-02-18 Qualcomm Incorporated Recess structure for padless stack via
CN115274594B (zh) * 2022-09-19 2022-12-16 合肥晶合集成电路股份有限公司 一种半导体结构及其制作方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0547760A (ja) * 1991-08-12 1993-02-26 Hitachi Ltd 半導体集積回路装置、その製造方法およびその製造に用いるスパツタターゲツト
JP2701730B2 (ja) * 1994-02-24 1998-01-21 日本電気株式会社 半導体装置およびその製造方法
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
EP0751567B1 (en) * 1995-06-27 2007-11-28 International Business Machines Corporation Copper alloys for chip interconnections and method of making
JPH11186273A (ja) * 1997-12-19 1999-07-09 Ricoh Co Ltd 半導体装置及びその製造方法
JP3040745B2 (ja) * 1998-01-12 2000-05-15 松下電子工業株式会社 半導体装置及びその製造方法
JP3840650B2 (ja) * 1998-01-21 2006-11-01 株式会社トリケミカル研究所 配線用銅合金膜形成材料および配線用銅合金膜形成方法
JP3149846B2 (ja) 1998-04-17 2001-03-26 日本電気株式会社 半導体装置及びその製造方法
TW408443B (en) * 1998-06-08 2000-10-11 United Microelectronics Corp The manufacture method of dual damascene
KR100329153B1 (ko) * 1998-07-08 2002-03-21 구마모토 마사히로 단자 및 커넥터용 구리합금 및 그 제조방법
KR100385042B1 (ko) * 1998-12-03 2003-06-18 인터내셔널 비지네스 머신즈 코포레이션 내 일렉트로 마이그레이션의 구조물을 도핑으로 형성하는 방법
JP2000208517A (ja) * 1999-01-12 2000-07-28 Fujitsu Ltd 半導体装置の製造方法
JP2000349085A (ja) * 1999-06-01 2000-12-15 Nec Corp 半導体装置及び半導体装置の製造方法
KR20020070443A (ko) * 1999-11-24 2002-09-09 허니웰 인터내셔널 인코포레이티드 전도성 상호연결장치
JP4686008B2 (ja) * 2000-05-31 2011-05-18 株式会社東芝 スパッタリングターゲットとそれを用いたＣｕ膜および電子デバイス
JP2002075995A (ja) 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
KR100385227B1 (ko) * 2001-02-12 2003-05-27 삼성전자주식회사 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법
KR100550505B1 (ko) * 2001-03-01 2006-02-13 가부시끼가이샤 도시바 반도체 장치 및 반도체 장치의 제조 방법
JP3540302B2 (ja) 2001-10-19 2004-07-07 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
JP2004014626A (ja) * 2002-06-04 2004-01-15 Applied Materials Inc シード膜及びその形成方法、Ｃｕ配線及びその形成方法、半導体装置及びその製造方法、並びに半導体装置の製造装置。
JP4647184B2 (ja) * 2002-12-27 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2004349609A (ja) * 2003-05-26 2004-12-09 Renesas Technology Corp 半導体装置およびその製造方法
JP4527393B2 (ja) * 2003-12-26 2010-08-18 株式会社神戸製鋼所 半導体装置用Ｃｕ系合金配線及びその製造方法
JP4832807B2 (ja) * 2004-06-10 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置
JP5012022B2 (ja) * 2004-06-24 2012-08-29 日本電気株式会社 半導体装置及びその製造方法
JP2006165115A (ja) * 2004-12-03 2006-06-22 Toshiba Corp 半導体装置
US7332428B2 (en) * 2005-02-28 2008-02-19 Infineon Technologies Ag Metal interconnect structure and method
JP4589835B2 (ja) * 2005-07-13 2010-12-01 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
JP2007053133A (ja) * 2005-08-15 2007-03-01 Toshiba Corp 半導体装置及びその製造方法
JP5014632B2 (ja) * 2006-01-13 2012-08-29 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

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Publication number Publication date
CN101000905B (zh) 2011-05-18
CN102157489B (zh) 2013-02-06
CN101872756A (zh) 2010-10-27
JP2007189061A (ja) 2007-07-26
TW200735275A (en) 2007-09-16
US20100327449A1 (en) 2010-12-30
US7816268B2 (en) 2010-10-19
KR20070076465A (ko) 2007-07-24
CN102157489A (zh) 2011-08-17
CN101872756B (zh) 2013-01-02
TWI440135B (zh) 2014-06-01
CN101000905A (zh) 2007-07-18
US7700487B2 (en) 2010-04-20
US20100151673A1 (en) 2010-06-17
US8097948B2 (en) 2012-01-17
US20070167010A1 (en) 2007-07-19

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