JP4989528B2 - 表面実装デバイスの実装構造体、そのリペア方法およびプリント基板 - Google Patents

表面実装デバイスの実装構造体、そのリペア方法およびプリント基板 Download PDF

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Publication number
JP4989528B2
JP4989528B2 JP2008061639A JP2008061639A JP4989528B2 JP 4989528 B2 JP4989528 B2 JP 4989528B2 JP 2008061639 A JP2008061639 A JP 2008061639A JP 2008061639 A JP2008061639 A JP 2008061639A JP 4989528 B2 JP4989528 B2 JP 4989528B2
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JP
Japan
Prior art keywords
adhesive
printed circuit
circuit board
surface mount
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008061639A
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English (en)
Japanese (ja)
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JP2009218436A5 (enExample
JP2009218436A (ja
Inventor
誠治 時井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2008061639A priority Critical patent/JP4989528B2/ja
Publication of JP2009218436A publication Critical patent/JP2009218436A/ja
Publication of JP2009218436A5 publication Critical patent/JP2009218436A5/ja
Application granted granted Critical
Publication of JP4989528B2 publication Critical patent/JP4989528B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
JP2008061639A 2008-03-11 2008-03-11 表面実装デバイスの実装構造体、そのリペア方法およびプリント基板 Expired - Fee Related JP4989528B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008061639A JP4989528B2 (ja) 2008-03-11 2008-03-11 表面実装デバイスの実装構造体、そのリペア方法およびプリント基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008061639A JP4989528B2 (ja) 2008-03-11 2008-03-11 表面実装デバイスの実装構造体、そのリペア方法およびプリント基板

Publications (3)

Publication Number Publication Date
JP2009218436A JP2009218436A (ja) 2009-09-24
JP2009218436A5 JP2009218436A5 (enExample) 2011-03-03
JP4989528B2 true JP4989528B2 (ja) 2012-08-01

Family

ID=41190008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008061639A Expired - Fee Related JP4989528B2 (ja) 2008-03-11 2008-03-11 表面実装デバイスの実装構造体、そのリペア方法およびプリント基板

Country Status (1)

Country Link
JP (1) JP4989528B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6665024B2 (ja) * 2016-05-12 2020-03-13 株式会社東海理化電機製作所 モジュール及びその製造方法
US11153970B1 (en) * 2020-07-20 2021-10-19 Atl Technology, Llc Apparatus with electrical components end mounted to printed circuit board
JP7451001B2 (ja) * 2022-01-11 2024-03-18 デンオン機器株式会社 半導体部品分離装置並びにこれを用いた半導体部品分離及び取付方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065664A (ja) * 1992-06-17 1994-01-14 Fujitsu Ltd ベアチップのリペア方法と装置
JP2002271014A (ja) * 2001-03-09 2002-09-20 Hitachi Kokusai Electric Inc 電子部品の実装方法
JP4246095B2 (ja) * 2004-03-31 2009-04-02 三菱電機株式会社 半導体パッケージ実装構造および半導体パッケージ実装方法
JP2008016460A (ja) * 2006-06-30 2008-01-24 Toshiba Corp プリント回路板、電子機器

Also Published As

Publication number Publication date
JP2009218436A (ja) 2009-09-24

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