JP4982382B2 - リセス型ソース/ドレイン領域をsoiウェハに含む半導体形成プロセス - Google Patents
リセス型ソース/ドレイン領域をsoiウェハに含む半導体形成プロセス Download PDFInfo
- Publication number
- JP4982382B2 JP4982382B2 JP2007549384A JP2007549384A JP4982382B2 JP 4982382 B2 JP4982382 B2 JP 4982382B2 JP 2007549384 A JP2007549384 A JP 2007549384A JP 2007549384 A JP2007549384 A JP 2007549384A JP 4982382 B2 JP4982382 B2 JP 4982382B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- box
- gate
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6727—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having source or drain regions connected to bulk conducting substrates
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/028,811 | 2005-01-03 | ||
| US11/028,811 US7091071B2 (en) | 2005-01-03 | 2005-01-03 | Semiconductor fabrication process including recessed source/drain regions in an SOI wafer |
| PCT/US2005/043208 WO2006073624A1 (en) | 2005-01-03 | 2005-11-30 | Semiconductor fabrication process including recessed source/drain regions in an soi wafer |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008527692A JP2008527692A (ja) | 2008-07-24 |
| JP2008527692A5 JP2008527692A5 (cg-RX-API-DMAC7.html) | 2008-10-23 |
| JP4982382B2 true JP4982382B2 (ja) | 2012-07-25 |
Family
ID=36641070
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007549384A Expired - Fee Related JP4982382B2 (ja) | 2005-01-03 | 2005-11-30 | リセス型ソース/ドレイン領域をsoiウェハに含む半導体形成プロセス |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7091071B2 (cg-RX-API-DMAC7.html) |
| JP (1) | JP4982382B2 (cg-RX-API-DMAC7.html) |
| KR (1) | KR101169920B1 (cg-RX-API-DMAC7.html) |
| CN (1) | CN101076924B (cg-RX-API-DMAC7.html) |
| TW (1) | TWI380374B (cg-RX-API-DMAC7.html) |
| WO (1) | WO2006073624A1 (cg-RX-API-DMAC7.html) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7358571B2 (en) * | 2004-10-20 | 2008-04-15 | Taiwan Semiconductor Manufacturing Company | Isolation spacer for thin SOI devices |
| US7659172B2 (en) * | 2005-11-18 | 2010-02-09 | International Business Machines Corporation | Structure and method for reducing miller capacitance in field effect transistors |
| US7422950B2 (en) * | 2005-12-14 | 2008-09-09 | Intel Corporation | Strained silicon MOS device with box layer between the source and drain regions |
| JP2008027942A (ja) * | 2006-07-18 | 2008-02-07 | Oki Electric Ind Co Ltd | 半導体デバイス及びその製造方法 |
| US8167906B2 (en) | 2006-11-01 | 2012-05-01 | Depuy Mitek, Inc. | Suture anchor with pulley |
| US7393751B1 (en) | 2007-03-13 | 2008-07-01 | International Business Machines Corporation | Semiconductor structure including laminated isolation region |
| US20080272432A1 (en) * | 2007-03-19 | 2008-11-06 | Advanced Micro Devices, Inc. | Accumulation mode mos devices and methods for fabricating the same |
| KR101194843B1 (ko) | 2007-12-07 | 2012-10-25 | 삼성전자주식회사 | Ge 실리사이드층의 형성방법, Ge 실리사이드층을포함하는 반도체 소자 및 그의 제조방법 |
| US20100038715A1 (en) * | 2008-08-18 | 2010-02-18 | International Business Machines Corporation | Thin body silicon-on-insulator transistor with borderless self-aligned contacts |
| US8106456B2 (en) * | 2009-07-29 | 2012-01-31 | International Business Machines Corporation | SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics |
| CN102237396B (zh) * | 2010-04-27 | 2014-04-09 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
| US9698054B2 (en) | 2010-10-19 | 2017-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of a p-type field effect transistor |
| CN102856207B (zh) * | 2011-06-30 | 2015-02-18 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
| US8476131B2 (en) | 2011-08-24 | 2013-07-02 | Globalfoundries Inc. | Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same |
| US9059212B2 (en) * | 2012-10-31 | 2015-06-16 | International Business Machines Corporation | Back-end transistors with highly doped low-temperature contacts |
| US9006071B2 (en) | 2013-03-27 | 2015-04-14 | International Business Machines Corporation | Thin channel MOSFET with silicide local interconnect |
| FR3025941A1 (fr) * | 2014-09-17 | 2016-03-18 | Commissariat Energie Atomique | Transistor mos a resistance et capacites parasites reduites |
| US9768254B2 (en) * | 2015-07-30 | 2017-09-19 | International Business Machines Corporation | Leakage-free implantation-free ETSOI transistors |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121659A (en) * | 1998-03-27 | 2000-09-19 | International Business Machines Corporation | Buried patterned conductor planes for semiconductor-on-insulator integrated circuit |
| US6420218B1 (en) * | 2000-04-24 | 2002-07-16 | Advanced Micro Devices, Inc. | Ultra-thin-body SOI MOS transistors having recessed source and drain regions |
| US6396121B1 (en) * | 2000-05-31 | 2002-05-28 | International Business Machines Corporation | Structures and methods of anti-fuse formation in SOI |
| US6930357B2 (en) * | 2003-06-16 | 2005-08-16 | Infineon Technologies Ag | Active SOI structure with a body contact through an insulator |
| JP4446690B2 (ja) * | 2003-06-27 | 2010-04-07 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| US7271453B2 (en) * | 2004-09-20 | 2007-09-18 | International Business Machines Corporation | Buried biasing wells in FETS |
| US7306997B2 (en) * | 2004-11-10 | 2007-12-11 | Advanced Micro Devices, Inc. | Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor |
-
2005
- 2005-01-03 US US11/028,811 patent/US7091071B2/en not_active Expired - Fee Related
- 2005-11-30 KR KR1020077015260A patent/KR101169920B1/ko not_active Expired - Fee Related
- 2005-11-30 WO PCT/US2005/043208 patent/WO2006073624A1/en not_active Ceased
- 2005-11-30 JP JP2007549384A patent/JP4982382B2/ja not_active Expired - Fee Related
- 2005-11-30 CN CN2005800425566A patent/CN101076924B/zh not_active Expired - Fee Related
- 2005-12-21 TW TW094145651A patent/TWI380374B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US7091071B2 (en) | 2006-08-15 |
| CN101076924A (zh) | 2007-11-21 |
| WO2006073624A1 (en) | 2006-07-13 |
| TW200636873A (en) | 2006-10-16 |
| TWI380374B (en) | 2012-12-21 |
| KR101169920B1 (ko) | 2012-08-06 |
| CN101076924B (zh) | 2012-01-18 |
| KR20070094616A (ko) | 2007-09-20 |
| US20060148196A1 (en) | 2006-07-06 |
| JP2008527692A (ja) | 2008-07-24 |
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