JP4974384B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP4974384B2
JP4974384B2 JP2008228822A JP2008228822A JP4974384B2 JP 4974384 B2 JP4974384 B2 JP 4974384B2 JP 2008228822 A JP2008228822 A JP 2008228822A JP 2008228822 A JP2008228822 A JP 2008228822A JP 4974384 B2 JP4974384 B2 JP 4974384B2
Authority
JP
Japan
Prior art keywords
dielectric constant
groove
low dielectric
film
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008228822A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010062465A (ja
JP2010062465A5 (hu
Inventor
猛 若林
一郎 三原
Original Assignee
株式会社テラミクロス
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社テラミクロス filed Critical 株式会社テラミクロス
Priority to JP2008228822A priority Critical patent/JP4974384B2/ja
Publication of JP2010062465A publication Critical patent/JP2010062465A/ja
Publication of JP2010062465A5 publication Critical patent/JP2010062465A5/ja
Application granted granted Critical
Publication of JP4974384B2 publication Critical patent/JP4974384B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
JP2008228822A 2008-09-05 2008-09-05 半導体装置の製造方法 Active JP4974384B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008228822A JP4974384B2 (ja) 2008-09-05 2008-09-05 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008228822A JP4974384B2 (ja) 2008-09-05 2008-09-05 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010062465A JP2010062465A (ja) 2010-03-18
JP2010062465A5 JP2010062465A5 (hu) 2011-05-19
JP4974384B2 true JP4974384B2 (ja) 2012-07-11

Family

ID=42188920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008228822A Active JP4974384B2 (ja) 2008-09-05 2008-09-05 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP4974384B2 (hu)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012009816A (ja) * 2010-05-28 2012-01-12 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2012023259A (ja) * 2010-07-16 2012-02-02 Casio Comput Co Ltd 半導体装置及びその製造方法
JP6062254B2 (ja) * 2013-01-15 2017-01-18 株式会社ディスコ ウエーハの加工方法
JP6491055B2 (ja) * 2015-06-30 2019-03-27 株式会社ディスコ ウエーハの加工方法
JP2017092125A (ja) * 2015-11-05 2017-05-25 株式会社ディスコ ウエーハの加工方法
US11699663B2 (en) 2020-04-27 2023-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme design for wafer singulation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3784776B2 (ja) * 2003-03-10 2006-06-14 沖電気工業株式会社 半導体装置の製造方法
JP2005044901A (ja) * 2003-07-24 2005-02-17 Fuji Electric Holdings Co Ltd 半導体ウェハ分割方法
JP2006156863A (ja) * 2004-12-01 2006-06-15 Hitachi Ltd 半導体装置及びその製造方法
JP2007161784A (ja) * 2005-12-09 2007-06-28 Fujifilm Corp 絶縁膜、化合物、膜形成用組成物及び電子デバイス
JP4193897B2 (ja) * 2006-05-19 2008-12-10 カシオ計算機株式会社 半導体装置およびその製造方法
JP4913563B2 (ja) * 2006-11-22 2012-04-11 株式会社テラミクロス 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2010062465A (ja) 2010-03-18

Similar Documents

Publication Publication Date Title
JP4666028B2 (ja) 半導体装置
JP4596001B2 (ja) 半導体装置の製造方法
JP2010283367A (ja) 半導体装置の製造方法
JP4193897B2 (ja) 半導体装置およびその製造方法
JP4538764B2 (ja) 半導体装置およびその製造方法
JP5393722B2 (ja) 半導体装置
US8871627B2 (en) Semiconductor device having low dielectric insulating film and manufacturing method of the same
JP4974384B2 (ja) 半導体装置の製造方法
JP4956465B2 (ja) 半導体装置の製造方法
JP4645863B2 (ja) 半導体装置の製造方法
JP2008130886A (ja) 半導体装置の製造方法
JP4913563B2 (ja) 半導体装置の製造方法
JP5004907B2 (ja) 半導体装置の製造方法
US20090079072A1 (en) Semiconductor device having low dielectric insulating film and manufacturing method of the same
JP2010093273A (ja) 半導体装置の製造方法
JP2012023259A (ja) 半導体装置及びその製造方法
JP4770892B2 (ja) 半導体装置の製造方法
JP5001884B2 (ja) 半導体装置およびその製造方法
JP2009135421A (ja) 半導体装置およびその製造方法
JP2008277639A (ja) 半導体装置およびその製造方法
JP2009135420A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110401

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110406

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20111129

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120312

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120406

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120409

R150 Certificate of patent or registration of utility model

Ref document number: 4974384

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150420

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250