JP4949013B2 - 温度感知装置を備えた半導体メモリ素子及びその駆動方法 - Google Patents
温度感知装置を備えた半導体メモリ素子及びその駆動方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 48
- 238000000034 method Methods 0.000 title claims description 10
- 230000004044 response Effects 0.000 claims description 52
- 230000000737 periodic effect Effects 0.000 claims description 22
- 230000001934 delay Effects 0.000 claims description 5
- 230000003111 delayed effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 12
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006880 cross-coupling reaction Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000006903 response to temperature Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
- G01K13/00—Thermometers specially adapted for specific purposes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5002—Characteristic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4061—Calibration or ate or cycle tuning
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Description
続いて、MPRレジスタ200は、N番目の温度値[N]th ODTS Dataとして温度感知部100の出力値「T」を保存する。
200 MPRレジスタ
300 出力ドライバー
400 初期化制御部
Claims (15)
- 駆動信号に応答して温度を感知する温度感知手段と、
該温度感知手段の出力を保存した後、これを温度値として出力する保存手段と、
前記駆動信号がアクティブになってから一定時間後に前記保存手段に保存された値が初期化されるように制御する初期化制御手段と
を備えたことを特徴とする半導体メモリ素子の温度感知装置。 - 前記初期化制御手段が、
前記駆動信号に応答して自体の出力信号をセットし、リセット信号に応答して前記自体の出力信号をリセットするラッチと、
該ラッチの出力信号がアクティブになっている間、周期信号を生成する周期信号生成部と、
該周期信号のアクティブ回数をカウントするカウンタと、
該カウンタの出力信号に応答して初期化信号及び前記リセット信号をアクティブにする初期化信号生成部と
を備えたことを特徴とする請求項1に記載の半導体メモリ素子の温度感知装置。 - 前記ラッチが、
前記駆動信号を反転させる第1インバータと、
該第1インバータの出力信号を1入力とする第1NANDゲートと、前記リセット信号を1入力とする第2NANDゲートとがクロスカップリングされて実現されることを特徴とする請求項2に記載の半導体メモリ素子の温度感知装置。 - 前記周期信号生成部が、
前記ラッチの出力信号と前記周期信号とを入力とする第3NANDゲートと、
該第3NANDゲートの出力信号を遅延させて前記周期信号として出力する第1インバータチェーンと
を備えたことを特徴とする請求項3に記載の半導体メモリ素子の温度感知装置。 - 前記初期化信号生成部が、
前記カウンタの複数の出力信号を入力とする第4NANDゲートと、
該第4NANDゲートの出力信号を反転させ、前記初期化信号として出力する第2インバータと、
前記第4NANDゲートの出力信号を反転させる第3インバータと、
前記第4NANDゲートの出力信号を遅延させる第2インバータチェーンと、
前記第3インバータ及び前記第2インバータチェーンの出力信号を入力として前記リセット信号を出力する第5NANDゲートと
を備えたことを特徴とする請求項4に記載の半導体メモリ素子の温度感知装置。 - 前記カウンタが、前記周期信号のアクティブ回数をカウントして該当出力信号をアクティブにし、反転された前記リセット信号に応答して前記該当出力信号を初期化させることを特徴とする請求項5に記載の半導体メモリ素子の温度感知装置。
- 前記保存手段が、
前記温度感知手段の出力値を保存して出力アクティブ信号に応答して保存した値を出力し、前記初期化制御手段の初期化信号に応答して前記保存された値を初期化させるレジスタと、
該レジスタの出力値を前記温度値にドライブする出力ドライバーと
を備えたことを特徴とする請求項2〜6のいずれかに記載の半導体メモリ素子の温度感知装置。 - 前記レジスタが、前記温度感知手段の出力値を各ビット単位で保存する複数のラッチ部を備えたことを特徴とする請求項7に記載の半導体メモリ素子の温度感知装置。
- 前記ラッチ部が、
前記温度感知手段の該当出力信号をラッチし、前記初期化信号に応答してリセットするラッチ素子と、
前記出力アクティブ信号に応答して前記ラッチ素子の出力データを伝達するトランスファーゲートと
を備えたことを特徴とする請求項8に記載の半導体メモリ素子の温度感知装置。 - 前記温度感知手段が、
前記駆動信号に応答して温度を感知する温度センサと、
上限電圧値及び下限電圧値を供給する電圧供給部と、
前記駆動信号に応答して前記温度センサのアナログ出力値を前記上限電圧値及び前記下限電圧値を基準としてデジタル値に変換して出力するアナログ−デジタル変換部と
を備えたことを特徴とする請求項9に記載の半導体メモリ素子の温度感知装置。 - 前記アナログ−デジタル変換部が、
ループを介して1ビット単位で前記温度センサの出力値をトラッキングして前記デジタル値に変換するトラッキングADCを備えたことを特徴とする請求項10に記載の半導体メモリ素子の温度感知装置。 - 温度感知回路を備えた半導体メモリ装置の駆動方法において、
外部から駆動信号の印加を受けて前記温度を感知する第1ステップと、
該第1ステップの感知した温度値を保存する第2ステップと、
該感知した温度値を出力アクティブ信号に応答して出力する第3ステップと、
駆動信号がアクティブになった後、一定時間後に前記感知した温度値を初期化する第4ステップと
を含むことを特徴とする半導体メモリ装置の駆動方法。 - 温度感知回路を備えた半導体メモリ装置の駆動方法において、
外部から駆動信号の印加を受けて前記温度感知回路を駆動する第1ステップと、
該第1ステップの駆動時間後、一定時間後に前記温度感知回路を初期化する第2ステップと、
前記温度感知回路の保存値を外部に出力する第3ステップと
を含むことを特徴とする半導体メモリ装置の駆動方法。 - 駆動信号に応答して温度を感知して保存する温度感知装置と、
前記駆動信号がアクティブになってから一定の時間がすぎた後、前記温度感知装置に保存された値が初期化されるように制御する初期化制御手段と
を備えたことを特徴とする半導体メモリ素子。 - 前記温度感知装置が、
駆動信号に応答して温度を感知する温度感知手段と、
該温度感知手段の出力を保存した後、これを温度値として出力する保存手段と
を備えたことを特徴とする請求項14に記載の半導体メモリ素子。
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KR1020060049134A KR100719181B1 (ko) | 2006-04-03 | 2006-05-31 | 온도 감지장치를 포함하는 반도체메모리소자 및 그의구동방법 |
KR10-2006-0049134 | 2006-05-31 |
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KR100816150B1 (ko) * | 2007-02-14 | 2008-03-21 | 주식회사 하이닉스반도체 | 온도 감지 장치 |
KR101053510B1 (ko) * | 2008-06-30 | 2011-08-03 | 주식회사 하이닉스반도체 | 반도체 집적회로의 온도/전압 변동 검출 장치 및 방법 |
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DE102006061753B4 (de) | 2016-12-01 |
US7551501B2 (en) | 2009-06-23 |
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US20070242540A1 (en) | 2007-10-18 |
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