五、發明説明（1 相關申請 曰提出之韓國申請號碼 入此間。 本申請宣布優先於2001年5月31 2 001-30522，該申請以參考方式併 發明之背景 本發明關於積體電路裝置，特別關於具有可選擇週期之 時脈之積體電路裝置，及利用此裝置之方法。 眾所周知在積體電路記憶體裝置，包括記憶體裝置儲存 資料係該記憶體以電荷在電容器中儲存資料。此記憶體裝 置典型更新儲存之資料，因電荷可能因為自電容器之漏電 流而遺失。一已知方法稱為更新作業，其中，儲存之資料 完全被擦拭，及資料重復地被摘取及再寫入。此裝置之一 例為動態隨機存取記憶體（DRAM)。此型dram通常無法在 更新作業時存取。DRAM在更新期間無法存取之期間稱為 佔線率。佔線率時間越短越佳。 吾人已知可提供電腦系統或其他裝置包括DRAM 一睡眠模 式，其時，電腦之大部電子電路為關閉以節省功率。但上 述之dram位關閉，因為其必須持續被更新以保持資料。 因此，自行更新電流被允許流經DRAMS，即使電腦之睡眠 杈式亦然。結果，降低自行更新電流最為理想，特別是在 電腦系統由電池操作時為然。 已建議不同方法以降低自行更新電流流經011八乂。一方法 為根據DRAM之分為數範圍之溫度改變DRAM之更新週期。 特別疋，更新時脈之較低週期可在溫度較低時使用，在較 低溫度時，DRAM較易保持資料一較長時間。 本紙張尺度適用t國國家標準(CNS) A4規格(210x 297公 -4- 550567 A7 B7 五、發明説明（2 ) 改變更新週期之一問題為用以決定裝置溫度之溫度偵測 器之特性’可能因為溫度偵測器製造期間之變化，而有大 巾萄變化。結果’可能提供dram —錯誤之溫度量測。例如 ’ DRAM ’可能操做在60。〇，因此需要一高頻率之更新時 脈’但溫度債測器可能錯誤偵測溫度為45它，及較低頻率 之更新時脈。此時，可能發生更新誤差，及導致資料遺失 Q溫度偵測器之變化問題可使用較高性能之偵測器而降低 ’但如此可導致溫度偵測器尺寸之增加。此外，其他製造 方法引進之DRAM之變化可能改變DRAM在各溫度下保持資 料之時間之長度。除此等變化源之外，一 DRAM單元可隨 時間變成過度退化，某些或全部DRAM可能無法成功的更 新’因而導致電腦系統遭遇到全部dram單元之更新失效。 本發明概述 本發明實施例包括時脈產生電路以供包括溫度偵測器電 路之積體電路裝置之用，溫度偵測器電路包括回應溫度編 石馬化唬之校正電路及一溫度偵測器。溫度偵測器電路有一 第一或測試模式裝態，其中，溫度偵測器電路之溫度輸出 仏號係根據溫度偵測器輸出控制信號，及有一第二或正常 才果式狀悲，其中，溫度輸出信號係根據溫度偵測器及校正 電路。一時脈週期控制器電路包括根據溫度輸出信號及時 脈週期控制電路之校正電路，產生一週期控制信號。時脈 產生為電路根據週期控制信號產生一時脈信號。 在本發明進一步實施例中，溫度偵測器電路之校正電路 包括複數個保險絲，溫度編碼信號選擇複數險絲之狀態以 -5- 550567 A7 B7 五、發明説明 校正與溫度偵測器輸出相關 上 之/皿度輪出信號。時脈週期控 制S'電路之;f父正電路亦& # 4 _ ^ 括復數個保險絲，週期編碼信號 k擇復數個包險絲之狀態以校正週期控制信號。 在本發明之其他實施例中，、、西 _ j ^ ，皿度偵測器電路之狀態根據 皿度偵測為輸出信號加以選擇⑺ 二、 k悍，皿度輸出信號可能為一具 有複數個狀態之數位作辦立由 L唬其中之一對應積體電路裝置之溫 度^業範圍。帛_狀態可為測模式，第二狀態可為正常作 業#式。溫度_||輸出控制信號包括複數個位元，其指 疋測4杈式中/皿度作業範圍。數為溫度輸出信號代表積 體電路裝置之偵出溫度溫度偵測器電路尚包括一多工器， 其根據自溫度偵測器及溫度編碼信號之數位溫度信號了輸 出溫度輸出信號。 在本發明之另-實施例中，時脈週期控制電路包括複數 個週期控制器’其由時脈週期控制器電路之校正電路根據 週期編碼信號予以校正。複數個週期控制器之一由溫度輸 出信號選擇以產生週期控制信號。時脈產生器電路可包括 一振盪器，其根據週期控制信號之週期產生時脈信號。積 體電路裝置可為一記憶體裝置，及時脈信號可為一更新時 脈。 在本發明另一實施例中，備有積體電路記憶體裝置，包 括有-回應溫度編碼信號之校正電路之溫度偵感電路，及 一溫度偵測器，其產生一作業溫度信號以回應記憶體裝置 及校正電路之溫度。溫度偵測器電路有一第一狀態，其中 ,溫度偵測器電路之溫度輸出信號係根據溫度偵測器輸出 -6 - 木紙張尺·度適用中國國家標準(CNS) A4規格（210 X 297公釐） 五、發明説明（4 控制信號，及有一第-壯能甘 ，'m — 第-狀心其中’溫度輪出信號為作業 =號。狀態或第二狀態由溫度㈣器輸出控制信 =擇。〜週期控制電路’其包括一校正電路回應週 i扁碼信號，根據溫度輸出信號及時脈㈣控制電路 週期控制信號。時脈產生器電路根據週期 ;V 記憶體裝置之更新時脈。作業溫度信號及溫 又m控制輸出控制信號各包括複數個位元，其一位 對應記憶體裝置之溫度作業範圍。 在本發明之另一實施例中，提供一方法以控制積體電路 記憶體裝置之更新週期。記憶體裝置之溫度偵測器電路校 2後’以輸人-溫度«電路_選擇之溫度編瑪信號以產 2一對應記憶體裝置之-操作溫度之操作溫度信號。溫度 貞測咨電路之測試模式被選擇’其中，溫度谓測器電路之 溫度輪出信號係根據溫度伯測器輸出控制信號，或選擇,、θ =測㈣路”常模式，其t，溫度輸出信號為操作二 又，號。第-狀態或第二狀態由溫度偵測器輸出控制信號 所選擇。记憶體裝置之時脈週期控制器電路校正後，以輸 入至時脈週期控制器電路一週期編碼信號，以產生具有= 週期之週期控制信號。週期控制信號尚根據溫度輸出信 说。兄憶體裝置之更新時脈得以產生’更新時脈之週期係 根據週期控制信號。 ^ 圖式簡略說明 本發明之其他特性可自以下特殊實施例之詳細敘述及配 合伴隨圖式而更為瞭解，其中： 550567V. Description of the Invention (1 The Korean application number filed in the related application is here. This application declares priority over May 31, 2001 2 001-30522. This application is by reference and invents the background. The present invention relates to integrated circuit devices, and particularly to An integrated circuit device having a clock with a selectable period and a method for using the same. It is well known that integrated circuit memory devices, including memory devices, store data in which the memory stores data in capacitors with charge. This memory The device typically updates the stored data because the charge may be lost due to the leakage current from the capacitor. A known method is called the update operation, in which the stored data is completely wiped, and the data is repeatedly extracted and rewritten. This An example of a device is dynamic random access memory (DRAM). This type of dram is usually not accessible during the update operation. The period during which DRAM cannot be accessed during the update is called the busy rate. The shorter the busy rate time, the better. It is known to provide computer systems or other devices including DRAM-sleep mode. At this time, most of the computer's electronic circuits are turned off to save energy. It saves power. But the above-mentioned dram bit is turned off because it must be continuously updated to maintain data. Therefore, self-update current is allowed to flow through the DRAMS, even if the computer sleeps. As a result, it is ideal to reduce the self-update current, especially This is true when the computer system is operated by a battery. Different methods have been proposed to reduce the self-refreshing current flowing through 011A. One method is to change the DRAM update cycle according to the temperature range of the DRAM. In particular, the update clock The lower cycle can be used when the temperature is low, and at lower temperatures, DRAM is easier to retain data for a longer time. This paper size is applicable to National Standards (CNS) A4 specifications (210x 297 male -4- 550567 A7 B7) V. Description of the Invention (2) One of the problems in changing the update period is the characteristics of the temperature detector used to determine the device temperature. 'May be due to changes in the temperature detector during manufacturing. There may be major changes. As a result, a dram may be provided. —Incorrect temperature measurement. For example, 'DRAM' may operate at 60 °. Therefore, a high-frequency update clock is required ', but the temperature debt detector may detect incorrectly. The temperature is 45 °, and the update frequency is lower. At this time, update errors and data loss may occur. Q The temperature detector can be reduced by using higher performance detectors, but this can lead to Increase in the size of the temperature detector. In addition, changes in DRAM introduced by other manufacturing methods may change the length of time that the DRAM retains data at various temperatures. In addition to these sources of change, a DRAM cell can become excessively degraded over time Some or all of the DRAMs may not be successfully updated, thus causing the computer system to experience the failure of all the dram unit updates. SUMMARY OF THE INVENTION Embodiments of the present invention include a clock generation circuit for integrated circuit devices including a temperature detector circuit. The temperature detector circuit includes a correction circuit and a temperature detector in response to the temperature. The temperature detector circuit has a first or test mode state, in which the temperature output number of the temperature detector circuit is based on the output signal of the temperature detector, and there is a second or normal result. Among them, The temperature output signal is based on a temperature detector and a calibration circuit. The clock cycle controller circuit includes a correction circuit based on the temperature output signal and the clock cycle control circuit to generate a cycle control signal. Clock generation is a circuit that generates a clock signal according to the period control signal. In a further embodiment of the present invention, the correction circuit of the temperature detector circuit includes a plurality of fuses, and the temperature-coded signal selects the status of the plurality of fuses as -5- 550567 A7 B7. 5. The invention explains that the correction is related to the output of the temperature detector. The signal is turned out. The clock cycle control S 'circuit; the f positive circuit also includes a plurality of fuses, and the cycle coded signal k selects the state of a plurality of fuses to correct the cycle control signal. In other embodiments of the present invention, the state of the detector circuit is selected as the output signal based on the detector detection. Second, k, the output signal of the detector may be one with a plurality of The status of the digital operation is determined by one of the values corresponding to the temperature range of the integrated circuit device. The 状态 _ state can be the measurement mode, and the second state can be the normal operation # type. Temperature_ || The output control signal includes a plurality of bits, which refers to a 4-range medium / dish operating range. The temperature output signal represents the detected temperature of the integrated circuit device. The temperature detector circuit further includes a multiplexer that outputs an output temperature signal based on the digital temperature signal from the temperature detector and the temperature-encoded signal. In another embodiment of the present invention, the clock cycle control circuit includes a plurality of cycle controllers' which are corrected by the correction circuit of the clock cycle controller circuit based on the cycle coded signal. One of the plurality of cycle controllers is selected by a temperature output signal to generate a cycle control signal. The clock generator circuit may include an oscillator that generates a clock signal according to the period of the period control signal. The integrated circuit device may be a memory device, and the clock signal may be an update clock. In another embodiment of the present invention, an integrated circuit memory device is provided, including a temperature detection circuit having a correction circuit that responds to a temperature-encoded signal, and a temperature detector that generates an operating temperature signal in response to the memory. Temperature of body device and calibration circuit. The temperature detector circuit has a first state. Among them, the temperature output signal of the temperature detector circuit is output according to the temperature detector. -6-Wood paper rule · Degree Applicable to China National Standard (CNS) A4 specification (210 X 297 male) (Centi) 5. Description of the invention (4 control signals, and a first-Zhuang Nenggan, 'm — the first-state of mind where the temperature wheel out signal is the job = number. The state or the second state is output by the temperature control device = control signal = Optional. ~ Cycle control circuit 'which includes a correction circuit responding to the cycle i flat code signal and pulses the control circuit cycle control signal in time according to the temperature output signal. The clock generator circuit responds to the cycle; the V memory device updates the clock. Operation The temperature signal and the temperature control output control signal each include a plurality of bits, one of which corresponds to a temperature operation range of the memory device. In another embodiment of the present invention, a method is provided for controlling an integrated circuit memory device The update cycle. After the temperature detector circuit of the memory device is calibrated 2, the input signal of the temperature-selected circuit is used to produce 2-corresponding to the operating temperature of the memory device. As the temperature signal, the test mode of the temperature test circuit is selected. Among them, the temperature wheel output signal of the temperature sensor circuit is based on the output control signal of the temperature tester, or it is selected, θ = test circuit. The t, temperature output signal is the second and the second operation number. The first state or the second state is selected by the temperature detector output control signal. After the clock cycle controller circuit of the memory device is calibrated, it is input to the clock. The cycle controller circuit encodes a cycle signal to generate a cycle control signal with = cycle. The cycle control signal is still based on the temperature output. The update clock of the memory device can be generated. The cycle of the update clock is based on the cycle control signal. ^ Schematic description of other features of the present invention can be better understood from the detailed description of the following special embodiments and the accompanying drawings, where: 550567
AT ________ B7 五、發明説明（5 ) 圖1為積體電路記憶體裝置之時脈產生電路之方塊圖，其 中之更新時脈週期可根據本發明實施例予以控制； 圖2為一方塊圖’說明本發明實施例之溫度偵測器，其可 用於圖1之電路中； 圖3為一方塊圖，說明本發明之時脈週期控制器，其可用 於圖1之電路中。 本發明詳細說明 本發明現在將以伴隨之圖式詳細說明，圖中顯示本發明 之較佳貫施例。本發明可以不同型式組成，但不應解釋為 對揭示之實施例之限制。反之，實施例之提供可使本發明 之揭不更完全及激底，及可充分傳達本發明之範疇給精於 此技藝人士。圖式中，區域之相對尺寸，為清晰計可能稍 為誇大。應瞭解，元件如層，區域或基板係指，，在，，其他元 件之上，其可能直接位於其件之上或存在著插入元件。反 之田元件係直接在’’另一元件之上時，則無插入元件 存在。應瞭解，當元件被指為彼此耦合，此一耦合可能為 直接或經一或多個插入元件耦合，但，，直接耦合，，則為無插 入元件之耦合。此外，說明之每一實施例包括其互補型實 施例。 本發明將以參考圖1中之實施例予以說明。圖丨說明積體 電路€憶體裝置之一時脈產生電路1〇〇。圖丨所示，積體電 路（半導體）記憶體裝置之時脈產生電路丨〇〇包括溫度偵測器 電路11〇，一時脈週期控制器電路12〇及一時脈產生電路ι3〇 。狐度偵測器電路n 〇包括一校正電路，如複數個保險絲， -8-AT ________ B7 V. Description of the invention (5) Figure 1 is a block diagram of the clock generating circuit of the integrated circuit memory device, in which the update clock cycle can be controlled according to the embodiment of the present invention; Figure 2 is a block diagram ' The temperature detector according to the embodiment of the present invention can be used in the circuit of FIG. 1. FIG. 3 is a block diagram illustrating the clock cycle controller of the present invention, which can be used in the circuit of FIG. 1. Detailed Description of the Invention The present invention will now be described in detail with accompanying drawings, which show preferred embodiments of the invention. The invention may be constituted in different forms, but should not be construed as limiting the disclosed embodiments. On the contrary, the embodiments are provided to make the disclosure of the present invention incomplete and radical, and to fully convey the scope of the present invention to those skilled in the art. In the figure, the relative size of the area may be slightly exaggerated for clarity. It should be understood that an element such as a layer, region or substrate refers to, on, other elements, which may be directly on the element or an intervening element is present. On the other hand, when the field element is directly above another element, no intervening element exists. It should be understood that when components are referred to as being coupled to each other, this coupling may be coupled directly or via one or more intervening components, but, directly coupled, is coupling without intervening components. In addition, each embodiment described includes its complementary embodiment. The invention will be described with reference to the embodiment shown in FIG. Figure 丨 illustrates the integrated circuit, a clock generation circuit 100, a memory device. As shown in the figure, the clock generation circuit of the integrated circuit (semiconductor) memory device includes a temperature detector circuit 110, a clock cycle controller circuit 120, and a clock generation circuit ι30. Fox detector circuit n 〇 includes a correction circuit, such as multiple fuses, -8-
550567 A7 ______ B7 五、發明説明（6 ) 保險絲之狀態選擇後可校正溫度偵測器電路1 1 〇。如圖2所 示’溫度偵測器電路1 1 0尚包括一溫度偵測器2 1 〇。 溫度偵測器電路1 1 0包括第一狀態或測試模式，或稱為 MRS模式，其中電路1 1 〇可予以校正以回應溫度編碼信號 TEMPCODES。例如，TEMPCODES可能為數位信號，其包 括指定待斷之保險絲之複數個位元，以校正與溫度債測器 2 10相關之溫度輸出信號TEMPS，俾溫度輸出信號TEMpS可 正確指出包括時脈產生電路100之積體電路記憶體裝置之溫 度操作範圍。測試模式時，溫度輸出信號係根據溫度偵測 器輸出控制信號TEMPSELECT—TEST，此點將參考圖2敘述 如下。溫度偵測器電路1 10亦有一第二狀態或正常操作模式 ，其中，溫度輸出信號TEMPS係根.據來自溫度偵測器210之 偵測器輸出信號SENOUT，其由溫度偵測器電路11〇之校正 電路所校正。 在測試或MRS模式時，如上所述，輸出之TEMPS被決定 以回應溫度偵測器輸出控制信號TEMPSELECT—TEST。因 此，輸出之TEMPS可選擇性設定，以指出積體電路記憶體 裝置之特殊溫度範圍與溫度偵測器210之偵測器輸出信號 SENOUT無關。如以下及參考圖2所述，TEMPSELECT一TEST 信號亦可用以選擇溫度偵測器電路1 1 0之第二或正常操作模 式，其中，溫度輸出信號TEMPS係回應溫度偵測器210之輸 出 SENOUT 〇 時脈週期控制器電路120根據溫度輸出信號TEMPS產生一 週期控制信號PRDCTRLS。例如，時脈週期控制器電路120 -9- 本紙張足度適用t國國家標準(CNS) A4規格（210X297公釐） 550567 A7 __B7 五、發明説明（7 ) 可用以產生一更新時脈RFRCK，更新週期適於積體電路記 憶體裝置之對應操作溫度範圍，如溫度輸出信號TEMPS所 指出者。時脈週期控制器電路120亦包括一校正電路，以便 在一或多個溫度操作範圍如溫度輸出信號TEMPS所指者校 正週期控制信號PRDCTRLS。校正電路可含複數個保險絲 ，其狀態可由週期編碼信號PRDCODES決定，俾所選擇之 一保險絲可被切斷以校正週期編碼信號PRDCTRLS。在此 實施例中，週期編碼信號PRDCODES可包括複數個位元， 其指定時脈週期控制器120校正電路之對應保險絲之狀態時 脈產生器電路130根據週期控制信號PRDCTRLS，產生一時 脈信號，如更新時脈RFRCK。 本發明之時脈產生電路100將以更詳細方式並參考圖1加 以說明。應瞭解溫度偵測器210之溫度偵測器特性，由於時 脈產生電路100之製造時之製造程序之變化而發生改變。結 果，可能遭遇在指示之操作溫度範為上之誤差。例如，包 括時脈產生電路100之na積體電路（半導體）記憶體裝置之溫 度將錯誤的指示為80°C，但實際操作範圍為100°C。此一情 況可在測試模式時，選擇溫度編碼信號TEMPCODES之值以 切斷溫度偵測器電路110校正電路之一保險絲而解決，俾溫 度偵測器1 1 0能確切指示操作溫度。應瞭解，保險絲可為溫 度偵測器210之一部分，俾輪出SEN0UT可由溫度偵測器電 路110之校正電路所校正，如圖2之實施例所示，或校正電 路可與溫度偵測器210分開，並與輸出SENS0UT相對校正 輸出信號TEMPS。 -10 - 度適用中國國家樣準(CNS) A4規格(210 X 297公釐) 550567 A7 B7 五、發明説明（8 ) " 現在進一步說明溫度編碼信號，其中之溫度編碼信號為 一數位信號，其包括複數個狀態如位元。例如，溫度編碼 信號TEMPCODES可包括界定校正電路之對應保險絲之位元 。此例中，一特定操作溫度範圍如100°C可用為操作溫度。 溫度編碼信號TEMP CODES之值可在000000至1111 11間變化 ，以便在校正溫度下產生對應之理想輸出TEMPS，偵測器 編碼信號TEMPCODES係由六個位元組成。溫度偵測器電路 1 1 0之校正電路中之保險絲，在校正模式時根據輸入溫度編 碼信號TEMPCODES將其切斷，如測試模式一樣。結果，如 溫度偵測器2 1 0所偵出之積體電路記憶體裝置之實際操作溫 度範圍，將在正常操作模式由溫度偵測器輸出控制信號 TEMPSELECT_TEST所選出時，產生一正確溫度輸出信號 TEMPS。 此說明性例中，溫度偵測器輸出控制信號TEMPSELECT_TEST 包括複數個位元，每一位元選擇積體電路記憶體裝置之一 複數個可能操作溫度範圍。例如，積體電路記憶體裝置之 操作溫度條件可能分為三個範圍，即1〇〇。〇，70。(：及40。(：。 一三位元TEMPSELECT_TEST信號可與每一對應三範圍之 一之每一位元共用。同理，溫度輸出信號TEMPS可有三位 元，每一對應積體電路記憶體裝置之一溫度操作範圍。 時脈週期控制器電路120接收一選擇之週期編碼信號 PRDC0DES以供校正目的，及產生週期控制信號 PRDCTRLS以控制更新時脈RFRCK之週期。如圖1及3之實 施例所示，週期控制信號PRDCTRLS亦回應溫度輸出信號 -11 - 本紙張义度適用令國國家標準(CNS) A4規格（210 X 297公釐） 550567 A7 B7 _ _ 五、發明説明（9 ) TEMPS之複敫個位元（3)中之一激活位元。 如溫度偵測器電路11 〇之校正電路所述，週期編碼信號 PRDCODES可包括複數個位元用以校正時脈週期控制器120 ，以輸出理想週期控制信號PRDCTRLS。例如，六位元之 週期編碼信號PRDCODES可用以改變週期控制信號 PRDCTRLS，即經改變週期編碼信號PRDCODES以設定更 新時脈RFRCEC之理想週期。例如，時脈產生電路100可經校 正以便在週期編碼信號PRDCODES在000000至111111變化 時，提供更新週期範圍在l〇ms-100ms之記憶體之6K位元組 之更新。如圖3所示，利用共同PRDCODES輸入，可提供每 一三溫度範圍之校正。因與TEMPS信號有關之每一溫度範 圍，及相關之保險絲或在時脈週期控制器電路120中之其他 校正電路，可能被切斷以提供更新時脈RFRCK之理想更新 週期。或者，PRDCODES信號可能為一輸入，根據PRDCODES 信號之現在狀態以控制輸出PRDCTRLS，以提供時脈週期 控制器120之校正，而非由相關保險絲之編碼。 時脈產生器130接收週期控制信號PRDCTRLS及產生適於 積體電路記憶體裝置之指示操作溫度範圍之更新時脈 RFRCK。本發明各實施例中，時脈產生器130包括一振盪器 以接收週期控制信號PRDCTRLS，及產生具有理想週期之 更新時脈RFRCK。振盪器可持續改變更新時脈RFRCK之週 期。時脈產生器130可含一計數器。其可利用較振盪器為快 之計數器以控制更新時脈RFRCK之週期。計數器可持續以 倍數改變更新時脈RFRCK之週期，如基本週期之二倍或三 -12 - 本紙張尺度適用令國國家標準(CNS) A4規格(210 X 297公釐） 550567 A7 B7 五、發明説明（1〇 ) 倍。 本發明之裝置現在將參可圖2之實施例予以進一步說明。 如圖2之實施例所示，溫度偵測器電路1 1 0包括多工器220及 溫度偵測器2 1 0。為說明之計，溫度偵測器2 10之偵測器輸 出信號SENOUT可認為係對應溫度偵測器輸出控制信號 TEMPSELECT—TEST之複數個位元，及對應積體電路記憶 體裝置三個操作範圍（如l〇〇°C，70°C及40。〇之溫度輸出信 號TEMPS之複數個位元（3)。位元無需各別對應一溫度範圍 。例如，偵測器輸出信號SENOUT可為”111’’以操作約100°C 之溫度範圍。同理，供操作70°C及40°C範圍時，偵測器輸 出信號SENOUT可為”011 ”及”001”。 多工器220接收偵測器輸出信號SENOUT及溫度輸出控制 信號TEMPSELECT—TEST，及產生溫度輸出信號TEMPS。 本發明一特殊實施例中，溫度偵測器輸出控制信號 TEMPSELECT—TEST利用複數個位元以控制，由多工器220 選擇之輸出，此點將參考一三位元實施例再予說明。溫度 輸出信號TEMPS僅由溫度偵測器輸出控制信號 TEMPSELECT—TEST決定，在溫度偵測器輸出控制信號 TEMPSELECT—TEST中任一位元有一邏輯”高”值，及另二位 元為”低’’值時，該信號與來自溫度偵測器210之輸出信號 SENOUT無關。溫度輸出信號TEMPS在溫度偵測器輸出控 制信號TEMPSELECT—TEST之所有位元均為”低”值時，由偵 測器輸出信號SENOUT決定。因此，正常操作模式可由設定 TEMPSELECT—TEST均為低值而選擇，俾溫度偵測器21〇之 -13- 本紙張足度適用中國國家標準(CNS) A4規格(210 X 297公釐) 550567 A7 B7 五、發明説明（11 ) 輸出驅動TEMPS信號，以指出積體電路記憶體之裝置之實 際操作溫度範圍。 參考圖3，時脈週期控制器電路1 20實施例將予說明。如 圖3所示，時脈週期控制器電路120包括複數個週期控制器 3 10，320及3 30，以接收週期編碼信號PRDCODES及產生週 期控制信號PRDCTRLS，以控制更新時脈RFRCK之週期。 應瞭解，時脈控制器電路120可包括多個或少於三個週期控 制器。僅有一週期控制器電路310，320及330如圖3所示被 溫度輸出信號TEMPS所啟動。例如，如溫度輸出信號 TEMPS指出在溫度100°C範圍操作，輸入至第一週期控制器 3 10操作溫度信號TEMPS1(例如，對應與溫度範圍有關之 TEMPS信號三位元之一）有一邏輯”高"值，其他操作溫度信 號TEMPS2及TEMPS3(對應其他二操作溫度範圍之TEMPS信 號之另外二位元）有一 ”低”邏輯值。結果，僅有第一個週期 控制器310被啟動，其他二週期控制器320及330為不啟動。 因此，第一週期控制器310產生第一週期控制信號 PRDCTRLS1。第一週期控制信號PRDCTRLS 1於是以週期控 帝J信號PRDCTRLS提供。 如以上不同實施例所述，時脈產生電路100可提供一更新 週期，其控制與溫度偵測之變化及引入積體電路記憶體之 變化無關。因此其可降低積體電路如DRAM之功率消耗及 佔線時間。 應瞭解，許多修改及變化均屬可行而不致有悖本發明之 原理。所有該修改及變化均欲包括於本發明申請專利範圍 之範疇中。 -14 - 本紙張足度適用中國國家標準(CNS) A4規格（210 X 297公釐）550567 A7 ______ B7 V. Description of the invention (6) After the fuse status is selected, the temperature detector circuit 1 1 〇 can be corrected. As shown in FIG. 2, the 'temperature detector circuit 1 10 further includes a temperature detector 2 1 0. The temperature detector circuit 1 10 includes a first state or a test mode, or MRS mode. The circuit 1 10 can be calibrated to respond to the temperature-coded signal TEMPCODES. For example, TEMPCODES may be a digital signal, which includes a plurality of bits designating the fuse to be broken to correct the temperature output signal TEMPS related to the temperature detector 2 10, and the temperature output signal TEMpS can correctly indicate that the clock generation circuit is included Temperature range of 100 integrated circuit memory device. In test mode, the temperature output signal is based on the temperature sensor output control signal TEMPSELECT_TEST. This point will be described below with reference to Figure 2. The temperature detector circuit 1 10 also has a second state or normal operating mode, in which the temperature output signal TEMPS is based. According to the detector output signal SENOUT from the temperature detector 210, it is provided by the temperature detector circuit 11. By the correction circuit. In the test or MRS mode, as described above, the output TEMPS is determined in response to the temperature detector output control signal TEMPSELECT_TEST. Therefore, the output TEMPS can be selectively set to indicate that the special temperature range of the integrated circuit memory device is independent of the detector output signal SENOUT of the temperature detector 210. As described below and with reference to FIG. 2, the TEMPSELECT_TEST signal can also be used to select the second or normal operating mode of the temperature detector circuit 1 1 0, wherein the temperature output signal TEMPS is in response to the output SENOUT of the temperature detector 210. The clock cycle controller circuit 120 generates a cycle control signal PRDCTRLS according to the temperature output signal TEMPS. For example, the clock cycle controller circuit 120 -9- This paper is fully applicable to the national standard (CNS) A4 specification (210X297 mm) 550567 A7 __B7 5. Invention description (7) can be used to generate an updated clock RFRCK, The update period is suitable for the corresponding operating temperature range of the integrated circuit memory device, as indicated by the temperature output signal TEMPS. The clock period controller circuit 120 also includes a correction circuit to correct the period control signal PRDCTRLS over one or more temperature operating ranges such as those indicated by the temperature output signal TEMPS. The correction circuit may include a plurality of fuses, the status of which may be determined by the periodic code signal PRDCODES, and one of the selected fuses may be cut to correct the periodic code signal PRDCTRLS. In this embodiment, the periodic code signal PRDCODES may include a plurality of bits, which specify the state of the corresponding fuse of the clock cycle controller 120 correction circuit. The clock generator circuit 130 generates a clock signal according to the cycle control signal PRDCTRLS, such as Update the clock RFRCK. The clock generating circuit 100 of the present invention will be explained in more detail and with reference to FIG. It should be understood that the characteristics of the temperature detector of the temperature detector 210 change due to changes in the manufacturing process of the clock generation circuit 100 during manufacture. As a result, errors in the indicated operating temperature range may be encountered. For example, the temperature of the na integrated circuit (semiconductor) memory device including the clock generation circuit 100 will incorrectly indicate 80 ° C, but the actual operating range is 100 ° C. This situation can be solved in the test mode by selecting the value of the temperature coding signal TEMPCODES to cut off one of the fuses of the temperature detector circuit 110 calibration circuit. The temperature detector 1 1 0 can accurately indicate the operating temperature. It should be understood that the fuse can be a part of the temperature detector 210, and the SENOUT can be corrected by the correction circuit of the temperature detector circuit 110, as shown in the embodiment of FIG. 2, or the correction circuit can be connected with the temperature detector 210. Separate and correct the output signal TEMPS relative to the output SENSOUT. -10-Degree applies to China National Standard (CNS) A4 specification (210 X 297 mm) 550567 A7 B7 V. Description of the invention (8) Now, the temperature-encoded signal will be further explained, in which the temperature-encoded signal is a digital signal. It includes multiple states such as bits. For example, the temperature-coded signal TEMPCODES may include bits defining a corresponding fuse of the correction circuit. In this example, a specific operating temperature range, such as 100 ° C, can be used as the operating temperature. The value of the temperature-coded signal TEMP CODES can be changed from 000000 to 1111 11 in order to generate the corresponding ideal output TEMPS at the corrected temperature. The detector-coded signal TEMPCODES is composed of six bits. The fuse in the calibration circuit of the temperature detector circuit 110 is cut off according to the input temperature coding signal TEMPCODES in the calibration mode, as in the test mode. As a result, the actual operating temperature range of the integrated circuit memory device detected by the temperature detector 2 10 will generate a correct temperature output signal when the temperature detector output control signal TEMPSELECT_TEST is selected in the normal operation mode. TEMPS. In this illustrative example, the temperature detector output control signal TEMPSELECT_TEST includes a plurality of bits, and each bit selects one of the integrated circuit memory devices and a plurality of possible operating temperature ranges. For example, the operating temperature conditions of integrated circuit memory devices may be divided into three ranges, namely 100. 〇, 70. (: And 40. (:. A three-bit TEMPSELECT_TEST signal can be shared with each bit in each corresponding one of the three ranges. Similarly, the temperature output signal TEMPS can have three bits, each corresponding to the integrated circuit memory One of the operating temperature ranges of the device. The clock cycle controller circuit 120 receives a selected period coded signal PRDC0DES for correction purposes, and generates a period control signal PRDCTRLS to control the period of updating the clock RFRCK. As shown in the embodiments of FIGS. 1 and 3 As shown, the cycle control signal PRDCTRLS also responds to the temperature output signal -11-This paper is applicable to the national standard (CNS) A4 specification (210 X 297 mm) 550567 A7 B7 _ _ 5. Description of the invention (9) of TEMPS One of the bits (3) is activated. As described in the correction circuit of the temperature detector circuit 110, the period coded signal PRDCODES may include a plurality of bits for correcting the clock cycle controller 120 to Output the ideal period control signal PRDCTRLS. For example, a six-bit period code signal PRDCODES can be used to change the period control signal PRDCTRLS, that is, the period code signal PRDCODES is changed to set the update The ideal period of the pulse RFRCEC. For example, the clock generating circuit 100 may be corrected to provide 6K bytes of update in the memory with an update period ranging from 10ms to 100ms when the period coded signal PRDCODES changes from 000000 to 111111. As shown in Figure 3, the use of a common PRDCODES input can provide corrections for every three temperature ranges. Because of each temperature range related to the TEMPS signal, and related fuses or other correction circuits in the clock cycle controller circuit 120 May be cut off to provide an ideal update period for updating the clock RFRCK. Or, the PRDCODES signal may be an input, and the output PRDCTRLS is controlled according to the current state of the PRDCODES signal to provide the correction of the clock cycle controller 120 instead of The coding of the relevant fuse. The clock generator 130 receives the period control signal PRDCTRLS and generates an updated clock RFRCK suitable for the integrated operating temperature range of the integrated circuit memory device. In each embodiment of the present invention, the clock generator 130 includes a The oscillator receives the cycle control signal PRDCTRLS and generates an updated clock RFRCK with an ideal cycle. The oscillator can The cycle of updating the clock RFRCK is continuously changed. The clock generator 130 may include a counter. It can use a counter faster than the oscillator to control the cycle of updating the clock RFRCK. The counter can continuously change the cycle of updating the clock RFRCK by a multiple. For example, double the basic period or three to 12-This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) 550567 A7 B7 5. The invention description (10) times. The device of the present invention will now be further described with reference to the embodiment of FIG. 2. As shown in the embodiment of FIG. 2, the temperature detector circuit 110 includes a multiplexer 220 and a temperature detector 210. For illustrative purposes, the detector output signal SENOUT of the temperature detector 2 10 can be considered to correspond to a plurality of bits corresponding to the temperature detector output control signal TEMPSELECT-TEST, and to the three operating ranges of the integrated circuit memory device (Such as 100 ° C, 70 ° C and 40 ° temperature output signal TEMPS multiple bits (3). The bit does not need to correspond to a temperature range. For example, the detector output signal SENOUT can be " 111 "to operate a temperature range of about 100 ° C. Similarly, when operating in the range of 70 ° C and 40 ° C, the detector output signal SENOUT can be" 011 "and" 001 ". The multiplexer 220 receives the detection signal. The detector output signal SENOUT and the temperature output control signal TEMPSELECT_TEST, and the temperature output signal TEMPS are generated. In a special embodiment of the present invention, the temperature detector output control signal TEMPSELECT_TEST is controlled by a plurality of bits, which is controlled by multiplexing. The output selected by the detector 220 will be explained with reference to a three-bit embodiment. The temperature output signal TEMPS is determined only by the temperature detector output control signal TEMPSELECT-TEST, and the temperature detector outputs the control signal TEMP When one of the bits in SELECT-TEST has a logic "high" value and the other two bits have a "low" value, this signal is independent of the output signal SENOUT from the temperature detector 210. The temperature output signal TEMPS is When all the bits of the detector output control signal TEMPSELECT_TEST are “low”, it is determined by the detector output signal SENOUT. Therefore, the normal operation mode can be selected by setting the TEMPSELECT_TEST to be all low values. 俾 Temperature detection器 -21〇 之 -13- This paper is fully compliant with Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 550567 A7 B7 V. Description of the invention (11) The output drives the TEMPS signal to indicate the integrated circuit memory. The actual operating temperature range of the device. Referring to FIG. 3, an embodiment of the clock cycle controller circuit 120 will be described. As shown in FIG. 3, the clock cycle controller circuit 120 includes a plurality of cycle controllers 3 10, 320, and 3 30. Receive the cycle code signal PRDCODES and generate the cycle control signal PRDCTRLS to control the cycle of updating the clock RFRCK. It should be understood that the clock controller circuit 120 may include multiple or fewer than three cycle controllers. Only one cycle controller circuit 310, 320, and 330 is activated by the temperature output signal TEMPS as shown in Figure 3. For example, if the temperature output signal TEMPS indicates operation in a temperature range of 100 ° C, input to the first cycle controller 3 10 operation The temperature signal TEMPS1 (for example, corresponding to one of the three bits of the TEMPS signal related to the temperature range) has a logic "high" value, and other operating temperature signals TEMPS2 and TEMPS3 (the other two bits corresponding to the other two operating temperature range TEMPS signals) ) There is a "low" logic value. As a result, only the first cycle controller 310 is activated, and the other two cycle controllers 320 and 330 are not activated. Therefore, the first period controller 310 generates a first period control signal PRDCTRLS1. The first period control signal PRDCTRLS 1 is then provided by the period control J signal PRDCTRLS. As described in the above different embodiments, the clock generating circuit 100 can provide an update period, and its control is independent of changes in the temperature detection and changes introduced in the integrated circuit memory. Therefore, it can reduce the power consumption and busy time of integrated circuits such as DRAM. It should be understood that many modifications and variations are possible without departing from the principles of the invention. All such modifications and changes are intended to be included within the scope of the patent application of the present invention. -14-This paper is fully compliant with China National Standard (CNS) A4 (210 X 297 mm)