KR19980083772A - Semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory. In the conventional semiconductor memory, since the internal row address strobe has a short high potential period and a short operation period, the time required to apply a high voltage to the actual word line is short compared to the burn time test result. In addition to the problem of decreasing the reliability of the word line, when a high voltage is applied to all the word lines by the word line controller, the word line is enabled only once, and other circuits such as a redundancy circuit cannot be burned in. There was a problem that the use efficiency is reduced. In view of the above problem, the present invention senses a burn-in test and uses the high-potential section and the inverted internal row address strobe having a long operating section inverted during the burn-in test. By enabling the line at the same time and burn-in test, the burn-in test time is shortened.

Description

Semiconductor memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory. In particular, internal row address signals used in a burn-in test and a general operation are inverted. The burn-in test time is improved by enabling all word lines at the same time. The present invention relates to a semiconductor memory suitable for shortening.

In general, the semiconductor memory performs burn-in tests that apply a voltage higher than the actual voltage to prevent initial failure, and according to the test result, the main memory cell which is abnormal is replaced with a memory cell manufactured in the semiconductor memory. The present invention will be commercialized, and will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a conventional semiconductor memory, and as shown therein, a self-refresh control unit 2 for determining a refresh cycle by applying different voltages according to bonding pad states of a power supply controller 1; A row address strobe (/ RAS), a column address strobe (/ CAS), a write enable signal (/ WE), a read enable signal (/ OE), and an address signal (ADD) are received, and the self refresh control unit 2 receives the A word line controller (3) for outputting a word line control signal in accordance with the output signal; A word line decoder (4) for receiving and decoding a word line control signal of the word line control unit (3) and outputting a word line selection signal; A row address strobe (/ RAS), a column address strobe (/ CAS), a write enable signal (/ WE), a read enable signal (/ OE), and an address signal (ADD) are received, and the self refresh control unit 2 receives the A bit line controller 6 for outputting a bit line control signal in accordance with the output signal; A bit line decoder 7 for receiving the bit line control signal of the bit line controller 6 and decoding the bit line control signal to output a bit line selection signal; A memory cell unit (5) for selecting a specific memory cell according to the word line selection signal and the bit line selection signal to store data in the specific memory cell or to output stored data; An input / output control unit 8 for controlling data input / output of the memory cell unit 5; The word line control unit 11 is configured to enable all word lines of the memory cell unit 5 simultaneously according to an external control signal TWSAT.

Hereinafter, the operation of the conventional semiconductor memory configured as described above will be described in detail.

First, FIG. 2 is an input / output waveform diagram of a main part of a conventional semiconductor memory. As shown in FIG. 2, a row address strobe (/ RAS), a column address strobe (/ CAS), and the row address strobe (/ RAS) of the same period are shown. And the self refresh enable signal 2 which receives the self refresh enable signal PSRB input at high potential when the column address strobe (/ CAS) is at low potential, is used in the burn-in mode, and the self refresh enable signal PSRB The burn-in test period is determined by outputting an internal row address strobe (/ RASIN) to have a plurality of periods in the high potential period. At this time, the burn-in test period operates one word line of the memory cell unit 5 every 4K, that is, 4096 cycles, or operates one word line of the memory cell unit 5 every 2K, that is, 2048 cycles. The internal row address strobe (/ RASIN) determines the self refresh period during normal operation of the semiconductor memory, and determines the burn-in test period during the burn-in test.

Then, the internal line address strobe (/ RASIN) of the self-refresh control unit 2, the word line control unit 3 receiving the row address strobe (/ RAS) and the address signal (ADD) outputs a control signal, A specific word line of the memory cell unit 5 is selected by the word line decoder 4 which decodes the control signal and outputs a word line selection signal.

Next, the bit line is selected by decoding the output signal of the self refresh control unit 2 and the control signal of the bit line control unit 6 which receives and processes the column address strobe (/ CAS) and the address signal ADD. Data of a specific memory cell in which the word line is selected by the bit line decoder 7 which outputs a signal is output through the input / output control unit 8.

In addition, the internal row address strobe of the self-refresh control unit 2 may be used in a burn-in test for applying a power higher than a value of a power supply voltage actually used to test the initial failure of the semiconductor memory. / RASIN) determines the burn-in test time. In other words, if the burn-in test time is set to 12 hours, if the refresh period is 4K, one word line receives a high voltage during the burn-in test for about 10.5 seconds (12 hours / 4096), and the refresh period is 2K. In this case, one word line receives a high voltage for about 42 seconds (12 hours / 2048).

3 is an input / output waveform diagram of all the word line controllers 11. As shown in FIG. 3, when the external control signal TWSAT is input, the high word of the control signal TWSAT is applied. By enabling all word lines in the above section, each word line is generally supplied with a power supply voltage higher than the power supply voltage commonly used in semiconductor memories.

However, as described above, in the conventional semiconductor memory, since the internal row address strobe has a short high potential period and a short operation period, the time required to apply a high voltage to the actual word line is shorter than that of the burn-in test time. In addition to reducing the problem, when the high voltage is applied to the entire word line by the whole word line controller, the burn-in test is enabled only once, and other circuits such as a redundancy circuit cannot be used for the burn-in test. There was a problem that the efficiency is reduced.

In consideration of such a problem, the present invention uses an internal row address strobe having a short high-frequency period and a short operation period in a general operation of a semiconductor memory, and detects a burn-in test during burn-in tests, It is an object of the present invention to provide a semiconductor memory in which the short internal row address strobe is inverted to be suitable for reducing burn-in test time by using an internal row address strobe having a high potential period and a long operation period.

1 is a block diagram of a conventional semiconductor memory.

Figure 2 is a waveform diagram of the main part in Figure 1;

3 is an input / output waveform diagram of the word line controller in FIG.

4 is a block diagram of a semiconductor memory according to the present invention;

FIG. 5 is a waveform diagram of the main part of FIG. 4; FIG.

* Description of the symbols for the main parts of the drawings *

1: power control unit 3: word line control unit

4: word line decoder 5: memory cell unit

6: bit line control unit 7: bit line decoder

8: I / O control unit 9: Self refresh control unit

10: burn-in detection unit 11: all word line control unit

The above object includes a burn-in test detector for recognizing operation in a burn-in test mode and outputting an output signal according to the above, and if the output signal of the burn-in test detector is an output signal indicating a burn-in test time, the internal row address strobe is inverted. It is achieved by configuring a self-refresh control unit for outputting the same, and the semiconductor memory according to the present invention will be described in detail with reference to the accompanying drawings.

Figure 4 is a block diagram of a semiconductor memory according to the present invention, and burn-in detection unit 10 for detecting the burn-in test signal as shown therein; The internal row address strobe (/ RASIN) is determined according to the bonding pad state of the power control unit 1, and the self-inverter outputs the internal row address strobe (/ RASIN) inverted or directly according to the output signal of the burn-in detection unit 10. A refresh control unit 9; A row address strobe (/ RAS), a column address strobe (/ CAS), a write enable signal (/ WE), a read enable signal (/ OE), and an address signal (ADD) are received, and the self refresh control unit 9 receives the A word line controller (3) for outputting a word line control signal in accordance with an internal row address strobe (/ RASIN); A word line decoder (4) for receiving and decoding a word line control signal of the word line control unit (3) and outputting a word line selection signal; A row address strobe (/ RAS), a column address strobe (/ CAS), a write enable signal (/ WE), a read enable signal (/ OE), and an address signal (ADD) are received, and the self refresh control unit 9 receives the A bit line controller 6 for outputting a bit line control signal in accordance with an internal row address strobe (/ RASIN); A bit line decoder 7 for receiving the bit line control signal of the bit line controller 6 and decoding the bit line control signal to output a bit line selection signal; A memory cell unit (5) for selecting a specific memory cell according to the word line selection signal and the bit line selection signal to store data in the specific memory cell or to output stored data; An input / output control unit 8 for controlling data input / output of the memory cell unit 5; The word line control unit 11 is configured to enable all word lines of the memory cell unit 5 simultaneously according to an external control signal TWSAT.

Hereinafter, the operation of the semiconductor memory according to the present invention configured as described above will be described.

First, the self-refresh control unit 9, which is supplied with the voltage of the power supply control unit 1 and the row address strobe (/ RAS) and the column address strobe (/ CAS) when not in the burn-in test, is operated in the same manner as before. An internal row address strobe (/ RASIN) having a short high potential period is output. When the burn-in test is not detected by the burn-in detector 10, the internal row address strobe (/ RASIN) is output. The internal line address strobe (/ RASIN), the row address strobe (/ RAS) and the address signal ADD applied to the word refresh controller 3 output the control signal. A specific word line of the memory cell unit 5 is selected by a word line decoder 4 which decodes a control signal and outputs a word line selection signal. The word line decoder 4 and the internal row address strobe (/ RASIN) of the self refresh control unit 9 are selected. The word is transmitted by the bit line decoder 7 which decodes a control signal of the bit line controller 6 which receives and processes a column address strobe / CAS and an address signal ADD and outputs a bit line selection signal. Data of a specific memory cell in which a line is selected is output through the input / output controller 8.

Next, FIG. 5 is an input / output waveform diagram of a main part of the semiconductor memory according to the present invention. As shown in FIG. 5, when the burn-in test is performed, the burn-in detection unit 10 outputs an output signal indicating that the burn-in test mode is performed. The refresh control unit 9 receives an output signal of the power control unit 1, an internal row address strobe having a short operation period and a high potential section generated by receiving a row address strobe (/ RAS) and a column address strobe (/ CAS). Invert (/ RASIN) to output an inverted internal row address strobe (RASIN) with a long operating period and a high potential period. The external control signal TWSAT of the inverted internal row address strobe RASIN of the self refresh control unit 9 is input to the all-word line control unit 11. Accordingly, all word lines WL0 to WLn of the memory cell unit 5 are enabled at the time of operation of the internal row address strobe RASIN, and thus all word lines WL0 to WLn are higher than commercial power voltages. All the word lines WL0 to WLn can be burned-in at the same time by applying the power supply voltage.

As described above, the semiconductor memory according to the present invention uses different internal row address signals used during burn-in test and normal operation, and increases the time for applying a high voltage to the word line during the same burn-in test time. In addition to improving reliability, the burn-in test time can be shortened by enabling all word lines at the same time according to the internal row address signal used in the burn-in test, and the peripheral circuits such as redundancy cells can be tested. .

Claims (1)

Burn-in detection means for detecting a burn-in test signal; Self refresh control means for generating an internal row address strobe and inverting or directly outputting the internal row address strobe according to an output signal of the burn-in sensing means; Word line control means for receiving a row address strobe, a column address strobe, a write enable signal, a read enable signal, and an address signal and outputting a word line control signal in accordance with an internal row address strobe of the self refresh control means; A word line decoder for receiving a word line control signal of the word line control means and decoding the word line control signal to output a word line selection signal; Bit line control means for receiving a row address strobe, a column address strobe, a write enable signal, a read enable signal, and an address signal and outputting a bit line control signal according to an internal row address strobe of the self refresh control means; A bit line decoder for receiving a bit line control signal of the bit line control means and decoding the bit line control signal to output a bit line selection signal; A memory cell unit configured to select a specific memory cell according to the word line selection signal and the bit line selection signal to store data in the specific memory cell or output stored data; Input / output control means for controlling data input / output of the memory cell unit; And all word line control means for enabling all word lines of the memory cell unit at the same time according to an external control signal.