JP4926963B2 - 多重メモリアクセスレイテンシ時間をサポートするコンピュータメモリシステムにおける性能を改善するためのシステムおよび方法 - Google Patents

多重メモリアクセスレイテンシ時間をサポートするコンピュータメモリシステムにおける性能を改善するためのシステムおよび方法 Download PDF

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JP4926963B2
JP4926963B2 JP2007527567A JP2007527567A JP4926963B2 JP 4926963 B2 JP4926963 B2 JP 4926963B2 JP 2007527567 A JP2007527567 A JP 2007527567A JP 2007527567 A JP2007527567 A JP 2007527567A JP 4926963 B2 JP4926963 B2 JP 4926963B2
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latency time
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ウー，スティーブン，シー．
エイチ． ツァン，ブライアン
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
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  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2007527567A 2004-05-21 2005-05-20 多重メモリアクセスレイテンシ時間をサポートするコンピュータメモリシステムにおける性能を改善するためのシステムおよび方法 Expired - Fee Related JP4926963B2 (ja)

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US10/850,803 US7222224B2 (en) 2004-05-21 2004-05-21 System and method for improving performance in computer memory systems supporting multiple memory access latencies
US10/850,803 2004-05-21
PCT/US2005/018246 WO2005114669A2 (en) 2004-05-21 2005-05-20 System and method for improving performance in computer memory systems supporting multiple memory access latencies

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JP2008500668A5 JP2008500668A5 (https=) 2008-05-29
JP4926963B2 true JP4926963B2 (ja) 2012-05-09

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EP (1) EP1754229B1 (https=)
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WO (1) WO2005114669A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11822789B2 (en) 2011-12-27 2023-11-21 Intel Corporation Methods and apparatus to manage workload memory allocation

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6464628B1 (en) * 1999-08-12 2002-10-15 Obtech Medical Ag Mechanical anal incontinence
US6471635B1 (en) * 2000-02-10 2002-10-29 Obtech Medical Ag Anal incontinence disease treatment with controlled wireless energy supply
EP1253880B1 (en) 2000-02-10 2005-09-14 Potencia Medical AG Controlled urinary incontinence treatment
MXPA02007654A (es) 2000-02-10 2004-08-23 Potencia Medical Ag Aparato mecanico para el tratamiento de impotencia.
DE60131726T2 (de) * 2000-02-11 2008-11-06 Potencia Medical Ag Kontrollierte impotenzbehandlung
ATE296071T1 (de) * 2000-02-14 2005-06-15 Potencia Medical Ag Penisprothese
ATE324087T1 (de) 2000-02-14 2006-05-15 Potencia Medical Ag Männliche impotentzprothesevorrichtung mit drahtloser energieversorgung
KR100448717B1 (ko) * 2002-08-02 2004-09-13 삼성전자주식회사 메모리 시스템
US20090118019A1 (en) 2002-12-10 2009-05-07 Onlive, Inc. System for streaming databases serving real-time applications used through streaming interactive video
US9314691B2 (en) 2002-12-10 2016-04-19 Sony Computer Entertainment America Llc System and method for compressing video frames or portions thereof based on feedback information from a client device
US9138644B2 (en) 2002-12-10 2015-09-22 Sony Computer Entertainment America Llc System and method for accelerated machine switching
KR100564635B1 (ko) * 2004-10-25 2006-03-28 삼성전자주식회사 메모리 모듈 내에서의 인터페이스 타이밍을 제어하는메모리 시스템 및 그 방법
US7512762B2 (en) * 2004-10-29 2009-03-31 International Business Machines Corporation System, method and storage medium for a memory subsystem with positional read data latency
US7331010B2 (en) 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
JP2006236105A (ja) * 2005-02-25 2006-09-07 Canon Inc アクセス制御装置及びその制御方法
KR100588599B1 (ko) * 2005-05-03 2006-06-14 삼성전자주식회사 메모리 모듈 및 메모리 시스템
US20070005922A1 (en) * 2005-06-30 2007-01-04 Swaminathan Muthukumar P Fully buffered DIMM variable read latency
US7911834B2 (en) 2006-05-15 2011-03-22 Apple Inc. Analog interface for a flash memory die
US7852690B2 (en) * 2006-05-15 2010-12-14 Apple Inc. Multi-chip package for a flash memory
US7701797B2 (en) * 2006-05-15 2010-04-20 Apple Inc. Two levels of voltage regulation supplied for logic and data programming voltage of a memory device
US8000134B2 (en) 2006-05-15 2011-08-16 Apple Inc. Off-die charge pump that supplies multiple flash devices
US7639542B2 (en) * 2006-05-15 2009-12-29 Apple Inc. Maintenance operations for multi-level data storage cells
US7613043B2 (en) * 2006-05-15 2009-11-03 Apple Inc. Shifting reference values to account for voltage sag
US7568135B2 (en) 2006-05-15 2009-07-28 Apple Inc. Use of alternative value in cell detection
US7639531B2 (en) * 2006-05-15 2009-12-29 Apple Inc. Dynamic cell bit resolution
US7551486B2 (en) * 2006-05-15 2009-06-23 Apple Inc. Iterative memory cell charging based on reference cell value
US7511646B2 (en) * 2006-05-15 2009-03-31 Apple Inc. Use of 8-bit or higher A/D for NAND cell value
JP5065618B2 (ja) * 2006-05-16 2012-11-07 株式会社日立製作所 メモリモジュール
US7496711B2 (en) * 2006-07-13 2009-02-24 International Business Machines Corporation Multi-level memory architecture with data prioritization
US7861140B2 (en) * 2006-10-31 2010-12-28 Globalfoundries Inc. Memory system including asymmetric high-speed differential memory interconnect
US20080104352A1 (en) * 2006-10-31 2008-05-01 Advanced Micro Devices, Inc. Memory system including a high-speed serial buffer
US7788414B2 (en) * 2007-01-16 2010-08-31 Lantiq Deutschland Gmbh Memory controller and method of controlling a memory
US20100185810A1 (en) * 2007-06-12 2010-07-22 Rambus Inc. In-dram cycle-based levelization
US7729168B2 (en) * 2007-06-28 2010-06-01 Intel Corporation Reduced signal level support for memory devices
JP5349775B2 (ja) * 2007-09-07 2013-11-20 キヤノン株式会社 メモリコントローラ及びその制御方法
JP5103663B2 (ja) * 2007-09-27 2012-12-19 ルネサスエレクトロニクス株式会社 メモリ制御装置
JP5188134B2 (ja) * 2007-10-03 2013-04-24 キヤノン株式会社 メモリアクセス制御装置及びメモリアクセス制御方法
US20090157940A1 (en) * 2007-12-15 2009-06-18 Hitachi Global Storage Technologies Netherlands, B.V. Techniques For Storing Data In Multiple Different Data Storage Media
US8825965B2 (en) * 2008-01-08 2014-09-02 Cisco Technology, Inc. System and methods for memory expansion
EP2244759B1 (en) * 2008-01-28 2024-11-27 Implantica Patent Ltd. A filter cleaning device
ES2981249T3 (es) 2008-01-29 2024-10-08 Implantica Patent Ltd Un dispositivo para el tratamiento de la obesidad
US20090215538A1 (en) * 2008-02-22 2009-08-27 Samuel Jew Method for dynamically synchronizing computer network latency
US9072907B2 (en) 2008-10-10 2015-07-07 Peter Forsell Heart help device, system, and method
ES2985873T3 (es) 2008-10-10 2024-11-07 Implantica Patent Ltd Medios de fijación para conjunto de control médico implantable
EP2349170B1 (en) 2008-10-10 2023-09-27 Implantica Patent Ltd. Apparatus for the treatment of female sexual dysfunction
EP2349096B1 (en) 2008-10-10 2021-01-27 MedicalTree Patent Ltd. An improved artificial valve
EP3120896A1 (en) 2008-10-10 2017-01-25 Kirk Promotion LTD. A system, an apparatus, and a method for treating a sexual dysfunctional female patient
AU2009302945C1 (en) 2008-10-10 2016-04-21 Medicaltree Patent Ltd Heart help device, system, and method
US8135723B2 (en) * 2008-11-12 2012-03-13 Microsoft Corporation Leveraging low-latency memory access
US9949812B2 (en) 2009-07-17 2018-04-24 Peter Forsell Vaginal operation method for the treatment of anal incontinence in women
US10952836B2 (en) 2009-07-17 2021-03-23 Peter Forsell Vaginal operation method for the treatment of urinary incontinence in women
US8375180B2 (en) 2010-02-05 2013-02-12 International Business Machines Corporation Storage application performance matching
US8639879B2 (en) * 2010-03-25 2014-01-28 International Business Machines Corporation Sorting movable memory hierarchies in a computer system
JP5314640B2 (ja) 2010-06-21 2013-10-16 ルネサスエレクトロニクス株式会社 半導体装置
US10114746B2 (en) 2010-10-14 2018-10-30 Micron Technology, Inc. Nonvolatile storage using low latency and high latency memory
US8725128B2 (en) 2010-12-10 2014-05-13 Alcatel Lucent Pre-fetching of assets to user equipment
US9081893B2 (en) * 2011-02-18 2015-07-14 Microsoft Technology Licensing, Llc Dynamic lazy type system
US11099982B2 (en) * 2011-03-31 2021-08-24 Oracle International Corporation NUMA-aware garbage collection
US10140208B2 (en) 2011-03-31 2018-11-27 Oracle International Corporation NUMA-aware garbage collection
JP5658082B2 (ja) * 2011-05-10 2015-01-21 ルネサスエレクトロニクス株式会社 半導体装置
WO2013147755A1 (en) * 2012-03-27 2013-10-03 Hewlett-Packard Development Company, L.P. Nonvolatile memory bank groups
TW201403459A (zh) * 2012-04-20 2014-01-16 Enmotus Inc 具有資料管理機制之儲存系統及操作該儲存系統之方法
GB2516435A (en) * 2013-04-05 2015-01-28 Continental Automotive Systems Embedded memory management scheme for real-time applications
KR20140123203A (ko) * 2013-04-11 2014-10-22 삼성전자주식회사 메모리 시스템
US9141541B2 (en) 2013-09-20 2015-09-22 Advanced Micro Devices, Inc. Nested channel address interleaving
WO2015047402A1 (en) * 2013-09-30 2015-04-02 Hewlett-Packard Development Company, L.P. Programming memory controllers to allow performance of active memory operations
GB2518884A (en) * 2013-10-04 2015-04-08 Ibm Network attached storage system and corresponding method for request handling in a network attached storage system
US9547834B2 (en) * 2014-01-08 2017-01-17 Bank Of America Corporation Transaction performance monitoring
US9992090B2 (en) 2014-01-08 2018-06-05 Bank Of America Corporation Data metrics analytics
WO2015164049A1 (en) * 2014-04-25 2015-10-29 Rambus, Inc. Memory mirroring
US9798628B2 (en) 2014-04-25 2017-10-24 Rambus Inc. Memory mirroring
KR20150145465A (ko) * 2014-06-19 2015-12-30 에스케이하이닉스 주식회사 메모리 시스템 및 이의 동작 방법
US9606928B2 (en) 2014-08-26 2017-03-28 Kabushiki Kaisha Toshiba Memory system
KR102076196B1 (ko) * 2015-04-14 2020-02-12 에스케이하이닉스 주식회사 메모리 시스템, 메모리 모듈 및 메모리 모듈의 동작 방법
JP6464916B2 (ja) * 2015-05-12 2019-02-06 富士通株式会社 メモリ装置及びメモリ装置の制御方法
JP6459820B2 (ja) * 2015-07-23 2019-01-30 富士通株式会社 記憶制御装置、情報処理装置、および制御方法
JP6456799B2 (ja) * 2015-08-31 2019-01-23 株式会社メガチップス メモリコントローラ
KR102532581B1 (ko) * 2016-03-17 2023-05-17 에스케이하이닉스 주식회사 메모리 장치를 포함하는 메모리 시스템 및 그의 동작 방법
KR102617843B1 (ko) * 2016-05-13 2023-12-27 에스케이하이닉스 주식회사 메모리 시스템 및 이의 동작 방법
US20180032429A1 (en) * 2016-07-29 2018-02-01 Intel Corporation Techniques to allocate regions of a multi-level, multi-technology system memory to appropriate memory access initiators
DE102016218280B4 (de) * 2016-09-22 2018-07-19 Infineon Technologies Ag Vorrichtung, die einen Überlagerungsmechanismus umfasst, System mit Vorrichtungen, die jeweils einen Überlagerungsmechanismus mit einer individuellen programmierbaren Verzögerung umfassen
US10095421B2 (en) 2016-10-21 2018-10-09 Advanced Micro Devices, Inc. Hybrid memory module bridge network and buffers
US10331581B2 (en) 2017-04-10 2019-06-25 Hewlett Packard Enterprise Development Lp Virtual channel and resource assignment
US10489225B2 (en) 2017-08-10 2019-11-26 Bank Of America Corporation Automatic resource dependency tracking and structure for maintenance of resource fault propagation
US10990525B2 (en) * 2018-12-12 2021-04-27 Mipsology SAS Caching data in artificial neural network computations
WO2020121030A1 (en) * 2018-12-12 2020-06-18 Mipsology SAS Caching data in artificial neural network computations
US11526632B2 (en) 2019-09-04 2022-12-13 Rambus Inc. Securing address information in a memory controller
US11199995B2 (en) * 2019-11-19 2021-12-14 Micron Technology, Inc. Time to live for load commands
US11243804B2 (en) 2019-11-19 2022-02-08 Micron Technology, Inc. Time to live for memory access by processors
US12387769B2 (en) * 2022-05-23 2025-08-12 Changxin Memory Technologies, Inc. Latency adjustment method, memory chip architecture, and semiconductor memory
US12405752B2 (en) 2023-09-26 2025-09-02 Smart Modular Technologies, Inc. Migrating data between byte-addressable and block-addressable storage devices in processor-based devices
US20250110873A1 (en) * 2023-09-29 2025-04-03 Samsung Electronics Co., Ltd. Systems, methods, and apparatus for cache management in a memory device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06266615A (ja) * 1993-03-12 1994-09-22 Hitachi Ltd 順次データ転送型メモリ及び順次データ転送型メモリを用いたコンピュータシステム
JPH11110280A (ja) * 1997-10-02 1999-04-23 Toshiba Corp 半導体メモリシステム
JPH11242629A (ja) * 1997-10-09 1999-09-07 Matsushita Electric Ind Co Ltd メモリシステム
JP2001290697A (ja) * 2000-04-06 2001-10-19 Hitachi Ltd 情報処理システム
US20020038405A1 (en) * 1998-09-30 2002-03-28 Michael W. Leddige Method and apparatus for implementing multiple memory buses on a memory module
US20020084458A1 (en) * 2000-12-28 2002-07-04 Halbert John B. Multi-tier point-to-point buffered memory interface
US20020144071A1 (en) * 2001-03-29 2002-10-03 Williams Michael W. Method and apparatus for handling memory read return data from different time domains
JP2002342153A (ja) * 2001-04-24 2002-11-29 Rambus Inc 多様に配置されたメモリ・コンポーネントからメモリ・オペレーションを調整する方法と装置
JP2003203481A (ja) * 2001-11-07 2003-07-18 Samsung Electronics Co Ltd Ｃａｓレイテンシを利用してロッキングレゾリューション調節が可能な遅延同期ループ回路
WO2004025478A1 (ja) * 2002-09-11 2004-03-25 Fujitsu Limited メモリブロック間のレイテンシ差を活用するデータ処理装置および方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6807609B1 (en) * 1989-12-04 2004-10-19 Hewlett-Packard Development Company, L.P. Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system
US6111796A (en) * 1999-03-01 2000-08-29 Motorola, Inc. Programmable delay control for sense amplifiers in a memory
US6646953B1 (en) 2000-07-06 2003-11-11 Rambus Inc. Single-clock, strobeless signaling system
US6877079B2 (en) * 2001-03-06 2005-04-05 Samsung Electronics Co., Ltd. Memory system having point-to-point bus configuration
US6658523B2 (en) * 2001-03-13 2003-12-02 Micron Technology, Inc. System latency levelization for read data
US6785793B2 (en) 2001-09-27 2004-08-31 Intel Corporation Method and apparatus for memory access scheduling to reduce memory access latency
JP4159415B2 (ja) * 2002-08-23 2008-10-01 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
US7089412B2 (en) * 2003-01-17 2006-08-08 Wintec Industries, Inc. Adaptive memory module
US7020757B2 (en) * 2003-03-27 2006-03-28 Hewlett-Packard Development Company, L.P. Providing an arrangement of memory devices to enable high-speed data access
US7133991B2 (en) * 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US7366864B2 (en) * 2004-03-08 2008-04-29 Micron Technology, Inc. Memory hub architecture having programmable lane widths

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06266615A (ja) * 1993-03-12 1994-09-22 Hitachi Ltd 順次データ転送型メモリ及び順次データ転送型メモリを用いたコンピュータシステム
JPH11110280A (ja) * 1997-10-02 1999-04-23 Toshiba Corp 半導体メモリシステム
JPH11242629A (ja) * 1997-10-09 1999-09-07 Matsushita Electric Ind Co Ltd メモリシステム
US20020038405A1 (en) * 1998-09-30 2002-03-28 Michael W. Leddige Method and apparatus for implementing multiple memory buses on a memory module
JP2001290697A (ja) * 2000-04-06 2001-10-19 Hitachi Ltd 情報処理システム
US20020084458A1 (en) * 2000-12-28 2002-07-04 Halbert John B. Multi-tier point-to-point buffered memory interface
US20020144071A1 (en) * 2001-03-29 2002-10-03 Williams Michael W. Method and apparatus for handling memory read return data from different time domains
JP2002342153A (ja) * 2001-04-24 2002-11-29 Rambus Inc 多様に配置されたメモリ・コンポーネントからメモリ・オペレーションを調整する方法と装置
JP2003203481A (ja) * 2001-11-07 2003-07-18 Samsung Electronics Co Ltd Ｃａｓレイテンシを利用してロッキングレゾリューション調節が可能な遅延同期ループ回路
WO2004025478A1 (ja) * 2002-09-11 2004-03-25 Fujitsu Limited メモリブロック間のレイテンシ差を活用するデータ処理装置および方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11822789B2 (en) 2011-12-27 2023-11-21 Intel Corporation Methods and apparatus to manage workload memory allocation

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US20050262323A1 (en) 2005-11-24
CN1977336B (zh) 2012-02-22
EP1754229A2 (en) 2007-02-21
JP2008500668A (ja) 2008-01-10
WO2005114669A3 (en) 2006-03-16
CN1977336A (zh) 2007-06-06
WO2005114669A2 (en) 2005-12-01
US7222224B2 (en) 2007-05-22
EP1754229B1 (en) 2012-07-11

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