JP2008500668A5 - - Google Patents

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Publication number
JP2008500668A5
JP2008500668A5 JP2007527567A JP2007527567A JP2008500668A5 JP 2008500668 A5 JP2008500668 A5 JP 2008500668A5 JP 2007527567 A JP2007527567 A JP 2007527567A JP 2007527567 A JP2007527567 A JP 2007527567A JP 2008500668 A5 JP2008500668 A5 JP 2008500668A5
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JP
Japan
Prior art keywords
memory
latency time
time group
memory device
latency
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JP2007527567A
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English (en)
Japanese (ja)
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JP4926963B2 (ja
JP2008500668A (ja
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Priority claimed from US10/850,803 external-priority patent/US7222224B2/en
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Publication of JP2008500668A5 publication Critical patent/JP2008500668A5/ja
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Publication of JP4926963B2 publication Critical patent/JP4926963B2/ja
Anticipated expiration legal-status Critical
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JP2007527567A 2004-05-21 2005-05-20 多重メモリアクセスレイテンシ時間をサポートするコンピュータメモリシステムにおける性能を改善するためのシステムおよび方法 Expired - Fee Related JP4926963B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/850,803 US7222224B2 (en) 2004-05-21 2004-05-21 System and method for improving performance in computer memory systems supporting multiple memory access latencies
US10/850,803 2004-05-21
PCT/US2005/018246 WO2005114669A2 (en) 2004-05-21 2005-05-20 System and method for improving performance in computer memory systems supporting multiple memory access latencies

Publications (3)

Publication Number Publication Date
JP2008500668A JP2008500668A (ja) 2008-01-10
JP2008500668A5 true JP2008500668A5 (https=) 2008-05-29
JP4926963B2 JP4926963B2 (ja) 2012-05-09

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JP2007527567A Expired - Fee Related JP4926963B2 (ja) 2004-05-21 2005-05-20 多重メモリアクセスレイテンシ時間をサポートするコンピュータメモリシステムにおける性能を改善するためのシステムおよび方法

Country Status (5)

Country Link
US (1) US7222224B2 (https=)
EP (1) EP1754229B1 (https=)
JP (1) JP4926963B2 (https=)
CN (1) CN1977336B (https=)
WO (1) WO2005114669A2 (https=)

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