CN1977336B - 改善支持多存储器访问延迟的计算机存储器系统的性能的系统和方法 - Google Patents

改善支持多存储器访问延迟的计算机存储器系统的性能的系统和方法 Download PDF

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Publication number
CN1977336B
CN1977336B CN2005800218157A CN200580021815A CN1977336B CN 1977336 B CN1977336 B CN 1977336B CN 2005800218157 A CN2005800218157 A CN 2005800218157A CN 200580021815 A CN200580021815 A CN 200580021815A CN 1977336 B CN1977336 B CN 1977336B
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memory
latency
group
delay
access
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CN1977336A (zh
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史蒂文·C·伍
布赖恩·H·特桑
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Rambus Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN2005800218157A 2004-05-21 2005-05-20 改善支持多存储器访问延迟的计算机存储器系统的性能的系统和方法 Expired - Fee Related CN1977336B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/850,803 US7222224B2 (en) 2004-05-21 2004-05-21 System and method for improving performance in computer memory systems supporting multiple memory access latencies
US10/850,803 2004-05-21
PCT/US2005/018246 WO2005114669A2 (en) 2004-05-21 2005-05-20 System and method for improving performance in computer memory systems supporting multiple memory access latencies

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CN1977336A CN1977336A (zh) 2007-06-06
CN1977336B true CN1977336B (zh) 2012-02-22

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CN2005800218157A Expired - Fee Related CN1977336B (zh) 2004-05-21 2005-05-20 改善支持多存储器访问延迟的计算机存储器系统的性能的系统和方法

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US (1) US7222224B2 (https=)
EP (1) EP1754229B1 (https=)
JP (1) JP4926963B2 (https=)
CN (1) CN1977336B (https=)
WO (1) WO2005114669A2 (https=)

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Also Published As

Publication number Publication date
US20050262323A1 (en) 2005-11-24
JP4926963B2 (ja) 2012-05-09
EP1754229A2 (en) 2007-02-21
JP2008500668A (ja) 2008-01-10
WO2005114669A3 (en) 2006-03-16
CN1977336A (zh) 2007-06-06
WO2005114669A2 (en) 2005-12-01
US7222224B2 (en) 2007-05-22
EP1754229B1 (en) 2012-07-11

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