Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
  • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
  • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
  • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
  • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
  • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
  • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
  • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

Definitions

• the disclosed embodiments relate generally to computer memory systems and methods, and in particular to performance improvements in memory systems supporting multiple memory access latencies.
• Figure 3 is a block diagram of a memory device for use in group levelization.
• Figure 5 is a block diagram of a memory system employing group levelization and including buffers for increased capacity.
• Figure 6 is a flow diagram of a process of allocating memory addresses to memory devices for use in a memory system employing group levelization.
• the memory devices in the memory system are allocated to latency groups including a first latency group and a second latency group.
• the first latency group has a lower latency than the second latency group.
• first and second portions of a memory address space are identified and the first portion of the address space is mapped to at least one memory device allocated to the first latency group while the . second portion of the address space is mapped to at least one memory device allocated to the second latency group.
• Providing the first portion of the address space with a lower access latency than the second portion of the address space can result in improved memory system performance.
• more than two latency groups and more than two portions of memory address space are used.
• a method of controlling access to memory devices in a memory system supporting multiple memory access latencies includes decoding a memory access request to provide a memory device identifier; identifying a latency group associated with the memory device identifier, wherein the latency group is one of a plurality of latency groups in the memory system; comparing the identified latency group with a latency group associated with a previous memory access request; and generating a timing control signal in response to the result of the comparison.
• memory devices disposed on first and second memory modules may be accessed.
• the first access latency to the first memory module may be allocated.
• the first memory module includes the first buffer and the first memory device coupled to the first buffer.
• the second access latency to the second memory module is allocated.
• the second memory module includes the second buffer and the second memory device coupled to the second buffer.
• An advantage of group levelization is that most of the implementation burden is in software (e.g., BIOS).
• BIOS e.g., BIOS
• the technique can be implemented in an off-the- shelf memory controller (e.g., SiS R658) as a BIOS option that can be enabled by motherboard manufacturers, system integrators, end users and the like. Because most of the implementation burden is in software, end-users can select from a large number of device ID/rank mappings or generate their own custom mappings.
• the delay devices 110 are implemented using well- known programmable delay devices and design techniques. As clock speeds increase, however, it becomes increasingly difficult to design a delay device 110 that can provide the delays required by global levelization without significantly impacting the design (e.g., increased size) of the memory devices 104 and/or memory controller 102, or restricting the system to a limited number of memory devices 104.
• the delay devices 100 are implemented using a shift register and an output multiplexer for delaying an output data signal by a specified number of clock cycles. The specified number of clock cycles is stored in a register in the memory device in which the delay device is embedded.
• the register can be loaded via a register write operation performed by the memory controller 102 during initialization.
• This memory allocation methodology is not a problem in computers using a memory system with global levelization, because access latency LQ is independent of the memory device being accessed. However, this memory allocation methodology may perform suboptimally in systems where different memory devices have different access latencies.
• each memory device 104 is assigned to one of a set of latency groups G J ...G M each having a different latency.
• the channel is split into two latency groups of memory devices 104, hereinafter referred to as latency groups G / (Near Group) and G 2 (Far Group).
• Memory devices 104 allocated to latency group Gj are levelized to latency Lj of the highest-latency device in the group (measured in clock cycles), while memory devices 104 allocated to latency group G 2 are levelized to latency Z, 2 of the highest latency device in group G 2 .
• N is equal to 4, which is the length of a data packet, in memory bus clock cycles in at least some memory systems that use RDRAM devices.
• FIG 4 is a block diagram of one embodiment of a memory controller 202 for use in group levelization.
• the memory controller 202 includes a front side bus interface 402 (e.g., for handling communications with a data processor or CPU), a graphics interface 404 (e.g., AGP interface), an I/O interface 408, an arbitration unit 406, controller logic 410, memory 412, and high-speed memory interface 106.
• a front side bus interface 402 e.g., for handling communications with a data processor or CPU
• graphics interface 404 e.g., AGP interface
• I/O interface 408 e.g., AGP interface
• arbitration unit 406 e.g., controller logic 410, memory 412, and high-speed memory interface 106.
• the controller logic 410 is coupled to memory 412, which includes group table 414, last group 416, initialization code 418, and group levelization code 420. Note that Figure 4 represents one particular embodiment of a memory controller.
• the disclosed group levelization techniques can be used with many types of memory controllers
• the initialization code 418 and the group levelization code 420 are stored in a BIOS EPROM, which can be a separate chip coupled to the memory controller 202 via a bus or other interconnect structure.
• the initialization code 418 is executed by the controller logic 410.
• the initialization code is responsible for allocating memory devices to latency groups, and hence filling in the entries of the group table 414.
• the format and content of group table 414 are discussed in more detail below.
• the group table 414 is not a static table, but is dynamically created every time the system is booted to account for changes in the system (e.g., memory may have been added or removed). In other embodiments, the group table 414 can be changed as memory access frequencies change.
• the group levelization code 420 is executed to make sure that all memory devices in each latency group have the same latency.
• the group levelization code 420 is responsible for levelizing latency across all memory devices in the same group. To do this, the group levelization code 420 determines how much delay (if any) to add to each of the memory devices in the group so that they match the latency of the highest latency memory device in the group.
• the memory devices in each group having the lowest latency may have their delay devices 110 (Fig. 3) configured, for example by storing an appropriate value in register 306 (Fig. 3), under the control of the group levelization code. This process is then repeated for each latency group.
• the group levelization code is implemented as part of the initialization code 418.
• the memory requests stored in the queues 422 are examined for memory access contentions by the arbitration unit 406 using conventional arbitration techniques (e.g., round-robin, priorities, etc.).
• the arbitration unit 406 selects a memory request from the requests stored in queue 422 and forwards the selected memory request to the controller logic 410.
• the N-bit address e.g., a 28-bit, 32-bit or 64-bit address
• a sample address mapping i.e., a map of the ⁇ address bits
• the group table 414 provides a mapping between memory addresses (as represented by their Device ID's) and latency groups , to which the memory devices 104 are allocated, using the process described with respect to Figure 6. While Table II also shows the positions of the physical memory devices whose Device ID's and Group values are stored in the group table, in some embodiments (e.g., in which memory devices are addressed using their Device ID's) the physical memory position is not stored in the group table 414. In other embodiments, the group table 414 stores the physical position of each memory device.
• steps 602 and 604 are re-executed at appropriate times so as to remap the most frequently accessed address ranges to a latency group having the smallest latency, or more generally to a latency group having an associated latency smaller than the latency of at least one other latency group.
• a timing control signal is generated (step 706). More specifically, if the current memory request is a request to read data in a memory device in a lower latency group than a memory read request immediately prior to the current request, then the timing control signal causes the controller logic to delay transmission of the current memory access command by an amount of time required to avoid a collision between the data returned by the immediately preceding and current memory access commands.

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• 2004
  • 2004-05-21 US US10/850,803 patent/US7222224B2/en not_active Expired - Lifetime
• 2005
  • 2005-05-20 CN CN2005800218157A patent/CN1977336B/zh not_active Expired - Fee Related
  • 2005-05-20 EP EP05753838A patent/EP1754229B1/en not_active Expired - Lifetime
  • 2005-05-20 WO PCT/US2005/018246 patent/WO2005114669A2/en not_active Ceased
  • 2005-05-20 JP JP2007527567A patent/JP4926963B2/ja not_active Expired - Fee Related

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