JP4800593B2 - 異質構造の製造方法 - Google Patents
異質構造の製造方法 Download PDFInfo
- Publication number
- JP4800593B2 JP4800593B2 JP2004170674A JP2004170674A JP4800593B2 JP 4800593 B2 JP4800593 B2 JP 4800593B2 JP 2004170674 A JP2004170674 A JP 2004170674A JP 2004170674 A JP2004170674 A JP 2004170674A JP 4800593 B2 JP4800593 B2 JP 4800593B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- substrates
- silicon
- thermal expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000000758 substrate Substances 0.000 claims description 215
- 238000000034 method Methods 0.000 claims description 53
- 239000000463 material Substances 0.000 claims description 48
- 239000010453 quartz Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 239000000126 substance Substances 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- -1 hydrogen ions Chemical class 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 6
- 230000003313 weakening effect Effects 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- 229910021426 porous silicon Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 description 6
- 230000035882 stress Effects 0.000 description 6
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 206010016275 Fear Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Combinations Of Printed Boards (AREA)
Description
22 基板(第2の基板)
23 層(脆弱化層または亀裂)
24 一部
25 層
26 基板(第3の基板)
Claims (14)
- 第1の物質の層を、第2の物質によって構成される基板上に形成する方法であって、
前記第1および第2の物質は異なる熱膨張係数を有し、
第1の物質によって構成される第1の基板、ここで、前記第1の基板は、前記第1の基板のうちの一方の表面に存在する移動層であって前記第1の物質からなる移動層を画定するための脆弱化層を含む、と、第2の物質によって構成される第2の基板と、前記第1および第2の物質の一方または他方と同じである物質から形成されるか、或いは前記第1および第2の物質の一方または他方の熱膨張係数と近似するかまたは同じである熱膨張係数を有する物質で構成される第3の基板とを選択する工程と、
前記移動層と前記第2の基板とが接するように前記第1の基板と前記第2の基板とが貼り合わされ、且つ、前記第1および第2の基板のうちの1つと前記第3の基板とが貼り合わされた集合体を形成する工程と、
前記第3の基板が前記第1および第2の基板のうちの1つと貼り合わされたままの状態で、前記第1の基板から分離された前記移動層と前記第2の基板との集合構造が形成されるように、前記脆弱化層に沿って前記第1の基板の厚み内に亀裂を生じさせる工程とを含む方法。 - 前記第1および第2の基板のうちの1つと前記第3の基板とを貼り合わせてから、前記第1および第2の基板を貼り合わせる請求項1に記載の方法。
- 前記第1および第2の基板のうちの1つの基板と前記第3の基板とを貼り合わせる前に、前記第1および第2の基板を貼り合わせる請求項1に記載の方法。
- 前記集合体を形成する工程において、前記第3の基板は、前記第1の基板および前記第2の基板のうち、前記第3の基板を構成する物質と同じである物質から構成されるか、或いは前記第3の基板を構成する物質の熱膨張係数と近似するかまたは同じである熱膨張係数を有する物質で構成される基板と貼り合わされる、請求項1〜3のいずれか1項に記載の方法。
- 前記脆弱化層は、原子打ち込みまたはイオン打ち込みによって、或いは、ポーラスシリコン層を形成することによって形成される請求項1に記載の方法。
- 前記脆弱化層が原子打ち込みまたはイオン打ち込みによって形成され、
打ち込まれるイオンが、水素イオン、または水素イオンおよびヘリウムイオンの混合イオンである請求項5に記載の方法。 - 前記第1の基板は、250℃〜600℃の範囲の温度で亀裂が生じる請求項1〜6のいずれか1項に記載の方法。
- 前記第1および第2の基板は、接着剤による接合または分子接合によって貼り合わせられている請求項1〜7のいずれか1項に記載の方法。
- 前記第1および第2の基板の集合体の界面を強化するために昇温する工程をさらに含む請求項1〜8のいずれか1項に記載の方法。
- 前記第1の基板が半導体によって形成されている請求項1〜9のいずれか1項に記載の方法。
- 前記第2の基板の厚さが500μm〜800μmの範囲である請求項1〜10のいずれか1項に記載の方法。
- 前記第3の基板の厚さが700μm〜1200μmの範囲である請求項1〜11のいずれか1項に記載の方法。
- 前記第1の物質の前記層および前記第2の物質によって構成される前記基板が、シリコン−石英、シリコン−ガラス、シリコン−サファイア、ゲルマニウム−シリコン、ゲルマニウム−ガラス、シリコンカーバイド(SiC)−石英、またはシリコンカーバイド(SiC)−ガラスの構造を形成している請求項1〜12のいずれか1項に記載の方法。
- 前記第1の物質がシリコンであり、前記第2の物質および前記第3の基板を構成する第3の物質が石英である請求項1〜12のいずれか1項に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0307027 | 2003-06-11 | ||
FR0307027A FR2856192B1 (fr) | 2003-06-11 | 2003-06-11 | Procede de realisation de structure heterogene et structure obtenue par un tel procede |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005005708A JP2005005708A (ja) | 2005-01-06 |
JP4800593B2 true JP4800593B2 (ja) | 2011-10-26 |
Family
ID=33186466
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004170674A Expired - Lifetime JP4800593B2 (ja) | 2003-06-11 | 2004-06-09 | 異質構造の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6858517B2 (ja) |
EP (1) | EP1487012A3 (ja) |
JP (1) | JP4800593B2 (ja) |
FR (1) | FR2856192B1 (ja) |
Families Citing this family (32)
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US8241996B2 (en) * | 2005-02-28 | 2012-08-14 | Silicon Genesis Corporation | Substrate stiffness method and resulting devices for layer transfer process |
US7674687B2 (en) * | 2005-07-27 | 2010-03-09 | Silicon Genesis Corporation | Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process |
US20070029043A1 (en) * | 2005-08-08 | 2007-02-08 | Silicon Genesis Corporation | Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process |
US7166520B1 (en) * | 2005-08-08 | 2007-01-23 | Silicon Genesis Corporation | Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process |
US7427554B2 (en) * | 2005-08-12 | 2008-09-23 | Silicon Genesis Corporation | Manufacturing strained silicon substrates using a backing material |
US7268051B2 (en) * | 2005-08-26 | 2007-09-11 | Corning Incorporated | Semiconductor on glass insulator with deposited barrier layer |
JP5041714B2 (ja) * | 2006-03-13 | 2012-10-03 | 信越化学工業株式会社 | マイクロチップ及びマイクロチップ製造用soi基板 |
US7863157B2 (en) * | 2006-03-17 | 2011-01-04 | Silicon Genesis Corporation | Method and structure for fabricating solar cells using a layer transfer process |
US7598153B2 (en) * | 2006-03-31 | 2009-10-06 | Silicon Genesis Corporation | Method and structure for fabricating bonded substrate structures using thermal processing to remove oxygen species |
EP2002484A4 (en) | 2006-04-05 | 2016-06-08 | Silicon Genesis Corp | METHOD AND STRUCTURE FOR MANUFACTURING PHOTOVOLTAIC CELLS USING A LAYER TRANSFER PROCESS |
JP2008004900A (ja) * | 2006-06-26 | 2008-01-10 | Sumco Corp | 貼り合わせウェーハの製造方法 |
US8153513B2 (en) * | 2006-07-25 | 2012-04-10 | Silicon Genesis Corporation | Method and system for continuous large-area scanning implantation process |
FR2919960B1 (fr) | 2007-08-08 | 2010-05-21 | Soitec Silicon On Insulator | Procede et installation pour la fracture d'un substrat composite selon un plan de fragilisation |
US20090206275A1 (en) * | 2007-10-03 | 2009-08-20 | Silcon Genesis Corporation | Accelerator particle beam apparatus and method for low contaminate processing |
US7781308B2 (en) * | 2007-12-03 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
FR2941324B1 (fr) | 2009-01-22 | 2011-04-29 | Soitec Silicon On Insulator | Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant. |
FR2942910B1 (fr) * | 2009-03-06 | 2011-09-30 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure visant a reduire l'etat de contrainte en tension du substrat donneur |
FR2942911B1 (fr) * | 2009-03-09 | 2011-05-13 | Soitec Silicon On Insulator | Procede de realisation d'une heterostructure avec adaptation locale de coefficient de dilatation thermique |
US8216945B2 (en) * | 2009-04-09 | 2012-07-10 | Texas Instruments Incorporated | Wafer planarity control between pattern levels |
FR2947098A1 (fr) * | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
FR2948318B1 (fr) * | 2009-07-22 | 2011-08-19 | Commissariat Energie Atomique | Procede de realisation d'un dispositif a element graphique |
JP5866088B2 (ja) * | 2009-11-24 | 2016-02-17 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
CN103650171B (zh) * | 2011-07-15 | 2018-09-18 | 亮锐控股有限公司 | 将半导体装置结合到支持衬底的方法 |
EP2960925B1 (en) * | 2013-02-19 | 2018-04-25 | NGK Insulators, Ltd. | Semiconductor device and method for manufacturing semiconductor device |
JP6371143B2 (ja) * | 2014-07-08 | 2018-08-08 | イビデン株式会社 | SiCウェハの製造方法、SiC半導体の製造方法及び黒鉛炭化珪素複合基板 |
JP6371142B2 (ja) * | 2014-07-08 | 2018-08-08 | イビデン株式会社 | SiCウェハの製造方法、SiC半導体の製造方法及び炭化珪素複合基板 |
CN110838463A (zh) * | 2018-08-17 | 2020-02-25 | 胡兵 | 一种半导体衬底、将衬底层与其上功能层分离的方法 |
FR3042647B1 (fr) * | 2015-10-20 | 2017-12-01 | Soitec Silicon On Insulator | Structure composite et procede de fabrication associe |
FR3068508B1 (fr) | 2017-06-30 | 2019-07-26 | Soitec | Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents |
CN111834520B (zh) * | 2020-06-29 | 2021-08-27 | 中国科学院上海微系统与信息技术研究所 | 一种表面均匀性优化的压电单晶薄膜制备方法 |
CN113394338A (zh) * | 2021-04-28 | 2021-09-14 | 上海新硅聚合半导体有限公司 | 一种异质单晶薄膜的制备方法及异质单晶薄膜 |
CN117597008A (zh) * | 2024-01-19 | 2024-02-23 | 苏州达波新材科技有限公司 | 一种改善注入晶圆翘曲的方法和压电单晶薄膜及其制备方法 |
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JPH01290229A (ja) * | 1988-05-18 | 1989-11-22 | Meidensha Corp | 半導体ウエハ |
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FR2767604B1 (fr) * | 1997-08-19 | 2000-12-01 | Commissariat Energie Atomique | Procede de traitement pour le collage moleculaire et le decollage de deux structures |
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US6498086B1 (en) * | 2001-07-26 | 2002-12-24 | Intel Corporation | Use of membrane properties to reduce residual stress in an interlayer region |
JP2003347522A (ja) * | 2002-05-24 | 2003-12-05 | Renesas Technology Corp | 半導体装置およびその製造方法 |
FR2842651B1 (fr) * | 2002-07-17 | 2005-07-08 | Procede de lissage du contour d'une couche utile de materiau reportee sur un substrat support | |
FR2845523B1 (fr) * | 2002-10-07 | 2005-10-28 | Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee | |
FR2850390B1 (fr) * | 2003-01-24 | 2006-07-14 | Soitec Silicon On Insulator | Procede d'elimination d'une zone peripherique de colle lors de la fabrication d'un substrat composite |
-
2003
- 2003-06-11 FR FR0307027A patent/FR2856192B1/fr not_active Expired - Lifetime
-
2004
- 2004-05-06 US US10/839,131 patent/US6858517B2/en not_active Expired - Lifetime
- 2004-05-18 EP EP04291267A patent/EP1487012A3/fr not_active Withdrawn
- 2004-06-09 JP JP2004170674A patent/JP4800593B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2005005708A (ja) | 2005-01-06 |
FR2856192A1 (fr) | 2004-12-17 |
US6858517B2 (en) | 2005-02-22 |
FR2856192B1 (fr) | 2005-07-29 |
EP1487012A2 (fr) | 2004-12-15 |
US20040253795A1 (en) | 2004-12-16 |
EP1487012A3 (fr) | 2005-11-16 |
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