JP4778201B2 - Cmosイメージセンサの製造方法 - Google Patents
Cmosイメージセンサの製造方法 Download PDFInfo
- Publication number
- JP4778201B2 JP4778201B2 JP2004088355A JP2004088355A JP4778201B2 JP 4778201 B2 JP4778201 B2 JP 4778201B2 JP 2004088355 A JP2004088355 A JP 2004088355A JP 2004088355 A JP2004088355 A JP 2004088355A JP 4778201 B2 JP4778201 B2 JP 4778201B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- buffer layer
- image sensor
- salicide
- cmos image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 230000002265 prevention Effects 0.000 claims description 41
- 125000006850 spacer group Chemical group 0.000 claims description 30
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 9
- 238000007796 conventional method Methods 0.000 description 3
- 230000005465 channeling Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
21 ゲート絶縁膜
22 ゲート電極
23 スペーサ
24 バッファ層
25 サリサイド防止膜
26 BARC膜
Claims (9)
- 上部にゲート絶縁膜及びゲート電極が形成され、前記ゲート電極側壁にスペーサが形成された半導体基板上に、前記スペーサ及びゲート電極を覆うようにバッファ層を形成するバッファ層形成ステップと、
前記バッファ層上にサリサイド防止膜を形成するサリサイド防止膜形成ステップと、
前記サリサイド防止膜上にBARC膜を形成するBARC膜形成ステップと、
前記ゲート電極の前記サリサイド防止膜が露出するまで前記BARC膜をエッチバックするBARC膜エッチバックステップと、
前記ゲート電極及び前記スペーサの上面の前記バッファ層が露出するまで前記サリサイド防止膜をエッチバックするサリサイド防止膜エッチバックステップと、
前記スペーサが露出して損傷を受けないように、露出した前記バッファ層を選択的に除去し、前記ゲート電極の上面を露出させて生成構造を形成する、バッファ層除去ステップと、
前記生成構造上にサリサイド層を形成するサリサイド形成ステップと
を含む、CMOSイメージセンサの製造方法。 - 前記スペーサは酸化膜からなり、前記バッファ層は窒化膜または酸窒化膜からなることを特徴とする請求項1記載のCMOSイメージセンサの製造方法。
- 前記サリサイド防止膜は、酸化膜からなることを特徴とする請求項2記載のCMOSイメージセンサの製造方法。
- 前記バッファ層除去ステップを、H3PO4溶液を利用したウェットエッチングで行うことを特徴とする請求項2または請求項3記載のCMOSイメージセンサの製造方法。
- 前記スペーサは窒化膜からなり、前記バッファ層は酸化膜からなることを特徴とする請求項1記載のCMOSイメージセンサの製造方法。
- 前記サリサイド防止膜は、酸窒化膜または窒化膜からなることを特徴とする請求項5記載のCMOSイメージセンサの製造方法。
- 前記バッファ層除去ステップを、BOE溶液を利用したウェットエッチングで行うことを特徴とする請求項5または請求項6記載のCMOSイメージセンサの製造方法。
- 前記バッファ層を、約500Åないし約700Åの厚さに形成することを特徴とする請求項2または請求項4記載のCMOSイメージセンサの製造方法。
- 前記バッファ層除去ステップを、ゲート電極用レチクルとネガティブフォトレジストパターンとを用いて形成したゲート電極マスクパターンを利用してドライエッチングによりバッファ層を除去することにより行うことを特徴とする請求項1記載のCMOSイメージセンサの製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0026968A KR100521966B1 (ko) | 2003-04-29 | 2003-04-29 | 씨모스 이미지센서의 제조방법 |
KR2003-026968 | 2003-04-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004327968A JP2004327968A (ja) | 2004-11-18 |
JP4778201B2 true JP4778201B2 (ja) | 2011-09-21 |
Family
ID=33308305
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004088355A Expired - Fee Related JP4778201B2 (ja) | 2003-04-29 | 2004-03-25 | Cmosイメージセンサの製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20040219709A1 (ja) |
JP (1) | JP4778201B2 (ja) |
KR (1) | KR100521966B1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100984913B1 (ko) * | 2003-04-29 | 2010-10-04 | 크로스텍 캐피탈, 엘엘씨 | 씨모스 이미지센서의 제조방법 |
KR100606908B1 (ko) * | 2004-12-29 | 2006-08-01 | 동부일렉트로닉스 주식회사 | 씨모스 이미지 센서의 제조방법 |
KR100641548B1 (ko) | 2005-05-27 | 2006-10-31 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
KR100790252B1 (ko) * | 2006-08-11 | 2008-01-02 | 동부일렉트로닉스 주식회사 | Cmos 이미지 센서 제조방법 |
Family Cites Families (21)
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US5403435A (en) * | 1992-01-23 | 1995-04-04 | Micron Technology, Inc. | Process for selectively etching integrated circuit devices having deep trenches or troughs or elevated features with re-entrant profiles |
US5618760A (en) * | 1994-04-12 | 1997-04-08 | The Board Of Trustees Of The Leland Stanford, Jr. University | Method of etching a pattern on a substrate using a scanning probe microscope |
US5918147A (en) * | 1995-03-29 | 1999-06-29 | Motorola, Inc. | Process for forming a semiconductor device with an antireflective layer |
US5834351A (en) * | 1995-08-25 | 1998-11-10 | Macronix International, Co. Ltd. | Nitridation process with peripheral region protection |
US5700706A (en) * | 1995-12-15 | 1997-12-23 | Micron Technology, Inc. | Self-aligned isolated polysilicon plugged contacts |
US5874200A (en) * | 1996-10-15 | 1999-02-23 | Daewoo Electronics Co., Ltd. | Method for forming a pattern preventing water mark formation |
US5923982A (en) * | 1997-04-21 | 1999-07-13 | Advanced Micro Devices, Inc. | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps |
JP3594779B2 (ja) * | 1997-06-24 | 2004-12-02 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6114209A (en) * | 1998-03-19 | 2000-09-05 | Mosel Vitelic Inc. | Method of fabricating semiconductor devices with raised doped region structures |
US6001697A (en) * | 1998-03-24 | 1999-12-14 | Mosel Vitelic Inc. | Process for manufacturing semiconductor devices having raised doped regions |
US6004843A (en) * | 1998-05-07 | 1999-12-21 | Taiwan Semiconductor Manufacturing Company | Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip |
US6225155B1 (en) * | 1998-12-08 | 2001-05-01 | United Microelectronics, Corp. | Method of forming salicide in embedded dynamic random access memory |
KR20000041321A (ko) * | 1998-12-22 | 2000-07-15 | 윤종용 | 실리사이데이션 저지층을 갖는 반도체 장치의 제조 방법 |
US6194258B1 (en) * | 2000-01-18 | 2001-02-27 | Taiwan Semiconductor Manufacturing Company | Method of forming an image sensor cell and a CMOS logic circuit device |
KR100640574B1 (ko) * | 2000-11-30 | 2006-10-31 | 삼성전자주식회사 | 반도체 메모리 소자의 제조방법 |
KR100374643B1 (ko) * | 2000-12-26 | 2003-03-04 | 삼성전자주식회사 | 하부 단차를 이용한 무노광 패턴 형성방법 |
KR100384062B1 (ko) * | 2001-02-12 | 2003-05-14 | 삼성전자주식회사 | MDL(Merged DRAM and LOGIC)의선택적 실리사이드막 형성방법 |
KR100479208B1 (ko) * | 2002-10-23 | 2005-03-28 | 매그나칩 반도체 유한회사 | 살리사이드 공정을 이용한 이미지센서의 제조 방법 |
US7091536B2 (en) * | 2002-11-14 | 2006-08-15 | Micron Technology, Inc. | Isolation process and structure for CMOS imagers |
JP3958199B2 (ja) * | 2002-12-10 | 2007-08-15 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
US6803291B1 (en) * | 2003-03-20 | 2004-10-12 | Taiwan Semiconductor Manufacturing Co., Ltd | Method to preserve alignment mark optical integrity |
-
2003
- 2003-04-29 KR KR10-2003-0026968A patent/KR100521966B1/ko not_active IP Right Cessation
- 2003-12-24 US US10/746,161 patent/US20040219709A1/en not_active Abandoned
-
2004
- 2004-03-25 JP JP2004088355A patent/JP4778201B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20040095938A (ko) | 2004-11-16 |
JP2004327968A (ja) | 2004-11-18 |
KR100521966B1 (ko) | 2005-10-17 |
US20040219709A1 (en) | 2004-11-04 |
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