JP4758869B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4758869B2
JP4758869B2 JP2006303139A JP2006303139A JP4758869B2 JP 4758869 B2 JP4758869 B2 JP 4758869B2 JP 2006303139 A JP2006303139 A JP 2006303139A JP 2006303139 A JP2006303139 A JP 2006303139A JP 4758869 B2 JP4758869 B2 JP 4758869B2
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JP
Japan
Prior art keywords
conductive layer
layer
substrate
bump
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006303139A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008124077A (ja
JP2008124077A5 (https=
Inventor
洋弘 町田
敏男 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2006303139A priority Critical patent/JP4758869B2/ja
Priority to KR1020070105924A priority patent/KR20080041991A/ko
Priority to US11/923,096 priority patent/US20080182400A1/en
Priority to TW096141633A priority patent/TW200824082A/zh
Priority to EP07021716A priority patent/EP1921670A2/en
Priority to CNA2007101637924A priority patent/CN101179036A/zh
Publication of JP2008124077A publication Critical patent/JP2008124077A/ja
Publication of JP2008124077A5 publication Critical patent/JP2008124077A5/ja
Application granted granted Critical
Publication of JP4758869B2 publication Critical patent/JP4758869B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01215—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2006303139A 2006-11-08 2006-11-08 半導体装置の製造方法 Expired - Fee Related JP4758869B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2006303139A JP4758869B2 (ja) 2006-11-08 2006-11-08 半導体装置の製造方法
KR1020070105924A KR20080041991A (ko) 2006-11-08 2007-10-22 반도체 장치의 제조 방법
US11/923,096 US20080182400A1 (en) 2006-11-08 2007-10-24 Manufacturing method of semiconductor device
TW096141633A TW200824082A (en) 2006-11-08 2007-11-05 Manufacturing method of semiconductor device
EP07021716A EP1921670A2 (en) 2006-11-08 2007-11-08 Manufacturing method of semiconductor device
CNA2007101637924A CN101179036A (zh) 2006-11-08 2007-11-08 半导体器件的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006303139A JP4758869B2 (ja) 2006-11-08 2006-11-08 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2008124077A JP2008124077A (ja) 2008-05-29
JP2008124077A5 JP2008124077A5 (https=) 2009-11-12
JP4758869B2 true JP4758869B2 (ja) 2011-08-31

Family

ID=38982849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006303139A Expired - Fee Related JP4758869B2 (ja) 2006-11-08 2006-11-08 半導体装置の製造方法

Country Status (6)

Country Link
US (1) US20080182400A1 (https=)
EP (1) EP1921670A2 (https=)
JP (1) JP4758869B2 (https=)
KR (1) KR20080041991A (https=)
CN (1) CN101179036A (https=)
TW (1) TW200824082A (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8692135B2 (en) * 2008-08-27 2014-04-08 Nec Corporation Wiring board capable of containing functional element and method for manufacturing same
US9299661B2 (en) * 2009-03-24 2016-03-29 General Electric Company Integrated circuit package and method of making same
JP5237242B2 (ja) 2009-11-27 2013-07-17 日東電工株式会社 配線回路構造体およびそれを用いた半導体装置の製造方法
EP2563464B1 (en) * 2010-04-30 2018-06-06 Second Sight Medical Products, Inc. Improved biocompatible bonding method
TWI557855B (zh) * 2011-12-30 2016-11-11 旭德科技股份有限公司 封裝載板及其製作方法
KR102015812B1 (ko) * 2012-10-05 2019-08-30 한국전자통신연구원 회로보드, 그 제조방법, 및 이를 포함하는 반도체 패키지
WO2014155619A1 (ja) * 2013-03-28 2014-10-02 株式会社安川電機 半導体装置、電力変換装置および半導体装置の製造方法
CN105990288B (zh) 2015-01-30 2019-03-12 日月光半导体制造股份有限公司 半导体衬底及其制造方法
JP2017126688A (ja) * 2016-01-15 2017-07-20 株式会社ジェイデバイス 半導体パッケージの製造方法及び半導体パッケージ
US12107037B2 (en) * 2021-11-03 2024-10-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing electronic devices

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796590A (en) * 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
JP2001339011A (ja) * 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
JP2002050716A (ja) * 2000-08-02 2002-02-15 Dainippon Printing Co Ltd 半導体装置及びその作製方法
JP4075306B2 (ja) * 2000-12-19 2008-04-16 日立電線株式会社 配線基板、ｌｇａ型半導体装置、及び配線基板の製造方法
JP2004047725A (ja) * 2002-07-11 2004-02-12 Sumitomo Bakelite Co Ltd 半導体装置及び製造方法
JP3933094B2 (ja) * 2003-05-27 2007-06-20 セイコーエプソン株式会社 電子部品の実装方法
JP2005064362A (ja) * 2003-08-19 2005-03-10 Nec Electronics Corp 電子装置の製造方法及びその電子装置並びに半導体装置の製造方法

Also Published As

Publication number Publication date
EP1921670A2 (en) 2008-05-14
CN101179036A (zh) 2008-05-14
KR20080041991A (ko) 2008-05-14
JP2008124077A (ja) 2008-05-29
TW200824082A (en) 2008-06-01
US20080182400A1 (en) 2008-07-31

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