JP4754825B2 - Pll回路のノイズを抑制するシステム及び方法 - Google Patents

Pll回路のノイズを抑制するシステム及び方法 Download PDF

Info

Publication number
JP4754825B2
JP4754825B2 JP2004548450A JP2004548450A JP4754825B2 JP 4754825 B2 JP4754825 B2 JP 4754825B2 JP 2004548450 A JP2004548450 A JP 2004548450A JP 2004548450 A JP2004548450 A JP 2004548450A JP 4754825 B2 JP4754825 B2 JP 4754825B2
Authority
JP
Japan
Prior art keywords
frequency
pll
signal
value
divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2004548450A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006504352A (ja
JP2006504352A5 (enExample
Inventor
ユンホ アン
エンソク ソン
イートー クー
ジョン−ウー リー
ジョーンバエ パク
キョンゴー リー
Original Assignee
ジーシーティー セミコンダクター インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ジーシーティー セミコンダクター インコーポレイテッド filed Critical ジーシーティー セミコンダクター インコーポレイテッド
Publication of JP2006504352A publication Critical patent/JP2006504352A/ja
Publication of JP2006504352A5 publication Critical patent/JP2006504352A5/ja
Application granted granted Critical
Publication of JP4754825B2 publication Critical patent/JP4754825B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H03L7/1978Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider using a cycle or pulse removing circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2004548450A 2002-10-25 2003-10-23 Pll回路のノイズを抑制するシステム及び方法 Expired - Lifetime JP4754825B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US42106002P 2002-10-25 2002-10-25
US60/421,060 2002-10-25
US10/689,986 2003-10-22
US10/689,986 US6952125B2 (en) 2002-10-25 2003-10-22 System and method for suppressing noise in a phase-locked loop circuit
PCT/US2003/033709 WO2004040898A2 (en) 2002-10-25 2003-10-23 System and method for suppressing noise in a phase-locked loop circuit

Publications (3)

Publication Number Publication Date
JP2006504352A JP2006504352A (ja) 2006-02-02
JP2006504352A5 JP2006504352A5 (enExample) 2007-01-18
JP4754825B2 true JP4754825B2 (ja) 2011-08-24

Family

ID=32179836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004548450A Expired - Lifetime JP4754825B2 (ja) 2002-10-25 2003-10-23 Pll回路のノイズを抑制するシステム及び方法

Country Status (8)

Country Link
US (1) US6952125B2 (enExample)
EP (1) EP1556952A4 (enExample)
JP (1) JP4754825B2 (enExample)
KR (1) KR100997490B1 (enExample)
AU (1) AU2003284893A1 (enExample)
CA (1) CA2502841A1 (enExample)
TW (1) TWI342674B (enExample)
WO (1) WO2004040898A2 (enExample)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7187241B2 (en) * 2003-05-02 2007-03-06 Silicon Laboratories Inc. Calibration of oscillator devices
US7295077B2 (en) * 2003-05-02 2007-11-13 Silicon Laboratories Inc. Multi-frequency clock synthesizer
US7436227B2 (en) * 2003-05-02 2008-10-14 Silicon Laboratories Inc. Dual loop architecture useful for a programmable clock source and clock multiplier applications
US7288998B2 (en) * 2003-05-02 2007-10-30 Silicon Laboratories Inc. Voltage controlled clock synthesizer
US7113009B2 (en) * 2004-03-24 2006-09-26 Silicon Laboratories Inc. Programmable frequency divider
US7187216B2 (en) * 2004-05-03 2007-03-06 Silicon Laboratories Inc. Phase selectable divider circuit
US7405601B2 (en) * 2004-05-03 2008-07-29 Silicon Laboratories Inc. High-speed divider with pulse-width control
KR100723152B1 (ko) 2005-05-27 2007-05-30 삼성전기주식회사 주파수 분주기 및 이를 이용한 위상 동기 루프 장치
US7406297B2 (en) * 2005-05-30 2008-07-29 Semiconductor Energy Laboratory Co., Ltd. Clock generation circuit and semiconductor device provided therewith
KR100616688B1 (ko) * 2005-06-21 2006-08-28 삼성전기주식회사 저분주비 프로그램가능 주파수 분주기 및 그 방법
TWI282218B (en) * 2005-07-01 2007-06-01 Realtek Semiconductor Corp Method of generating spread spectrum and/or over-clock and its circuit thereof
WO2007004465A1 (ja) * 2005-07-04 2007-01-11 Matsushita Electric Industrial Co., Ltd. 半導体装置およびそれを用いた無線回路装置
US7372341B2 (en) * 2006-04-25 2008-05-13 Sun Microsystems, Inc. Noise immunity circuitry for phase locked loops and delay locked loops
US7551009B2 (en) * 2007-02-28 2009-06-23 Silicon Laboratories Inc. High-speed divider with reduced power consumption
TWI355199B (en) * 2007-03-26 2011-12-21 Realtek Semiconductor Corp Display control device and method
US7929929B2 (en) * 2007-09-25 2011-04-19 Motorola Solutions, Inc. Method and apparatus for spur reduction in a frequency synthesizer
CN101221230B (zh) * 2007-12-26 2010-10-06 西安华迅微电子有限公司 一种多通道公共相位噪声的抑制装置及抑制方法
GB0804342D0 (en) * 2008-03-07 2008-04-16 Cambridge Silicon Radio Ltd Charge transfer in a phase-locked loop
US7983378B2 (en) * 2008-06-30 2011-07-19 Intel Corporation Extended multi-modulus prescaler
US8121569B2 (en) * 2008-09-30 2012-02-21 Intel Corporation Frequency generation techniques
CN102405415B (zh) * 2009-02-20 2014-06-18 加州理工学院 在高精度长期频率/定时测量中的噪声抑制技术
TWI382671B (zh) * 2009-03-13 2013-01-11 Ncku Res & Dev Foundation 可重新組態之積分三角調變模組
US8941443B1 (en) * 2012-03-01 2015-01-27 Rockwell Collins, Inc. Electronically tuned cavity filter
FR2988240B1 (fr) * 2012-03-19 2015-05-29 Thales Sa Generateur de frequence pour un equipement radiofrequence et procede pour generer un signal de sortie
CN102931984B (zh) * 2012-09-26 2014-11-19 成都嘉纳海威科技有限责任公司 一种用于毫米波超宽带频率合成器
GB2533556A (en) * 2014-12-16 2016-06-29 Nordic Semiconductor Asa Oscillator calibration
US9444465B1 (en) * 2015-03-23 2016-09-13 Peregrine Semiconductor Corporation Low phase noise frequency divider
US9553714B2 (en) * 2015-06-26 2017-01-24 Broadcom Corporation Frequency multiplier for a phase-locked loop
US10715157B2 (en) 2016-03-31 2020-07-14 Apple Inc. Methods and mobile communication devices for performing spur relocation for phase-locked loops
US9998129B1 (en) 2017-09-21 2018-06-12 Qualcomm Incorporated PLL post divider phase continuity
CN110764439B (zh) * 2018-07-25 2022-09-06 上海英威腾工业技术有限公司 伺服驱动脉冲输出分频器及其使用方法
JP7420537B2 (ja) * 2019-11-26 2024-01-23 ローム株式会社 位相ロックループ回路
US11165432B1 (en) * 2020-11-06 2021-11-02 Movellus Circuits, Inc. Glitch-free digital controlled delay line apparatus and method
CN112491415B (zh) * 2020-12-09 2024-10-29 北京中科飞鸿科技股份有限公司 一种超宽频带低杂散双锁相环频率源
CN112636747A (zh) * 2020-12-22 2021-04-09 成都华微电子科技有限公司 锁相环参考杂散快速仿真方法
US11387834B1 (en) * 2021-05-13 2022-07-12 Texas Instruments Incorporated Methods and apparatus to implement pulse swallowing circuitry in a phase frequency detector

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10247851A (ja) * 1997-03-04 1998-09-14 Hitachi Denshi Ltd フラクショナル−n方式の周波数シンセサイザおよびそれを使用した中継装置
JPH10285027A (ja) * 1997-04-03 1998-10-23 Sony Tektronix Corp Pll発振回路
JPH11195986A (ja) * 1997-12-26 1999-07-21 Hitachi Denshi Ltd 集積回路
US20020145472A1 (en) * 2000-10-10 2002-10-10 Lee-Sang Oh Single-bit sigma-delta modulated fractional-N frequency synthesizer
JP2003179490A (ja) * 2001-10-02 2003-06-27 Nec Electronics Corp フラクショナルn周波数シンセサイザ

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5038117A (en) * 1990-01-23 1991-08-06 Hewlett-Packard Company Multiple-modulator fractional-N divider
US5070310A (en) * 1990-08-31 1991-12-03 Motorola, Inc. Multiple latched accumulator fractional N synthesis
US5825253A (en) * 1997-07-15 1998-10-20 Qualcomm Incorporated Phase-locked-loop with noise shaper
US5777521A (en) * 1997-08-12 1998-07-07 Motorola Inc. Parallel accumulator fractional-n frequency synthesizer
JP2001127632A (ja) * 1999-10-29 2001-05-11 Matsushita Electric Ind Co Ltd 周波数シンセサイザ及び発振周波数制御方法
US20020030546A1 (en) * 2000-05-31 2002-03-14 Keating Pierce Vincent Frequency synthesizer having an offset frequency summation path
JP3415574B2 (ja) * 2000-08-10 2003-06-09 Necエレクトロニクス株式会社 Pll回路
KR100725935B1 (ko) * 2001-03-23 2007-06-11 삼성전자주식회사 프랙셔널-앤 주파수 합성기용 위상 고정 루프 회로
US6873213B2 (en) * 2001-10-02 2005-03-29 Nec Compound Semiconductor Devices, Ltd. Fractional N frequency synthesizer
US6642800B2 (en) * 2002-04-04 2003-11-04 Ati Technologies, Inc. Spurious-free fractional-N frequency synthesizer with multi-phase network circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10247851A (ja) * 1997-03-04 1998-09-14 Hitachi Denshi Ltd フラクショナル−n方式の周波数シンセサイザおよびそれを使用した中継装置
JPH10285027A (ja) * 1997-04-03 1998-10-23 Sony Tektronix Corp Pll発振回路
JPH11195986A (ja) * 1997-12-26 1999-07-21 Hitachi Denshi Ltd 集積回路
US20020145472A1 (en) * 2000-10-10 2002-10-10 Lee-Sang Oh Single-bit sigma-delta modulated fractional-N frequency synthesizer
JP2003179490A (ja) * 2001-10-02 2003-06-27 Nec Electronics Corp フラクショナルn周波数シンセサイザ

Also Published As

Publication number Publication date
AU2003284893A1 (en) 2004-05-25
WO2004040898A3 (en) 2004-09-02
TW200421715A (en) 2004-10-16
KR100997490B1 (ko) 2010-12-01
KR20050070078A (ko) 2005-07-05
HK1081739A1 (zh) 2006-05-19
EP1556952A2 (en) 2005-07-27
CA2502841A1 (en) 2004-05-13
JP2006504352A (ja) 2006-02-02
TWI342674B (en) 2011-05-21
AU2003284893A8 (en) 2004-05-25
WO2004040898A2 (en) 2004-05-13
US6952125B2 (en) 2005-10-04
US20040085103A1 (en) 2004-05-06
EP1556952A4 (en) 2005-12-21

Similar Documents

Publication Publication Date Title
JP2006504352A (ja) Pll回路のノイズを抑制するシステム及び方法
US8305115B2 (en) Elimination of fractional N boundary spurs in a signal synthesizer
JP3082860B2 (ja) 音声/データ通信システム用分数分周合成器
US7477676B2 (en) Spread spectrum clock generator and integrated circuit device using the spread spectrum clock generators
US6873213B2 (en) Fractional N frequency synthesizer
JP2007522740A (ja) サブμ技術に適したデジタル位相同期回路
JP4903969B2 (ja) 回転周波数合成器
JPH06244721A (ja) 周波数合成におけるスプリアス低減装置および方法
JP3267260B2 (ja) 位相同期ループ回路及びそれを使用した周波数変調方法
JP2013200135A (ja) レーダ送受信機
JP6366523B2 (ja) 周波数シンセサイザ
KR100819390B1 (ko) 2개의 위상 동기 루프를 사용한 주파수 합성기
JP2015100081A (ja) スペクトラム拡散クロックジェネレータ及びその制御方法
KR101251708B1 (ko) 저주파수 기생 발산의 제거를 이용하는 광대역 주파수 합성기
TWI831562B (zh) 具有減少的抖動的鎖相迴路以及用以自參考時脈產生具有減少的抖動之輸出時脈的方法
US7574185B2 (en) Method and apparatus for generating a phase-locked output signal
US7355457B2 (en) Frequency synthesizer
JP2003179490A (ja) フラクショナルn周波数シンセサイザ
CN100362743C (zh) 用于抑制锁相环电路中的噪声的系统和方法
KR100684053B1 (ko) 시그마 델타 변조 장치, 이를 이용한 주파수 합성기 및 분수 분주 주파수 합성 방법
JP3797791B2 (ja) Pllシンセサイザ発振器
JP2001237700A (ja) 位相同期ループ回路
KR100638894B1 (ko) Σ△ 변조를 이용한 프로그램가능 주파수 분주기
HK1081739B (en) System and method for suppressing noise in a phase-locked loop circuit
JP2005513852A (ja) 低ノイズシンセサイザ

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061023

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061122

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090625

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090703

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20091005

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20091013

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20091102

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20091110

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20091202

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20091209

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100316

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100716

RD13 Notification of appointment of power of sub attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7433

Effective date: 20100720

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20100720

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20100916

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110415

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110513

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110526

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140603

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4754825

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term