JP4751039B2 - 不揮発性半導体記憶装置 - Google Patents
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- JP4751039B2 JP4751039B2 JP2004215532A JP2004215532A JP4751039B2 JP 4751039 B2 JP4751039 B2 JP 4751039B2 JP 2004215532 A JP2004215532 A JP 2004215532A JP 2004215532 A JP2004215532 A JP 2004215532A JP 4751039 B2 JP4751039 B2 JP 4751039B2
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- 239000004065 semiconductor Substances 0.000 title claims description 47
- 230000015654 memory Effects 0.000 claims description 243
- 238000012795 verification Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 description 56
- 238000009826 distribution Methods 0.000 description 48
- 230000008569 process Effects 0.000 description 27
- 238000003860 storage Methods 0.000 description 15
- 230000008859 change Effects 0.000 description 13
- 238000002360 preparation method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- SJHPCNCNNSSLPL-CSKARUKUSA-N (4e)-4-(ethoxymethylidene)-2-phenyl-1,3-oxazol-5-one Chemical compound O1C(=O)C(=C/OCC)\N=C1C1=CC=CC=C1 SJHPCNCNNSSLPL-CSKARUKUSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 239000002784 hot electron Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
圧は、“11”に対応するものとする。図5に、書き込み動作において、各メモリセルの制御ゲートに印加するゲート電圧、つまり、ワード線電圧の波形を示す。尚、各メモリセルのドレインに印加するドレイン電圧、つまり、ビット線電圧は一定値Vdp(例えば5V)で、各メモリセルのソース(共通ソース線)は、書き込み及びベリファイ工程中は何れも接地されている。各電圧の初期状態として、例えば、ワード線電圧0V、ビット線電圧0V、ソース電圧0V(ソース電圧は書き込み期間中0Vに固定)であるとする。
11: メモリアレイ
12: リファレンスメモリアレイ
13: ワード線電圧供給回路
14: ビット線電圧供給回路
15: センスアンプ・アレイ
16: 書き込み電圧発生回路
17: 読み出し電圧発生回路
18: 制御回路
40: フローティングゲート
41: チャネル領域
42: 制御ゲート
43: トンネル酸化膜
44: 絶縁膜
45: ソース
46: ドレイン
100: メモリセル
Claims (14)
- チャネル領域と制御ゲート間に絶縁膜を介してフローティングゲートの形成されたトランジスタを有するメモリセルを行方向及び列方向に夫々複数配列し、同一行の前記メモリセルの前記制御ゲートを相互に接続して共通のワード線とし、同一列の前記メモリセルのドレインを相互に接続して共通のビット線として構成されたメモリセルアレイと、
書き込み対象の前記メモリセルに接続する前記ワード線を選択して書き込み用のゲート電圧を印加するワード線電圧供給手段と、
書き込み対象の前記メモリセルに接続する前記ビット線を選択して書き込み用のドレイン電圧を印加するビット線電圧供給手段と、を備えてなり、
前記ワード線電圧供給手段は、同じ前記メモリセルに対して1回目に印加する前記ゲート電圧と異なるゲート電圧を2回目以降に印加可能に構成され、
前記ワード線電圧供給手段と前記ビット線電圧供給手段の少なくとも一方は、前記ゲート電圧と前記ドレイン電圧の両方が前記メモリセルに印加されている印加時間に関し、同じ前記メモリセルに対して1回目に印加する電圧の前記印加時間を2回目に印加する前記印加時間より長く設定可能に構成され、更に、同じ前記メモリセルに対して2回目から3回目以降の所定回目までに印加する電圧の前記印加時間が、徐々に段階的に長くなるように設定され、1回目の前記印加時間と前記所定回目以降の前記印加時間が等しく設定されていることを特徴とする不揮発性半導体記憶装置。 - 前記ワード線電圧供給手段は、同じ前記メモリセルに対して2回目以降に印加する前記ゲート電圧を、1回目に印加するゲート電圧に対して徐々に段階的に高くして供給することを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記ワード線電圧供給手段が2回目以降に印加するゲート電圧の1回前の印加時のゲート電圧からの電圧上昇分が一定値であることを特徴とする請求項2に記載の不揮発性半導体記憶装置。
- 書き込み対象の前記メモリセルの書き込み状態を検証する書き込み検証手段を備え、
前記書き込み検証手段は、前記ゲート電圧の印加が終了する毎に、前記メモリセルの書き込み状態を検証することを特徴とする請求項1に記載の不揮発性半導体記憶装置。 - 前記ワード線電圧供給手段と前記ビット線電圧供給手段の少なくとも一方は、前記書き込み検証手段によって、閾値電圧が所定の設定値以上となっている書き込み状態と判定された前記メモリセルに対しては、前記電圧の印加を行わないことを特徴とする請求項4に記載の不揮発性半導体記憶装置。
- 前記ワード線電圧供給手段は、同じ前記メモリセルに対して、1回目に印加する前記ゲート電圧として2以上の異なる電圧値を選択的に印加することにより、前記各メモリセルに3値以上のデータを記憶可能に構成されていることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記ワード線電圧供給手段は、1回目に印加する前記ゲート電圧を同じ電圧で断続的に印加することにより1回目の前記印加時間を調整可能に構成されていることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記ワード線電圧供給手段は、同じ前記メモリセルに対して1回目に印加する前記ゲート電圧と同じゲート電圧を2回目に印加可能に構成されていることを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- チャネル領域と制御ゲート間に絶縁膜を介してフローティングゲートの形成されたトランジスタを有するメモリセルを行方向及び列方向に夫々複数配列し、同一行の前記メモリセルの前記制御ゲートを相互に接続して共通のワード線とし、同一列の前記メモリセルのドレインを相互に接続して共通のビット線として構成されたメモリセルアレイと、
書き込み対象の前記メモリセルに接続する前記ワード線を選択して書き込み用のゲート電圧を印加するワード線電圧供給手段と、
書き込み対象の前記メモリセルに接続する前記ビット線を選択して書き込み用のドレイン電圧を印加するビット線電圧供給手段と、を備えてなり、
前記ワード線電圧供給手段は、同じ前記メモリセルに対して1回目に印加する前記ゲート電圧と異なるゲート電圧を2回目以降に印加可能に構成され、1回目と2回目に印加される前記ゲート電圧の電圧差と2回目と3回目に印加される前記ゲート電圧の電圧差を異ならせ、且つ、3回目以降の前記ゲート電圧は、印加回数に応じて徐々に段階的に高くして供給し、同じ前記メモリセルに対して2回目に印加する前記ゲート電圧を、1回目に印加する前記ゲート電圧以下にして供給し、更に、同じ前記メモリセルに対して3回目以降に印加する前記ゲート電圧を、その1回前に印加する前記ゲート電圧からの上昇分を徐々に段階的に大きくして供給することを特徴とする不揮発性半導体記憶装置。 - 前記ワード線電圧供給手段と前記ビット線電圧供給手段の少なくとも何れか一方は、前記ゲート電圧と前記ドレイン電圧の両方が前記メモリセルに印加されている印加時間に関し、同じ前記メモリセルに対して1回目に印加する電圧の前記印加時間と2回目以降に印加する前記印加時間を等しく設定していることを特徴とする請求項9に記載の不揮発性半導体記憶装置。
- 書き込み対象の前記メモリセルの書き込み状態を検証する書き込み検証手段を備え、
前記書き込み検証手段は、前記ゲート電圧の印加が終了する毎に、前記メモリセルの書き込み状態を検証することを特徴とする請求項9に記載の不揮発性半導体記憶装置。 - 前記ワード線電圧供給手段と前記ビット線電圧供給手段の少なくとも一方は、前記書き込み検証手段によって、閾値電圧が所定の設定値以上となっている書き込み状態と判定された前記メモリセルに対しては、前記電圧の印加を行わないことを特徴とする請求項11に記載の不揮発性半導体記憶装置。
- 前記ワード線電圧供給手段は、同じ前記メモリセルに対して、1回目に印加する前記ゲート電圧として2以上の異なる電圧値を選択的に印加することにより、前記各メモリセルに3値以上のデータを記憶可能に構成されていることを特徴とする請求項9に記載の不揮発性半導体記憶装置。
- 前記ワード線電圧供給手段は、同じ前記メモリセルに対して1回目に印加する前記ゲート電圧と同じゲート電圧を2回目に印加可能に構成されていることを特徴とする請求項9に記載の不揮発性半導体記憶装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/760,351 US6937520B2 (en) | 2004-01-21 | 2004-01-21 | Nonvolatile semiconductor memory device |
US10-760351 | 2004-01-21 |
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JP2005216466A JP2005216466A (ja) | 2005-08-11 |
JP4751039B2 true JP4751039B2 (ja) | 2011-08-17 |
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JP2004215532A Expired - Fee Related JP4751039B2 (ja) | 2004-01-21 | 2004-07-23 | 不揮発性半導体記憶装置 |
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JP (1) | JP4751039B2 (ja) |
Families Citing this family (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100525004B1 (ko) * | 2004-02-26 | 2005-10-31 | 삼성전자주식회사 | 멀티레벨 셀(Multi-level cell)플래쉬메모리장치 및 이의 프로그램 방법 |
KR100626377B1 (ko) * | 2004-06-07 | 2006-09-20 | 삼성전자주식회사 | 동작 모드에 따라 프로그램 전압의 증가분을 가변할 수있는 불 휘발성 메모리 장치 |
US7057934B2 (en) * | 2004-06-29 | 2006-06-06 | Intel Corporation | Flash memory with coarse/fine gate step programming |
US7110298B2 (en) * | 2004-07-20 | 2006-09-19 | Sandisk Corporation | Non-volatile system with program time control |
US7173859B2 (en) * | 2004-11-16 | 2007-02-06 | Sandisk Corporation | Faster programming of higher level states in multi-level cell flash memory |
WO2006071686A2 (en) * | 2004-12-29 | 2006-07-06 | Atmel Corporation | Method and system for reducing soft-writing in a multi-level flash memory |
ITMI20042538A1 (it) * | 2004-12-29 | 2005-03-29 | Atmel Corp | Metodo e sistema per la riduzione del soft-writing in una memoria flash a livelli multipli |
JP4907896B2 (ja) * | 2005-04-12 | 2012-04-04 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR100666174B1 (ko) * | 2005-04-27 | 2007-01-09 | 삼성전자주식회사 | 3-레벨 불휘발성 반도체 메모리 장치 및 이에 대한구동방법 |
US7342833B2 (en) * | 2005-08-23 | 2008-03-11 | Freescale Semiconductor, Inc. | Nonvolatile memory cell programming |
US7286406B2 (en) * | 2005-10-14 | 2007-10-23 | Sandisk Corporation | Method for controlled programming of non-volatile memory exhibiting bit line coupling |
US7180780B1 (en) * | 2005-11-17 | 2007-02-20 | Macronix International Co., Ltd. | Multi-level-cell programming methods of non-volatile memories |
US7372732B2 (en) * | 2005-11-23 | 2008-05-13 | Macronix International Co., Ltd. | Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell |
ITMI20052350A1 (it) * | 2005-12-09 | 2007-06-10 | St Microelectronics Srl | Metodo di programmazione di celle di memoria in particolare di tipo flash e relativa architettura di programmazione |
US7327608B2 (en) * | 2006-03-28 | 2008-02-05 | Sandisk Corporation | Program time adjustment as function of program voltage for improved programming speed in programming method |
US7330373B2 (en) * | 2006-03-28 | 2008-02-12 | Sandisk Corporation | Program time adjustment as function of program voltage for improved programming speed in memory system |
US7630253B2 (en) * | 2006-04-05 | 2009-12-08 | Spansion Llc | Flash memory programming and verification with reduced leakage current |
WO2007132457A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Combined distortion estimation and error correction coding for memory devices |
WO2007132456A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Memory device with adaptive capacity |
CN103208309B (zh) | 2006-05-12 | 2016-03-09 | 苹果公司 | 存储设备中的失真估计和消除 |
DE602006011451D1 (de) * | 2006-06-21 | 2010-02-11 | Hynix Semiconductor Inc | Verfahren und Vorrichtung zum elektrischen Programmieren von Halbleiterspeicherzellen |
JP4901348B2 (ja) * | 2006-07-20 | 2012-03-21 | 株式会社東芝 | 半導体記憶装置およびその制御方法 |
WO2008026203A2 (en) * | 2006-08-27 | 2008-03-06 | Anobit Technologies | Estimation of non-linear distortion in memory devices |
US7450426B2 (en) * | 2006-10-10 | 2008-11-11 | Sandisk Corporation | Systems utilizing variable program voltage increment values in non-volatile memory program operations |
US7474561B2 (en) * | 2006-10-10 | 2009-01-06 | Sandisk Corporation | Variable program voltage increment values in non-volatile memory program operations |
WO2008045805A1 (en) * | 2006-10-10 | 2008-04-17 | Sandisk Corporation | Variable program voltage increment values in non-volatile memory program operations |
WO2008053472A2 (en) | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7924648B2 (en) * | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
US8151163B2 (en) | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
KR100850509B1 (ko) * | 2007-01-10 | 2008-08-05 | 삼성전자주식회사 | 프로그램 에러를 감소시킬 수 있는 멀티 비트 플래시메모리 장치의 프로그램 방법 |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
WO2008111058A2 (en) | 2007-03-12 | 2008-09-18 | Anobit Technologies Ltd. | Adaptive estimation of memory cell read thresholds |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
US7656709B2 (en) * | 2007-05-03 | 2010-02-02 | Micron Technology, Inc. | NAND step up voltage switching method |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
WO2008139441A2 (en) | 2007-05-12 | 2008-11-20 | Anobit Technologies Ltd. | Memory device with internal signal processing unit |
US7580290B2 (en) * | 2007-06-21 | 2009-08-25 | Sandisk Corporation | Non-volatile storage system with intelligent control of program pulse duration |
US7630249B2 (en) * | 2007-06-21 | 2009-12-08 | Sandisk Corporation | Intelligent control of program pulse duration |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
US7869273B2 (en) * | 2007-09-04 | 2011-01-11 | Sandisk Corporation | Reducing the impact of interference during programming |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US7978520B2 (en) * | 2007-09-27 | 2011-07-12 | Sandisk Corporation | Compensation of non-volatile memory chip non-idealities by program pulse adjustment |
WO2009050703A2 (en) | 2007-10-19 | 2009-04-23 | Anobit Technologies | Data storage in analog memory cell arrays having erase failures |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US8000141B1 (en) * | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
WO2009063450A2 (en) | 2007-11-13 | 2009-05-22 | Anobit Technologies | Optimized selection of memory units in multi-unit memory devices |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
US7916544B2 (en) | 2008-01-25 | 2011-03-29 | Micron Technology, Inc. | Random telegraph signal noise reduction scheme for semiconductor memories |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US8533563B2 (en) * | 2008-03-31 | 2013-09-10 | Qimonda Ag | Memory read-out |
KR100976696B1 (ko) * | 2008-07-10 | 2010-08-18 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치의 프로그램 방법 |
US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US7995388B1 (en) | 2008-08-05 | 2011-08-09 | Anobit Technologies Ltd. | Data storage using modified voltages |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
JP2011040135A (ja) * | 2009-08-13 | 2011-02-24 | Toshiba Corp | 不揮発性半導体記憶装置 |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8677203B1 (en) | 2010-01-11 | 2014-03-18 | Apple Inc. | Redundant data storage schemes for multi-die memory systems |
US8218366B2 (en) | 2010-04-18 | 2012-07-10 | Sandisk Technologies Inc. | Programming non-volatile storage including reducing impact from other memory cells |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
KR101205084B1 (ko) * | 2010-07-09 | 2012-11-26 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 프로그램 방법 |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
US8472257B2 (en) * | 2011-03-24 | 2013-06-25 | Sandisk Technologies Inc. | Nonvolatile memory and method for improved programming with reduced verify |
US8995206B2 (en) * | 2011-07-14 | 2015-03-31 | Technion Research And Development Foundation Ltd. | Device, method and computer readable program for accessing memory cells using shortened read attempts |
CN103165183A (zh) | 2011-12-09 | 2013-06-19 | 株式会社东芝 | 非易失性半导体存储装置 |
JP5622712B2 (ja) * | 2011-12-09 | 2014-11-12 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US8824203B2 (en) * | 2012-07-13 | 2014-09-02 | Micron Technology, Inc. | Multiple step programming in a memory device |
US9928126B1 (en) | 2017-06-01 | 2018-03-27 | Apple Inc. | Recovery from cross-temperature read failures by programming neighbor word lines |
TWI699772B (zh) * | 2019-10-29 | 2020-07-21 | 旺宏電子股份有限公司 | 在步進編程脈衝操作中決定快速通過寫入操作的方法與系統 |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3184366B2 (ja) * | 1992-06-02 | 2001-07-09 | 株式会社東芝 | 不揮発性半導体記憶装置 |
TW389909B (en) * | 1995-09-13 | 2000-05-11 | Toshiba Corp | Nonvolatile semiconductor memory device and its usage |
US6166979A (en) * | 1995-09-13 | 2000-12-26 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method for using the same |
TW365001B (en) * | 1996-10-17 | 1999-07-21 | Hitachi Ltd | Non-volatile semiconductor memory apparatus and the operation method |
JPH1139887A (ja) * | 1997-07-14 | 1999-02-12 | Sony Corp | 不揮発性半導体記憶装置 |
JPH11134879A (ja) | 1997-10-30 | 1999-05-21 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP3906545B2 (ja) * | 1998-02-03 | 2007-04-18 | ソニー株式会社 | 不揮発性半導体記憶装置 |
JP3922516B2 (ja) * | 2000-09-28 | 2007-05-30 | 株式会社ルネサステクノロジ | 不揮発性メモリと不揮発性メモリの書き込み方法 |
JP2002133885A (ja) * | 2000-10-30 | 2002-05-10 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP4245437B2 (ja) * | 2003-08-08 | 2009-03-25 | シャープ株式会社 | 不揮発性半導体記憶装置の書き込み方法 |
US7177199B2 (en) * | 2003-10-20 | 2007-02-13 | Sandisk Corporation | Behavior based programming of non-volatile memory |
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