DE602006011451D1 - Verfahren und Vorrichtung zum elektrischen Programmieren von Halbleiterspeicherzellen - Google Patents

Verfahren und Vorrichtung zum elektrischen Programmieren von Halbleiterspeicherzellen

Info

Publication number
DE602006011451D1
DE602006011451D1 DE602006011451T DE602006011451T DE602006011451D1 DE 602006011451 D1 DE602006011451 D1 DE 602006011451D1 DE 602006011451 T DE602006011451 T DE 602006011451T DE 602006011451 T DE602006011451 T DE 602006011451T DE 602006011451 D1 DE602006011451 D1 DE 602006011451D1
Authority
DE
Germany
Prior art keywords
memory cells
semiconductor memory
electrical programming
programming
electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006011451T
Other languages
English (en)
Inventor
Luca Crippa
Rino Micheloni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
SK Hynix Inc
Original Assignee
STMicroelectronics SRL
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL, Hynix Semiconductor Inc filed Critical STMicroelectronics SRL
Publication of DE602006011451D1 publication Critical patent/DE602006011451D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
DE602006011451T 2006-06-21 2006-06-21 Verfahren und Vorrichtung zum elektrischen Programmieren von Halbleiterspeicherzellen Active DE602006011451D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP06115812A EP1870905B1 (de) 2006-06-21 2006-06-21 Verfahren und Vorrichtung zum elektrischen Programmieren von Halbleiterspeicherzellen

Publications (1)

Publication Number Publication Date
DE602006011451D1 true DE602006011451D1 (de) 2010-02-11

Family

ID=37431921

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006011451T Active DE602006011451D1 (de) 2006-06-21 2006-06-21 Verfahren und Vorrichtung zum elektrischen Programmieren von Halbleiterspeicherzellen

Country Status (4)

Country Link
US (1) US7499332B2 (de)
EP (1) EP1870905B1 (de)
CN (1) CN101123118B (de)
DE (1) DE602006011451D1 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7393739B2 (en) * 2006-08-30 2008-07-01 International Business Machines Corporation Demultiplexers using transistors for accessing memory cell arrays
US7920430B2 (en) * 2008-07-01 2011-04-05 Qimonda Ag Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation
KR101532754B1 (ko) 2008-09-22 2015-07-02 삼성전자주식회사 비휘발성 메모리 장치의 프로그램 방법
KR101066686B1 (ko) * 2009-06-29 2011-09-21 주식회사 하이닉스반도체 반도체 메모리 소자 및 이의 독출 방법
KR101616097B1 (ko) * 2009-11-11 2016-04-28 삼성전자주식회사 불휘발성 메모리 장치의 프로그램 방법
KR101676816B1 (ko) 2010-02-11 2016-11-18 삼성전자주식회사 플래시 메모리 장치 및 그것의 프로그램 방법
KR101802815B1 (ko) 2011-06-08 2017-12-29 삼성전자주식회사 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 프로그램 방법
JP2013534685A (ja) 2010-07-21 2013-09-05 モサイド・テクノロジーズ・インコーポレーテッド フラッシュメモリのためのマルチページプログラム方式
KR101193059B1 (ko) * 2011-04-21 2012-10-22 에스케이하이닉스 주식회사 비휘발성 메모리 장치 및 그 동작 방법
JP2013196731A (ja) 2012-03-21 2013-09-30 Toshiba Corp 不揮発性半導体記憶装置
KR101980676B1 (ko) * 2012-05-25 2019-05-22 에스케이하이닉스 주식회사 메모리 및 그 검증 방법
KR102005709B1 (ko) * 2012-10-22 2019-08-01 삼성전자 주식회사 메모리 장치 구동 방법 및 메모리 시스템
KR102090677B1 (ko) * 2013-09-16 2020-03-18 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 동작 방법
KR20150085375A (ko) * 2014-01-15 2015-07-23 삼성전자주식회사 메모리 컨트롤러의 동작방법 및 메모리 컨트롤러
KR20160039486A (ko) * 2014-10-01 2016-04-11 에스케이하이닉스 주식회사 반도체 장치
FR3039921B1 (fr) * 2015-08-06 2018-02-16 Stmicroelectronics (Rousset) Sas Procede et systeme de controle d'une operation d'ecriture d'une donnee dans une cellule-memoire du type eeprom
DE102015225693A1 (de) * 2015-12-17 2017-06-22 Henkel Ag & Co. Kgaa Treibmittelfreie Deodorant- und/oder Antitranspirantien mit speziellen Konservierungsmittelkombinationen
KR102524916B1 (ko) * 2018-03-13 2023-04-26 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
KR20210027783A (ko) * 2019-09-03 2021-03-11 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
KR20210105728A (ko) * 2020-02-19 2021-08-27 에스케이하이닉스 주식회사 메모리 장치 및 그 동작 방법
JP6928698B1 (ja) * 2020-08-05 2021-09-01 ウィンボンド エレクトロニクス コーポレーション 半導体装置および読出し方法
KR20220039282A (ko) * 2020-09-22 2022-03-29 에스케이하이닉스 주식회사 컨트롤러 및 이를 포함하는 메모리 시스템
CN112270947B (zh) * 2020-10-29 2023-08-04 长江存储科技有限责任公司 用于存储器的编程方法和装置
WO2023028846A1 (zh) * 2021-08-31 2023-03-09 长江存储科技有限责任公司 存储器、存储器的编程方法及编程验证方法、存储器系统

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3920501B2 (ja) * 1999-04-02 2007-05-30 株式会社東芝 不揮発性半導体記憶装置及びそのデータ消去制御方法
JP4249352B2 (ja) 1999-11-09 2009-04-02 富士通株式会社 不揮発性半導体記憶装置
US6738289B2 (en) 2001-02-26 2004-05-18 Sandisk Corporation Non-volatile memory with improved programming and method therefor
US6466480B2 (en) * 2001-03-27 2002-10-15 Micron Technology, Inc. Method and apparatus for trimming non-volatile memory cells
JP3891863B2 (ja) * 2002-03-07 2007-03-14 松下電器産業株式会社 半導体装置及び半導体装置の駆動方法
US6937520B2 (en) * 2004-01-21 2005-08-30 Tsuyoshi Ono Nonvolatile semiconductor memory device
US6888758B1 (en) 2004-01-21 2005-05-03 Sandisk Corporation Programming non-volatile memory
US7450426B2 (en) * 2006-10-10 2008-11-11 Sandisk Corporation Systems utilizing variable program voltage increment values in non-volatile memory program operations

Also Published As

Publication number Publication date
US7499332B2 (en) 2009-03-03
EP1870905A1 (de) 2007-12-26
EP1870905B1 (de) 2009-12-30
CN101123118A (zh) 2008-02-13
CN101123118B (zh) 2011-11-30
US20080013378A1 (en) 2008-01-17

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