WO2023028846A1 - 存储器、存储器的编程方法及编程验证方法、存储器系统 - Google Patents

存储器、存储器的编程方法及编程验证方法、存储器系统 Download PDF

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WO2023028846A1
WO2023028846A1 PCT/CN2021/115699 CN2021115699W WO2023028846A1 WO 2023028846 A1 WO2023028846 A1 WO 2023028846A1 CN 2021115699 W CN2021115699 W CN 2021115699W WO 2023028846 A1 WO2023028846 A1 WO 2023028846A1
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state
programming
verification
result
memory
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PCT/CN2021/115699
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English (en)
French (fr)
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郭晓江
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长江存储科技有限责任公司
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Priority to PCT/CN2021/115699 priority Critical patent/WO2023028846A1/zh
Priority to CN202180003091.2A priority patent/CN113892141A/zh
Priority to US18/091,231 priority patent/US20230148366A1/en
Publication of WO2023028846A1 publication Critical patent/WO2023028846A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • Embodiments of the present disclosure relate to but are not limited to the field of semiconductors, and in particular, relate to a memory, a memory programming method, a programming verification method, and a memory system.
  • Flash memory is widely used as a storage medium of portable electronic devices such as mobile phones and digital cameras. Flash memory typically uses one-transistor memory cells that allow for high memory density, high reliability, and low power consumption. Changes in the threshold voltage of memory cells determine the data state (e.g., data value ).
  • Embodiments of the present disclosure provide a memory, a memory programming method, a programming verification method, and a memory system.
  • a program verification method for a memory including:
  • the programming state range of the i-th programming verification operation verification is from the nth state to the n+kth state, i and n are positive integers, k is a natural number, and the n+k states are less than or equal to the highest programmed state of said memory;
  • the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result determine the programming state range that needs to be verified for the i+1th programming verification operation
  • the (i+1)th programming verification operation is performed according to the determined program state range to be verified by the i+1th programming verification operation.
  • determine the programming state range that needs to be verified in the (i+1)th programming verification operation include:
  • the verifier result of the nth state in the ith verification result includes: the ith statistical data of the nth state, used to count the number of failed bits programmed to the nth state;
  • the determining the lowest programming state that needs to be verified for the i+1th programming verification operation according to the verification sub-result of the nth state in the ith verification result includes:
  • the state is the n+1th state
  • the ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is greater than or equal to the first preset ratio, it is determined that the i+1th programming verification operation needs The lowest programmed state to verify is the nth state.
  • the method also includes:
  • a value range of the first preset value or a value range of the first preset ratio is determined according to the number of cycles.
  • the value range of the first preset value is within the allowable range of the error correction code error correction mechanism performed on the memory.
  • the verification sub-results of the n+kth state in the ith verification result include: i-th statistical data of the n+kth state, used to count the number of successful bits programmed to the n+kth state ;
  • determining the highest programming state that needs to be verified in the i+1th programming verification operation includes:
  • the n+kth state When the number of successful bits programmed to the n+kth state is greater than a second preset value, and the n+kth state is less than the highest programmed state of the memory, determine the i+1th programming The highest programming state that needs to be verified in the verification operation is the n+k+1th state;
  • the method also includes:
  • step size and/or programming voltage slope of incremental step pulse programming determine the value of the second preset value or the second preset ratio according to the step size and/or the programming voltage slope Range; wherein, the programming verification method is applied in the incremental step pulse programming method;
  • the number of cycles of the storage unit to be programmed is obtained; and according to the number of cycles, a value range of the second preset value or a value range of the second preset ratio is determined.
  • the value range of the second preset ratio is 2% to 3%.
  • determining the programming state range that needs to be verified for the (i+1)th programming verification operation includes :
  • the highest programming state to be verified in the i+1th program verification operation is determined according to the i-th sampling statistical data of the n+k-th state.
  • a memory programming method including:
  • the The programming of the nth state and the programming of the n+k state count the number of failed bits to obtain the i-th counting result; wherein, the range of the programming state verified by the i-th programming verification operation is the nth state to the n+kth state, i and n are positive integers, k is a natural number, and the n+kth state is less than or equal to the highest programming state of the memory;
  • the programming state range verified by the i-th programming verification operation is the nth state to the n+kth state, i and n is a positive integer, k is a natural number, and the n+kth state is less than or equal to the highest programming state of the memory;
  • the (i+1)th program verification operation is performed according to the determined program state range to be verified by the i+1th program verification operation.
  • the ith counting result includes: the number of failed bits for programming the nth state in the ith programming operation;
  • determining the programming state range that needs to be verified in the i+1th programming verification operation includes:
  • the state is the n+1th state
  • the ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is greater than or equal to the first preset ratio, it is determined that the i+1th programming verification operation needs The lowest programmed state to verify is the nth state.
  • the i-th counting result includes: the number of failed bits for programming the n+k-th state in the i-th programming operation;
  • determining the programming state range that needs to be verified in the i+1th programming verification operation includes:
  • the highest programming state to be verified is the n+k+1th state
  • the programming and The programming of the n+k state counts the number of failed bits, and obtains the i-th counting result, including:
  • the programming of the n-th state and the programming of the n+k-th state in the i-th programming operation fail bit number counting, to obtain the i-th counting result.
  • a memory including:
  • an array of memory cells comprising a plurality of rows of memory cells
  • peripheral circuitry coupled to the plurality of word lines and configured to perform a program verify operation on a selected row of memory cells of the plurality of rows of memory cells, the selected row of memory cells being coupled to a selected row of memory cells word line, wherein, to perform the program verify operation, the peripheral circuit is configured to:
  • the programming state range of the i-th programming verification operation verification is from the nth state to the n+kth state, i and n are positive integers, k is a natural number, and the n+k states are less than or equal to the highest programmed state of said memory;
  • the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result determine the programming state range that needs to be verified for the i+1th programming verification operation
  • the (i+1)th program verification operation is performed according to the determined program state range to be verified by the i+1th program verification operation.
  • a memory including:
  • an array of memory cells comprising a plurality of rows of memory cells
  • peripheral circuitry coupled to the plurality of word lines and configured to perform a program operation on a selected row of memory cells of the plurality of rows of memory cells, the selected row of memory cells coupled to a selected word line line, wherein, in order to perform the programming operation, the peripheral circuit is configured to:
  • the The programming of the nth state and the programming of the n+k state count the number of failed bits to obtain the i-th counting result; wherein, the range of the programming state verified by the i-th programming verification operation is the nth state to the n+kth state, i and n are positive integers, k is a natural number, and the n+kth state is less than or equal to the highest programming state of the memory;
  • the (i+1)th program verification operation is performed according to the determined program state range to be verified by the i+1th program verification operation.
  • a memory system including:
  • a memory controller coupled to the memory and configured to control the memory.
  • a fixed start time (start loop) is usually determined for each programming state to be verified based on empirical values, for example, after the third programming pulse is applied (that is, the third programming pulse is applied), the The program verification (PV2) is performed in the second state, and the verification initial cycle of the second state is 3.
  • start loop the third programming pulse is applied
  • PV2 The program verification
  • this fixed start time determined based on empirical values may not be the most suitable start time for verification.
  • the set verification start time is earlier than the most suitable verification start time, starting the program verification too early will prolong the program verification operation time, thereby prolonging the programming duration.
  • an over-program phenomenon may occur, thereby reducing the programming quality.
  • the i+1th program verification operation to be executed after the next program pulse is applied is determined.
  • the programming state range that needs to be verified that is, the programming state range that needs to be verified in the next programming verification operation is determined according to the result of the previous programming verification operation, and the starting moment of each programming state to be verified can be dynamically determined. Not only the method is simple, but also It can improve the accuracy of the determined starting time of each programming state to be verified.
  • the embodiments of the present disclosure do not need to manually set fixed start times, and The difference in memory programming performance can be tracked through the verification results, and then the programming state range that needs to be verified for each programming verification operation can be automatically determined. programming quality.
  • Fig. 1 is a threshold voltage distribution diagram of a programming operation shown according to an exemplary embodiment
  • Fig. 2 is a flow chart of a program verification method according to an exemplary embodiment
  • FIG. 3 is a flowchart of a programming method shown according to an exemplary embodiment
  • Fig. 4 is a partial flowchart of a programming method according to an exemplary embodiment
  • Fig. 5 is a schematic diagram of a memory according to an exemplary embodiment
  • Fig. 6 is a partial cross-sectional view of a memory cell array including NAND memory strings according to an exemplary embodiment
  • FIG. 7 is a block diagram of a memory including a memory cell array and peripheral circuits shown according to an exemplary embodiment
  • Fig. 8 is a schematic diagram of another memory according to an exemplary embodiment
  • Fig. 9a is a block diagram of a memory system according to an exemplary embodiment
  • Fig. 9b is a block diagram of another memory system shown according to an exemplary embodiment.
  • Fig. 10a is a schematic diagram of a memory card according to an exemplary embodiment
  • Fig. 10b is a schematic diagram of a solid state drive (SSD) according to an exemplary embodiment.
  • SSD solid state drive
  • the term "A is connected to B" includes the situation that A and B are connected to each other and A and B are in contact with each other, or there are other components interposed between A and B and A is connected to each other in a non-contact manner. The case where B is connected.
  • first”, “second”, etc. are used to distinguish similar objects, and not necessarily used to describe a specific sequence or sequence. It can be understood that “first”, “second”, etc. may be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be used in a manner other than what is illustrated or described herein. implemented sequentially.
  • the term "layer" refers to a portion of material comprising a region having a thickness.
  • a layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure.
  • a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure.
  • a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of the continuous structure.
  • Layers may extend horizontally, vertically and/or along sloped surfaces.
  • Layers can include multiple sublayers.
  • an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.
  • NAND memory is a non-volatile memory device (Non-volatile Memory Device). It uses a nonlinear macro-cell mode inside, which has the advantages of large capacity and fast rewriting speed, and is suitable for storing large amounts of data. NAND memory is widely used in embedded products, such as digital cameras, MP3 player memory cards, and compact U disks.
  • the storage units of early NAND memory particles are mostly single-level cells (Single-Level Cell, SLC), that is, one storage unit stores 1 bit (bit) data, and each storage unit has two states at this time , specifically 0 and 1.
  • SLC Single-Level Cell
  • the storage unit of NAND memory particles has gradually evolved from a single-level cell to a multi-level cell (Multi-Level Cell, MLC), that is, a storage unit stores 2 bits of data, and then a triple-level cell (Triple-Level Cell) is introduced.
  • MLC multi-level cell
  • Triple-Level Cell triple-level cell
  • Level Cell, TLC that is, a storage unit stores 3-bit data
  • QLC quad-level cell
  • the state of the NAND memory particle storage unit is also determined by 2 becomes 4, 8 or even 16.
  • the operation of NAND memory includes three parts: erasing operation, programming (writing operation) and reading operation.
  • the erasing operation can be performed in units of blocks (Block), and the programming and reading operations can be performed in units of pages (Page).
  • the process is further divided into three steps, for example, pressurization programming (that is, applying a programming pulse), program verification (Program Verify, PV) and scanning verification results.
  • the programming time (t PROG ) is an important index to measure the performance of NAND memory. Therefore, R&D personnel have been working on how to improve the programming speed and shorten the programming time under the premise of ensuring the programming quality (for example, ensuring the read budget window, Read Budget Window). Since the duration of the applied programming pulse cannot be changed, the number of applied programming pulses, the number of programming verifications, the time for each programming verification, and the time for scanning and verifying the results are all important factors in determining the programming time. .
  • the TLC memory cell has 1 erased state and 7 programmed states, and its programmed states are sequentially recorded as L1, L2, L3, L4, L5, L6 and L7 from the 1st state to the 7th state.
  • the traditional programming method for TLC is to start the program verification operation for each state between the application of two adjacent programming pulses. The problem with this method is that after the first programming pulse is applied, only a very small number of memory cells actually reach the L1 state, and none of the memory cells reach the L2, L3, L4, L5, L6, and L7 states.
  • Table 1 shows the corresponding start time of each programming verification state in the improved related programming verification method.
  • PV1 represents the programming verification operation on the first state (L1)
  • PV2 represents the programming verification operation on the second state (L2)
  • PV3 represents the programming verification operation on the third state (L3)
  • PV4 represents the fourth state (L4) performs a program verification operation
  • PV5 indicates a program verification operation for the fifth state (L5)
  • PV6 indicates a program verification operation for the sixth state (L6)
  • PV7 indicates a program verification operation for the seventh state (L7).
  • the start time of the program verification operation can be defined by the number of programming pulses the program verification operation starts after. For example, the start time of the program verification operation in the first state is 1, which means that the program verification operation is applied after the first pulse is applied. After the program pulse, and before the second program pulse is applied, program verify for the first state begins.
  • all memory cells to be programmed are programmed from the erased state.
  • the threshold voltage of a memory cell to be programmed can reach a higher programmed state after several programming pulses are applied. Therefore, in the related art, the programming speed can be improved by reducing the number of program verifications.
  • the improved programming method does not need to perform the program verification operation of the higher programming state after the programming pulse applied earlier.
  • the program verification method uses a fixed start time to control when to start the program verification of each programming state.
  • the start time of the program verification operation for the 3rd state is set to 4, that is, after the first 3 programming pulses are applied, the 3rd state does not need to be verified, but starts after the 4th programming pulse is applied.
  • Carry out the program verification operation of the third state ie PV3.
  • the improved above-mentioned method reduces the number of program verification times to a certain extent. For each state, setting the same start time for all dies, blocks, or word lines (Word Line, WL) will still cause errors. Therefore, in order to ensure the programming quality, when setting the initial time of the program verification operation of each programming state, it is necessary to set aside enough margin (margin), and when the units of programming are different, it is necessary to set the value of each program according to the empirical value. Each unit sets the corresponding fixed programming verification operation start time, which consumes a lot of circuit resources and increases the test time.
  • the programming characteristics of NAND are also affected by many other factors. For example, as conditions such as cycle number (cycling) or temperature change, the performance of each memory cell will change, resulting in different programming performance of NAND.
  • the fixed start time is not the most suitable start time.
  • the fixed starting time set by the program verifying operation is earlier than the most suitable starting time, starting the program verifying too early will prolong the time of the verifying operation, thereby prolonging the programming duration.
  • the fixed start time of the program verify operation is set later than the most suitable start time, over-programming may occur and the programming quality will be reduced.
  • FIG. 1 is a threshold voltage distribution diagram showing a programming operation of a memory according to an exemplary embodiment. It should be noted that the TLC has 7 programming states, and FIG. 1 only shows programming of 5 programming states (ie, L1 to L5 ) as an example.
  • each sub-graph includes 5 curves, and each curve represents the distribution of memory cells with the same target programming state after a programming pulse is applied.
  • V th1 , V th2 , V th3 , V th4 , V th5 , V th6 and V th7 respectively represent: the initial threshold voltage of the first state, the initial threshold voltage of the second state, and the initial threshold voltage of the third state. Threshold voltage, the initial threshold voltage of the 4th state, the initial threshold voltage of the 5th state, the initial threshold voltage of the 6th state, and the initial threshold voltage of the 7th state. specifically:
  • Figure (a) shows the threshold voltage distribution curve obtained by performing the first programming verification operation on the memory cell after the first programming pulse is applied starting from the erasing state.
  • the first program verification operation includes program verification (PV1) performed on the first state, that is, the range of the program state verified by the first program verification operation is L1.
  • Figure (b) shows the threshold voltage distribution curve obtained by performing the second programming verification operation on the memory cell after applying the next programming pulse on the basis of Figure (a), that is, Figure (b) shows the threshold voltage distribution curve obtained from the erase State start, after applying the second programming pulse, the threshold voltage distribution curve obtained by performing the second program verification operation on the memory cell.
  • the second program verification operation includes program verification (PV1) performed on the first state, that is, the range of the program state verified by the second program verification operation is L1.
  • the scheme of setting the start time of program verification operation on the second state to 2 It will increase the time of programming verification, thereby increasing the programming time. That is to say, when the fixed starting time set by the program verifying operation is earlier than the most suitable starting time, starting the program verifying too early will prolong the time of the verifying operation, thereby prolonging the programming duration.
  • Figure (c) shows the threshold voltage distribution curve obtained by performing the third program verification operation on the memory cell after applying the next programming pulse on the basis of Figure (b), that is, Figure (c) shows the threshold voltage distribution curve obtained from the erase The threshold voltage distribution curve obtained by performing the third programming verification operation on the memory cell after the third programming pulse is applied at the beginning of the state.
  • the third program verification operation includes program verification (PV1) for the first state and program verification (PV2) for the second state, and the range of the program states verified by the third program verification operation is L1 to L2.
  • Figure (d) shows the threshold voltage distribution curve obtained by performing the fourth program verification operation on the memory cell after applying the next programming pulse on the basis of Figure (c), that is, Figure (d) shows the threshold voltage distribution curve from the erase
  • the threshold voltage distribution curve obtained by performing the fourth programming verification operation on the memory cell after the fourth programming pulse is applied at the beginning of the state.
  • the fourth program verification operation includes program verification (PV1) performed on the first state and program verification (PV2) performed on the second state, and the range of program states verified by the fourth program verification operation is L1 to L2.
  • Figure (e) shows the threshold voltage distribution curve obtained by performing the fifth program verification operation on the memory cell after applying the next programming pulse on the basis of Figure (d), that is, Figure (e) shows the threshold voltage distribution curve from the erase
  • the threshold voltage distribution curve obtained by performing the fifth programming verification operation on the memory cell after the fifth programming pulse is applied at the beginning of the state.
  • the fifth programming verification operation includes programming verification (PV1) for the first state, programming verification (PV2) for the second state, and programming verification (PV3) for the third state, and the programming for the fifth programming verification operation verification
  • the state range is L1 to L3.
  • Figure (f) shows the threshold voltage distribution curve obtained by performing the sixth program verification operation on the memory cell after applying the next programming pulse on the basis of Figure (e), that is, Figure (e) shows the The threshold voltage distribution curve obtained by performing the sixth programming verification operation on the memory cell after the sixth programming pulse is applied at the beginning of the state.
  • the sixth programming verification operation includes programming verification (PV1) for the first state, programming verification (PV2) for the second state, and programming verification (PV3) for the third state, and programming for the sixth programming verification operation verification.
  • the state range is L1 to L3.
  • Figure (g) shows the threshold voltage distribution curve obtained by performing the seventh program verification operation on the memory cell after applying the next programming pulse on the basis of figure (f), that is, figure (g) shows the threshold voltage distribution curve from the erase
  • the threshold voltage distribution curve obtained by performing the seventh programming verification operation on the memory cell after the seventh programming pulse is applied at the beginning of the state.
  • the seventh programming verification operation includes programming verification (PV2) carried out on the 2nd state, programming verification (PV3) carried out on the 3rd state, and programming verification (PV4) carried out on the 4th state, the programming of the seventh programming verification operation verification
  • the state range is L2 to L4.
  • Figure (h) shows the threshold voltage distribution curve obtained by performing the eighth program verification operation on the memory cell after applying the next programming pulse on the basis of Figure (g), that is, Figure (h) shows the threshold voltage distribution curve obtained from the erase
  • the threshold voltage distribution curve obtained by performing the eighth programming verification operation on the memory cell after the eighth programming pulse is applied at the beginning of the state.
  • the eighth programming verification operation includes programming verification (PV2) for the second state, programming verification (PV3) for the third state, and programming verification (PV4) for the fourth state, and the programming for the eighth programming verification operation verification
  • the state range is L2 to L4. And so on until the programming is completed.
  • the threshold voltages of memory cells in different programming states will move simultaneously.
  • a program inhibit condition can be applied to this memory cell so that when the next programming pulse is applied, the threshold voltage of the memory cell that reached the target threshold voltage will not occur again move. It can be understood that, in the process of applying the next programming pulse, the threshold voltage of the memory cells that have not reached the target threshold voltage will increase, and the threshold voltage distribution curve will move to a higher threshold voltage direction.
  • the threshold voltage range of the higher programmed state can be predicted according to the information obtained by performing program verification on the lower programmed state.
  • the memory cell can reach the 3rd state, that is, the 3rd state will not be programmed successfully. Therefore, it is not necessary to start the program verification operation for the 3rd state after the next programming pulse is applied, so that the next program verification operation can be reduced.
  • the number of programming states is beneficial to shorten the programming verification time, reduce the number of verification results to be processed, and improve programming efficiency.
  • the present disclosure provides a memory program verification method of an embodiment, as shown in FIG. 2 , the program verification method includes the following steps:
  • S100 Obtain the i-th verification result of the i-th programming verification operation; wherein, the programming state range of the i-th programming verification operation verification is from the nth state to the n+kth state, i and n are positive integers, k is a natural number, and The n+k state is less than or equal to the highest programmed state of the memory;
  • S120 Execute the i+1th programming verification operation according to the determined programming state range to be verified by the i+1th programming verification operation.
  • the memory may include a storage array composed of a plurality of memory cells, and the memory cells may include single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC) or levels more units etc.
  • SLC single-level cells
  • MLC multi-level cells
  • TLC triple-level cells
  • QLC quad-level cells
  • the i-th program verification operation can be understood as a program verification operation performed on the memory cell to be programmed after the i-th program pulse is applied and before the i+1-th program pulse is applied from the erased state.
  • the programming state range of the i-th programming verification operation verification is from the nth state to the n+kth state, that is, the lowest state of the i-th programming verification operation verification is the nth state, the highest state is the n+kth state, and the i-th programming verification The operation needs to verify the state between the nth state and the n+kth state.
  • the i-th verification result is used to represent the programming result of the memory cell to be programmed after i programming pulses are applied.
  • the i-th verification result may include at least one of the following: the first type of indication information indicating whether each memory cell verified has passed programming; the second type of indication information indicating whether each memory cell verified has failed programming; indicating that the target programming state has been reached.
  • the third type of indication information for the number of storage units.
  • the verification sub-result of the nth state is used to represent the program verification result obtained by performing program verification on the memory cell whose target programming state is the nth state during the i-th program verification operation.
  • the verification sub-result of the nth state may include at least one of the following: indicating whether the target programming state is the first type of indication information for each memory cell of the nth state; indicating that the target programming state is each memory cell of the nth state The second type of indication information indicating whether programming has failed; the third type of indication information indicating the number of memory cells reaching the target programming state of the nth state.
  • the verification sub-result of the n+kth state is used to represent the program verification result of the memory cell whose target programming state is the n+kth state during the i-th program verification operation.
  • the verification sub-result of the n+kth state may include at least one of the following: indicating whether the target programming state is the first type of indication information for each memory cell of the n+kth state; indicating that the target programming state is the n+kth state
  • the second type of indication information indicates whether each memory cell in the state has failed programming; the third type of indication information indicates the number of memory cells that have reached the target programming state of the n+kth state.
  • the value of k may be equal to 0.
  • the value of n is equal to the value of n+k, that is, the ith program verification operation only performs program verification on the nth state.
  • the highest programming state of the memory is the 7th state, therefore, the value of n+k is less than or equal to 7.
  • the highest programming state of the memory is the 15th state, therefore, the value of n+k is less than or equal to 15.
  • determining the program state range to be verified in the (i+1)th program verification operation may include determining a verification level range in the (i+1)th program verification operation.
  • S110 includes:
  • program verification may be performed on all memory cells in the target state within the range of the programming state to be verified in the (i+1)th program verification operation.
  • the (i+1)th program verification can also be performed only on the memory cells whose target state is within the range of the programming state that needs to be verified in the (i+1)th program verification operation and that have not been successfully programmed in the previous programming, so that Reduce the number of memory cells that need to be verified and shorten the program verification time.
  • the i+1th verification result obtained not only includes data indicating whether the memory cell that performs the i+1th program verification is successfully programmed, but also includes information indicating the number of memory cells that have been successfully programmed .
  • the (i+1)th program verification operation may be performed after the (i+1)th programming pulse is applied. It can be understood that the steps given in the above program verification method can be executed cyclically until the programming is completed, or until the number of times of program verification that can be performed reaches the maximum value.
  • the i+1th program verification operation to be executed after the next program pulse is applied is determined.
  • the programming state range that needs to be verified that is, the programming state range that needs to be verified in the next programming verification operation is determined according to the result of the previous programming verification operation, and the starting moment of each programming state to be verified can be dynamically determined, and each determined to be verified can be improved. Verify the accuracy of the starting time of the programming state. On the one hand, it can reduce the increase in the programming time caused by setting the programming verification starting time too early, which is beneficial to shorten the programming time; on the other hand, it can reduce the Over-programming caused by setting too late is conducive to ensuring better programming quality.
  • the embodiments of the present disclosure do not need to be manually set.
  • the starting time is fixed, but the difference in memory programming performance is tracked through the verification results, and then the programming state range that needs to be verified for each programming verification operation is automatically determined.
  • the method is simple, and the program verification operation needs to be verified according to the memory performance.
  • the dynamic range is beneficial to improve the programming quality.
  • the verifier result of the nth state in the ith verification result includes: the ith statistical data of the nth state, used to count the number of failed bits programmed to the nth state;
  • determining the lowest programming state that needs to be verified for the i+1th programming verification operation includes:
  • the i-th statistical data of the n-th state may include: data indicating whether the n-th program verification operation for each memory cell whose target state is the n-th state passes. According to the i-th statistical data of the n-th state, the number of failed bits for the i-th programming operation on the n-th state can be determined.
  • a binary code may be used to indicate whether the memory cell is programmed or not. For example, 0 may be used to indicate that the programming has been passed, and 1 may be used to indicate that the programming has failed; During implementation, those skilled in the art can choose an appropriate way to indicate whether the memory cell has been programmed according to the actual situation, which is not limited in the embodiments of the present disclosure.
  • the number of failed bits for programming the nth state is greater than or equal to the first preset value, it can be considered that the programming for the nth state has not been successful, so in the next programming verification process, it is necessary to continue to perform programming verification for the nth state .
  • the ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is less than a first preset ratio, determine the minimum program that needs to be verified for the i+1th program verification operation The state is the n+1th state;
  • the ratio of the number of failed bits programmed to the nth state to the number of bits in the target state being the nth state is greater than or equal to the first preset ratio, it is determined that the i+1th programming verification operation needs to verify the lowest programming state to be the nth state.
  • the ratio of the number of bits that fail to program the nth state to the number of bits in the nth state as the target state is less than the first preset value, it can be considered that the programming of the nth state is successfully completed. Therefore, in the next programming During the verification process, there is no need to perform programming verification on the nth state. In this way, compared with verifying the nth state every time, the program verification time can be shortened and the programming speed can be increased.
  • the method also includes:
  • the value range of the first preset value or the value range of the first preset ratio is determined.
  • Performing one erase operation and one write operation on the memory is called a cycle.
  • the programming performance of the memory may change, resulting in a change in programming speed.
  • a loop is defined in the smallest unit of programming. For example, when a block is used as the minimum unit for programming, the number of cycles of each storage unit in the block is basically the same.
  • the number of cycles obtained is the number of cycles of the minimum unit for programming.
  • the embodiment of the present disclosure Compared with providing a fixed first preset value, in the embodiment of the present disclosure, by obtaining the number of cycles of the memory cell to be programmed, and determining the first preset value according to the number of cycles, it is possible to trace the following cycles during the program verification process.
  • the programming characteristic changes with the number of times, and then flexibly adjusts the range of the first preset value, reducing the slow programming speed caused by improper determination of the first preset value, which is conducive to improving the programming speed and ensuring better programming quality.
  • the value range of the first preset value is within a range allowed by an error correction code (Error Correcting Code, ECC) error correction mechanism for the memory.
  • ECC Error Correcting Code
  • ECC since the value range of the first preset value is within the range allowed by the ECC mechanism, when the number of failed bits for programming the nth state is less than the first preset value, ECC can be used to correct The error mechanism corrects the failed bits to ensure that the programming of the nth state can be successfully completed, and the next programming verification does not need to verify the nth state, which is conducive to reducing the number of programming states that need to be verified and improving programming efficiency.
  • the value range of the first preset ratio is 0.4% to 0.6%.
  • the value of the first preset ratio may be 0.5%.
  • the verification sub-results of the n+kth state in the i-th verification result include: i-th statistical data of the n+kth state, used to count the number of successful bits programmed to the n+kth state;
  • determining the highest programming state that needs to be verified in the i+1th programming verification operation includes:
  • the highest programming state to be verified by the i+1th programming verification operation is the first n+k+1 state
  • the i-th statistical data of the n+k-th state may include: data indicating whether the n-th program verification operation for each memory cell whose target state is the n+k-th state is passed. According to the i-th statistical data of the n+k-th state, the number of failed bits for the i-th programming operation on the n+k-th state can be determined.
  • the number of successful bits programmed to the n+k state is greater than the second preset value, and the n+k state is less than the highest programming state of the memory, it can be considered that after the programming pulse is applied next time, many target programming states may be The memory cell in the n+kth state will reach the target state, and there may be a memory cell whose target state is the n+k+1th state will reach the target state. Therefore, in the next program verification process, it is necessary to check the n+k+th Program verification is performed on the 1st state to reduce over-programming caused by starting verification of the n+k+1th state too late.
  • the target state is the n+th
  • the probability of the memory cell in the k+1 state reaching the target state is very low. Therefore, in the next programming verification process, there is no need to start verifying the n+k+1 state, and the highest state to be verified in the next programming verification operation is still the n+th state. k state.
  • the ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is greater than a second preset ratio, it is determined that the i+1th program verification operation requires The highest programming state verified is the n+k+1th state;
  • the ratio of the number of successful bits programmed to the n+kth state to the number of bits in the n+kth state being the target state is less than or equal to the second preset ratio, determine the highest programming that needs to be verified in the i+1th programming verification operation
  • the state is the n+kth state.
  • the ratio of the number of successful bits programmed to the n+k state and the number of bits in the target state being the n+k state is greater than the second preset value, and the n+k state is less than the highest programming state of the memory , it can be considered that after the next programming pulse is applied, there may be many memory cells whose target programming state is the n+kth state will reach the target state, and there may be memory cells whose target state is the n+k+1th state will reach the target state , therefore, in the next program verification process, it is necessary to start program verification for the n+k+1th state, so as to reduce overprogramming caused by starting verification of the n+k+1th state too late.
  • the method also includes:
  • the value range of the second preset value or the value range of the second preset ratio is determined.
  • the embodiment of the present disclosure Compared with providing a fixed second preset value, in the embodiment of the present disclosure, by obtaining the number of cycles of the memory cell to be programmed, and determining the second preset value according to the number of cycles, it is possible to trace the following cycles during the program verification process.
  • the programming characteristic changes with the number of times, and then flexibly adjusts the range of the second preset value, reducing the slow programming speed caused by improper setting of the second preset value, which is conducive to improving the programming speed and ensuring better programming quality.
  • the value range of the second preset ratio is 2% to 3%.
  • the value of the second preset ratio may be 2.3%.
  • each programming pulse will move the threshold voltage distribution by ⁇ 2 times of sigma, and the verification level between different programming states The difference is around 3 times sigma.
  • the value of the second preset value can be set to Outside of positive 2x sigma (ie 2.3%).
  • the ratio of the number of successful bits programmed to the n+k state to the number of bits whose target state is the n+k state is greater than 2.3%, it can be considered that after the programming pulse is applied next time, there may be many (for example, 50%) )
  • the memory cell whose target programming state is the n+kth state will reach the target state, and since the target threshold voltage distribution of the n+k+1th state is at negative 3 times sigma, the target state will also start to appear as When the memory cell in the n+k+1th state reaches the target threshold voltage, it is necessary to start verifying the n+k+1th state during the next programming verification.
  • the program verification method is applied to an incremental step pulse programming method, and the program verification method further includes:
  • the value range of the second preset value is determined according to the step size and/or the programmed voltage slope; or, the value range of the second preset ratio is determined according to the step size and the programmed voltage slope.
  • the memory may be programmed in an incremental step pulse programming (Incremental Step Pulse Programming, ISPP) manner.
  • ISPP Intelligent Step Pulse Programming
  • the threshold voltage of the memory cell increases greatly after applying each programming pulse, therefore, the values of the second preset value and the second preset ratio can be relatively Small.
  • the threshold voltage of the memory cell increases slightly after applying each programming pulse, therefore, the second preset value and the second preset ratio can be relatively large.
  • coarse programming coarse programming
  • fine programming fine programming
  • the step size of the coarse programming is larger than the step size of the fine programming. Therefore, when using the coarse programming, the second preset value The value is smaller than the value of the second preset value when fine-tuning programming is used; or, the value of the second preset ratio when coarse-tuning programming is used is smaller than the value of the second preset ratio when fine-tuning programming is used.
  • the embodiment of the present disclosure by obtaining the step size and/or programming voltage slope of the incremental step pulse programming, and according to the step size and/or programming
  • the voltage slope determines the value range of the second preset value; or, according to the step size and the programming voltage slope, determines the value range of the second preset ratio, and the second preset value and the second preset ratio can be flexibly adjusted range, reducing the slow programming speed caused by improper setting of the second preset value and the second preset ratio, which is conducive to improving the programming speed and ensuring better programming quality.
  • S110 includes:
  • the generated verification results can be stored in the page buffer (page buffer), and these data can be used to determine the memory cells that need to be applied with the program prohibition voltage during the subsequent application of the program pulse.
  • the verification result can be stored in a dedicated latch in the page buffer, and the specific latch is only used to temporarily store the verification result of the program verification operation.
  • the verification result can also be stored in some other latches in the page buffer, and these latches can also be used to store programming data, or program prohibition information, and the like.
  • the i-th sampling statistical data of the n-th state may include: randomly sampling the verification results of all memory cells whose target programming state is the n-th state, and statistical data obtained by counting the number of failed bits on the sampling results.
  • the i-th sampling statistical data of the n+k-th state may include: randomly sampling the verification results of all memory cells whose target programming state is the n+k-th state, and statistical data obtained by counting the number of failed bits on the sampling results.
  • the verification results stored in 4KB of the latches can be randomly selected as sample data to determine the i+1th programming verification operation needs The lowest and highest programming states verified.
  • the data stored in the 2KB or 8KB latches can also be randomly selected as the sampling sample data to determine the lowest programming state and the highest programming state that need to be verified in the i+1 program verification operation. state.
  • the generated verification results include a relatively large amount of data, especially when program verification is performed on each memory cell to be programmed. Therefore, if the verification results of all memory cells are counted and counted, the time required for counting the number of failed bits will be prolonged, resulting in an increase in programming time.
  • the i-th sampling statistical data of the n-th state and the i-th sampling statistics of the n+k state are obtained data, and according to the i-th sampling statistical data of the n-th state, determine the lowest programming state that needs to be verified for the i+1-th programming verification operation, and determine the i+1-th programming verification operation according to the i-th sampling statistical data of the n+k-th state
  • the highest programming state that needs to be verified can reduce the total amount of data that needs to be counted each time the number of failed bits is counted, which is conducive to shortening the time for counting the number of failed bits and improving the determination range of the programming state that needs to be verified in the i+1th programming verification operation , thereby increasing the programming speed, shortening the programming time, and improving memory performance.
  • programming of a memory is generally performed using an iterative process of applying a programming pulse to a memory cell, and verifying whether the memory cell has reached a desired data state (i.e., a target programming state) in response to the programming pulse, and The iterative process is repeated until the memory cell program verification is passed.
  • a desired data state i.e., a target programming state
  • FBC Fail Bit Count
  • FIG. 3 is a flow chart showing a memory programming method according to an exemplary embodiment. Shown in Fig. 3 with reference to, described programming method comprises the following steps:
  • S210 During the process of applying the i+1th programming pulse, according to the verifier result of the nth state and the verifier result of the n+kth state in the ith verification result of the ith programming verification operation, perform The programming of the nth state and the programming of the n+k state count the number of failed bits to obtain the i-th counting result; wherein, the range of the programming state verified by the i-th programming verification operation is the nth state to the n+kth state, i and n are positive integers, k is a natural number, and the n+kth state is less than or equal to the highest programming state of the memory;
  • a program pulse application operation may be performed on the memory cell array through the program operation circuit in the peripheral circuit of the memory device, so as to control the potential level of the bit line of the selected memory cell array.
  • the i+1th programming pulse process may include an i+1th programming preparation operation phase and an i+1th programming stable execution phase.
  • the (i+1)th programming preparation operation is to perform the state and data preparation operation related to the (i+1)th programming operation, and in the voltage sequence, it corresponds to the stage of applying the (i+1)th pass voltage (Vpass) to the selected word line.
  • the +1 program stable execution phase is to control the potential level of the bit line of the memory cell array in response to the program data during the program pulse application operation, and corresponds to the phase of applying the (i+1) th program voltage to the selected word line in voltage timing.
  • the i+1th programming stable execution stage may be read for the ith statistical data.
  • the i-th counting result may include the i-th statistical data of the n-th state and the i-th statistical data of the n+k-th state in the program verification method described above.
  • the i-th counting result may include the i-th sampling statistical data in the above-mentioned program verification method.
  • the programming method provided by the disclosed embodiment can, in the process of applying the i+1th programming pulse, according to the verifier result of the nth state and the verifier result of the n+kth state in the ith verification result of the ith programming verification operation , respectively count the number of failed bits for the programming result of the nth state and the programming result of the n+kth state to determine the programming state range that needs to be verified in the i+1th programming verification operation.
  • the operation of counting the number of failed bits does not take extra time, so that the execution time of the iterative process of the entire programming operation can be saved, and the efficiency of programming memory cells can be improved.
  • the embodiments of the present disclosure can save logic overhead by hiding the process of counting the number of failed bits in the process of applying programming pulses.
  • S220 may be executed between S210 and S230.
  • S220 may overlap with S210 in terms of time sequence. Specifically, S220 may be executed during the application of the i+1 programming pulse and after the i th counting result is obtained. In this way, the range of programming states to be verified for the i+1th programming verification operation can be hidden in the process of applying the i+1th programming pulse, so that in the iterative process of the entire programming operation, it is determined that the i+1th programming verification operation Operations in the range of programming states that need to be verified do not take extra time, so that the execution time of the iterative process of the entire programming operation can be further saved, and the efficiency of programming memory cells can be improved.
  • the i-th counting result includes: the number of failed bits for programming the n-th state in the i-th programming operation;
  • S220 may include:
  • the number of failed bits for programming the nth state is greater than or equal to the first preset value, it is determined that the lowest programming state to be verified by the (i+1)th program verification operation is the nth state.
  • S220 may include:
  • determine the minimum programming that needs to be verified for the i+1th programming verification operation state is the nth state.
  • the i-th counting result includes: the number of failed bits for programming the n+k-th state in the i-th programming operation;
  • S220 may include:
  • S220 may include:
  • the ratio of the number of successful bits programmed to the n+kth state to the number of bits in the n+kth state being the target state is less than or equal to the second preset ratio, determine the highest programming that needs to be verified in the i+1th programming verification operation
  • the state is the n+kth state.
  • S210 may include:
  • the number of failed bits is counted for the programming of the nth state and the programming of the n+k state in the ith programming operation, and the number of failed bits is obtained. i counts the result.
  • the i-th counting result may include the i-th sampling statistical data of the n-th state and the i-th sampling statistical data of the n+k-th state.
  • the verification results of all memory cells whose target programming state is the nth state can be randomly sampled to obtain the i-th sampling sample data of the n-th state, and then the i-th sampling sample data of the n-th state can be counted as failure bits Statistically obtain the i-th sampling statistical data of the n-th state.
  • the verification results of all memory cells whose target programming state is the n+kth state can be randomly sampled to obtain the i-th sampling sample data of the n+k-th state, and then the i-th sampling sample data of the n+k-th state Statistics of the number of failed bits are performed on the data to obtain the i-th sampling statistical data of the n+k-th state.
  • the i-th sampling sample data of the n-th state and the i-th sampling sample of the n+k-th state are obtained by sampling the verifier result of the nth state and the verifier result of the n+k state respectively data, and according to the i-th sampling sample data of the n-th state and the i-th sampling sample data of the n+k-th state, the i-th counting result can be obtained, which can reduce the total amount of data needed to count the number of failed bits each time. It is beneficial to shorten the time for counting the number of failed bits, increase the determination range of the programming state that needs to be verified in the i+1th programming verification operation, thereby increasing the programming speed, shortening the programming time, and improving memory performance.
  • this programming method comprises the following steps:
  • S300 Execute the i-th programming verification, so as to perform programming verification on memory cells whose target state is the n-th state to the n+k-th state (that is, verify (PVn, ..., PVn+k)); wherein, i and n are positive Integer, k is a natural number, and the n+kth state is less than or equal to the highest programming state of the memory;
  • S310 After executing the i-th program verification, apply the i+1-th programming pulse; during the process of applying the i+1-th programming pulse, according to the verifier result of the n-th state in the i-th verification result of the i-th program verification operation and For the verification sub-result of the n+k state, count the number of failed bits for the programming of the n-th state and the programming of the n+k-th state in the i-th programming operation, and obtain the i-th counting result;
  • the number of failed bits when performing program verification (i.e. PVn) on the nth state is less than the first preset value, and the number of successful bits when performing program verification (i.e. PVn+k) on the n+k state is less than or equal to the second
  • the preset value it can be determined that the range of programming states to be verified by the i+1th programming verification operation is from the n+1th state to the n+kth state, therefore, jump to execute S332;
  • the number of failed bits is greater than or equal to the first preset value, and the number of successful bits when performing program verification (i.e. PVn+k) on the n+k state is less than or equal to
  • the second preset value it can be determined that the range of programming states to be verified by the i+1th programming verification operation is the nth state to the n+kth state, therefore, jump to execute S342;
  • S331 Execute the i+1th programming verification, so as to perform programming verification on memory cells whose target state is the n+1th state to the n+k+1th state (that is, verifying (PVn+1, ..., PVn+k+1 )); wherein, the n+k+1th state is less than or equal to the highest programmed state of the memory;
  • S332 Execute the i+1th program verification, so as to perform program verification on memory cells whose target states are the n+1th state to the n+kth state (ie, verify (PVn+1, . . . , PVn+k));
  • S341 Execute the i+1th programming verification, so as to perform programming verification on memory cells whose target state is the nth state to the n+k+1th state (ie, verify (PVn, ..., PVn+k+1)); where , the n+k+1th state is less than or equal to the highest programming state of the memory;
  • S342 Execute the i+1th program verification, so as to perform program verification on memory cells whose target states are the nth state to the n+kth state (ie, verify (PVn, . . . , PVn+k));
  • the highest state verified must be less than or equal to the highest state that the memory can be programmed.
  • the highest state of the next programming verification determined according to S330 is greater than the highest state that the memory can be programmed, the highest state when performing the next programming verification is still the highest state that the memory can be programmed.
  • the highest state that can be programmed is L7, then when the highest state of the ith program verification operation is L7, and the number of successful bits of PV7 is greater than the second preset value, the highest state of the i+1th program verification operation The state is still L7.
  • the method includes the following steps:
  • Step 1 Execute the fourth programming verification operation (i.e. execute S300), the verification state range of the fourth programming verification operation is from the first state to the second state, and obtain the threshold voltage distribution curve as shown in (d) in FIG. 1;
  • Step 2 After performing the 4th programming verification, apply the 5th programming pulse, and, in the process of applying the 5th programming pulse, according to the verification result of the 4th programming verification operation, the verifier in the lowest state (that is, the first state) result and the verification sub-result of the highest state (that is, the second state), count the number of failed bits for the programming of the first state and the programming of the second state in the fourth programming operation, and obtain the fourth counting result (that is, the first execution S310);
  • step three can be performed: according to the fourth counting result, judge whether the number of failed bits when performing program verification on the first state in the fourth program verification operation is less than the first preset value (i.e. execute S320); As a result, it is judged whether the number of successful bits is greater than the second preset value when the program verification is performed in the second state (i.e., execute S330);
  • Step 4 When the fourth counting result indicates that in the fourth program verification operation, the number of failed bits when performing program verification on the first state is less than the first preset value, and the number of successful bits when performing program verification on the second state is greater than the first When the second preset value is selected, jump to step five (i.e. execute S331);
  • step 6 i.e. execute S332
  • step 7 i.e. execute S341
  • step 8 i.e. execute S342
  • Step 5 Perform the fifth programming verification operation, wherein the target state range to be verified by the fifth programming verification operation is the second state to the third state; then perform step nine;
  • Step 6 Perform the fifth program verification operation, wherein the target state to be verified in the fifth program verification operation is the second state; then perform step 9;
  • Step 7 Perform the fifth programming verification operation, wherein the target state range to be verified by the fifth programming verification operation is the first state to the third state; then perform step nine;
  • Step 8 Perform the fifth programming verification operation, wherein the target state range to be verified by the fifth programming verification operation is the first state to the second state; then perform step nine;
  • Step 9 Applying the sixth programming pulse; and, during the process of applying the sixth programming pulse, counting the number of failed bits for the lowest programming state verified in the fifth programming verification operation, and counting the highest number of failed bits verified in the fifth programming verification operation. In the programming state, the number of failed bits is counted, and the fifth counting result is obtained (that is, S350 is executed).
  • the above programming method can be executed cyclically until the programming is completed, or until the number of application of programming pulses reaches the maximum number, or until the number of times of program verification reaches the maximum value.
  • Fig. 5 is a schematic diagram of a memory 100 according to an exemplary embodiment.
  • the memory 100 includes:
  • a memory cell array 110 the memory cell array 110 includes a plurality of memory cell rows
  • a plurality of word lines 120 are respectively coupled to a plurality of memory cell rows;
  • Peripheral circuitry 130 coupled to the plurality of word lines 120 and configured to perform a program verify operation on a selected row of memory cells of the plurality of rows of memory cells, the selected row of memory cells being coupled to the selected word line, wherein, To perform program verify operations, peripheral circuitry 130 is configured to:
  • the programming state range of the i-th programming verification operation verification is from the nth state to the n+kth state, i and n are positive integers, k is a natural number, and the n+th The k state is less than or equal to the highest programmed state of the memory;
  • the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result determine the programming state range to be verified for the i+1 programming verification operation
  • the (i+1)th programming verification operation is performed according to the determined programming state range to be verified by the i+1th programming verification operation.
  • the memory cell array 110 may be an array of NAND flash memory cells, wherein the memory cell array 110 is provided in the form of an array of NAND memory strings 111 each extending vertically over a substrate (not shown).
  • each NAND memory string 111 includes a plurality of memory cells 112 coupled in series and stacked vertically.
  • Each memory cell 112 may hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the area of the memory cell 112 .
  • Each memory cell 112 may be a floating gate type memory cell including a floating gate transistor, or a charge trap type memory cell including a charge trap transistor.
  • each memory cell 112 is a single-level cell that has two possible memory states and thus can store one bit of data.
  • a first memory state "0" may correspond to a first voltage range
  • a second memory state "1" may correspond to a second voltage range.
  • each memory cell 112 is a cell capable of storing more than a single bit of data in more than four memory states. For example, two bits can be stored per cell (also known as a multi-level cell), three bits can be stored per cell (also known as a triple-level cell), or four bits can be stored per cell (also known as a quad-level cell) .
  • Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take three possible programming levels from the erased state by writing one of three possible nominal storage values to the cell one of the. A fourth nominal stored value may be used for the erased state.
  • each NAND memory string 111 may include a source select gate (SSG) 113 at its source terminal and a drain select gate (DSG) 114 at its drain terminal.
  • Source select gate 113 and drain select gate 114 may be configured to activate selected NAND memory strings 111 (columns of the array) during read and program operations.
  • the sources of the NAND memory strings 111 in the same block 115 are coupled by the same source line (SL) 116 (eg, a common SL).
  • SL source line
  • all NAND memory strings 111 in the same block 115 have an array common source (ACS).
  • the drain select gate 114 of each NAND memory string 111 is coupled to a corresponding bit line 117, from which data can be read or written via an output bus (not shown).
  • each NAND memory string 111 is configured by applying a select voltage (e.g., higher than the threshold voltage of a transistor having a drain select gate 114 ) or a deselect voltage ( For example, 0 V) is applied to the corresponding drain select gate 114 . And/or, in some embodiments, each NAND memory string 111 is configured to pass a select voltage (eg, higher than the threshold voltage of the transistor with source select gate 113 ) or A deselect voltage (eg, 0V) is applied to the corresponding source select gate 113 to be selected or deselected.
  • a select voltage e.g., higher than the threshold voltage of a transistor having a drain select gate 114
  • a deselect voltage For example, 0 V
  • each NAND memory string 111 is configured to pass a select voltage (eg, higher than the threshold voltage of the transistor with source select gate 113 ) or A deselect voltage (eg, 0V) is applied to the corresponding source select gate 113 to be selected or des
  • NAND memory string 111 may be organized into a plurality of blocks 115, each of which may have a common source line 116 (eg, coupled to ground).
  • each block 115 is the basic unit of data for an erase operation, i.e., all memory cells 112 on the same block 115 are erased simultaneously.
  • an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) coupled to the selected block and at the same location as the selected block may be biased.
  • Source lines of unselected blocks in the face may be biased.
  • erase operations may be performed at the half-block level, at the quarter-block level, or at any suitable number or fraction of blocks.
  • Memory cells 112 of adjacent NAND memory strings 111 may be coupled by word lines 120 that select which row of memory cells 112 is affected by read and program operations.
  • each word line 120 is coupled to a page 130 of memory cells 112, which is the basic unit of data for programming operations.
  • the size of a page 130 in bits may be related to the number of NAND memory strings 111 coupled by word lines 120 in a block 115 .
  • Each word line 120 may include a plurality of control gates (gate electrodes) at each memory cell 112 in a corresponding page 130 and a gate line coupling the control gates. It can be understood that a memory cell row is a plurality of memory cells 112 located in the same page 130 .
  • NAND memory string 111 may extend vertically above substrate 101 through memory stack layer 102 .
  • the substrate 101 may comprise silicon (eg, monocrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable Material.
  • the memory stack layer 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104 .
  • the number of gate conductive layer 103 and gate-to-gate dielectric layer 104 pairs in memory stack layer 102 may determine the number of memory cells 112 in memory cell array 110 .
  • the gate conductive layer 103 may include conductive materials including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.
  • each gate conductive layer 103 includes a metal layer, such as a tungsten layer.
  • each gate conductive layer 103 includes a doped polysilicon layer.
  • Each gate conductive layer 103 may include a control gate surrounding a memory cell 112 and may extend laterally at the top of the memory stack layer 102 as a DSG line 118 and at the bottom of the memory stack layer 102 as a SSG line 119 , or extend laterally between the DSG line 118 and the SSG line 119 as the word line 120 .
  • NAND memory string 111 includes a channel structure 105 extending vertically through memory stack layer 102 .
  • the channel structure 105 includes a semiconductor material(s) filled (eg, as the semiconductor channel 106 ) and a dielectric material(s) (eg, as the memory film 107 ). trench hole.
  • semiconductor channel 106 includes silicon, eg, polysilicon.
  • memory film 107 is a composite dielectric layer including tunneling layer 108 , storage layer 109 (also referred to as “charge trapping/storage layer”), and blocking layer 1010 .
  • the channel structure 105 may have a cylindrical shape (eg, a pillar shape).
  • the semiconductor channel 106 , the tunneling layer 108 , the storage layer 109 and the barrier layer 1010 are radially arranged in this order from the center of the cylinder towards the outer surface of the cylinder.
  • the tunneling layer 108 may include silicon oxide, silicon oxynitride, or any combination thereof.
  • the storage layer 109 may include silicon nitride, silicon oxynitride, or any combination thereof.
  • Barrier layer 1010 may include silicon oxide, silicon oxynitride, a high-k (high-k) dielectric, or any combination thereof.
  • the memory film 107 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).
  • a well 414 (eg, a P-well and/or an N-well) is formed in the substrate 101 , and a source terminal of the NAND memory string 111 is in contact with the well 414 .
  • source line 116 may be coupled to well 414 to apply an erase voltage to well 414 (ie, the source of NAND memory string 111 ) during an erase operation.
  • the NAND memory string 111 also includes a channel plug 416 at the drain terminal of the NAND memory string 111 . It should be understood that although not shown in FIG. 6 , additional components of the memory cell array 110 may be formed, including but not limited to gate line gaps/source contacts, local contacts, interconnect layers, and the like.
  • the peripheral circuit 130 may be coupled to the memory cell array 110 through the bit line 117 , the word line 120 , the source line 116 , the SSG line 119 and the DSG line 118 .
  • Peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and/or current signals via bit lines 117, word lines 120, source lines 116, SSG lines 119, and DSG lines 118. Sensing voltage signals and/or current signals to and from each target memory cell 112 facilitates operation of the memory cell array 110 .
  • the peripheral circuit 130 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.
  • FIG. 7 shows some exemplary peripheral circuits 130 including page buffer/sense amplifier 504, column decoder/bit line (BL) driver 506, row decoder/word line (WL) driver 508 , voltage generator 510 , control logic unit 512 , register 514 , interface 516 and data bus 518 . It should be understood that in some examples, additional peripheral circuitry not shown in FIG. 7 may also be included.
  • the page buffer/sense amplifier 504 may be configured to read data from and program (write) data to the memory cell array 110 according to control signals from the control logic unit 512 .
  • the page buffer/sense amplifier 504 may store a page of programming data (write data) to be programmed into one page 130 of the memory cell array 110 .
  • the page buffer/sense amplifier 504 may perform a program verify operation to ensure that data has been correctly programmed into the memory cells 112 coupled to the selected word line 120 .
  • page buffer/sense amplifier 504 may also sense a low power signal from bit line 117 representing a data bit stored in memory cell 112 and amplify the small voltage swing during a read operation to a recognizable logic level.
  • Column decoder/bit line driver 506 may be configured to be controlled by control logic unit 512 and to select one or more NAND memory strings 111 by applying bit line voltages generated from voltage generator 510 .
  • Row decoder/word line driver 508 may be configured to be controlled by control logic unit 512 and select/deselect blocks 115 of memory cell array 110 and select/deselect word lines 120 of blocks 115 . Row decoder/wordline driver 508 may also be configured to drive wordline 120 using a wordline voltage (V WL ) generated from voltage generator 510 . In some implementations, the row decoder/wordline driver 508 can also select/deselect and drive the SSG line 119 and the DSG line 118 . As described in detail below, the row decoder/wordline driver 508 is configured to perform erase operations on the memory cells 112 coupled to the selected wordline(s) 120 .
  • V WL wordline voltage
  • the voltage generator 510 may be configured to be controlled by the control logic unit 512, and generate word line voltages (eg, read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.) to be supplied to the memory cell array 110, bit line voltage and source line voltage.
  • word line voltages eg, read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.
  • Control logic unit 512 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits.
  • Registers 514 may be coupled to control logic unit 512 and include status registers, command registers and address registers for storing status information, command operation codes (OP codes) and command addresses for controlling the operation of each peripheral circuit.
  • Interface 516 may be coupled to control logic unit 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic unit 512 and to buffer status received from control logic unit 512 information and relay it to the host.
  • Interface 516 may also be coupled to column decoder/bit line driver 506 via data bus 518 and act as a data I/O interface and data buffer to buffer and relay data to and from memory cell array 110 continue or buffer data.
  • peripheral circuit 130 is configured to perform the program verification operation provided by the embodiments of the present disclosure on a selected memory cell row among the plurality of memory cell rows.
  • Fig. 8 is a schematic diagram of a memory 200 according to an exemplary embodiment.
  • the memory 200 includes:
  • a memory cell array 110 the memory cell array 110 includes a plurality of memory cell rows
  • Peripheral circuitry 230 coupled to the plurality of word lines 120 and configured to perform a programming operation on a selected row of memory cells of the plurality of rows of memory cells, the selected row of memory cells being coupled to the selected word line, wherein, for To perform a programming operation, the peripheral circuit 230 is configured to:
  • the n-th state programming and n+k state programming to count the number of failed bits to obtain the ith counting result;
  • the programming state range of the i programming verification operation verification is from the nth state to the n+k state, and i and n are A positive integer, k is a natural number, and the n+kth state is less than or equal to the highest programming state of the memory;
  • the (i+1)th programming verification operation is performed according to the determined programming state range to be verified by the i+1th programming verification operation.
  • peripheral circuit 230 is configured to perform the programming operation provided by the embodiments of the present disclosure on a selected row of memory cells among the plurality of rows of memory cells.
  • the structure of the peripheral circuit 230 may be the same as that of the peripheral circuit 130 .
  • Fig. 9a is a schematic diagram of a memory system 300 according to an exemplary embodiment
  • Fig. 9b is a schematic diagram of another memory system 300 according to an exemplary embodiment. 9a and 9b, the memory system 300 includes:
  • a memory controller 321 coupled to the memory 100 or the memory 200 and configured to control the memory 100 or the memory 200 .
  • System 300 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, pointing device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device or any other suitable electronic device having memory therein.
  • VR virtual reality
  • AR augmented reality
  • the system 300 may include a host 310 and a storage subsystem 320 having one or more memories 100 or 200 , and the storage subsystem further includes a memory controller 321 .
  • the host 310 may be a processor (eg, a central processing unit (CPU)) or a system on chip (SoC) (eg, an application processor (AP)) of an electronic device.
  • SoC system on chip
  • the host 310 may be configured to send data to the memory 100 or the memory 200 .
  • the host 310 may be configured to receive data from the memory 100 or the memory 200 .
  • the memory 100 or the memory 200 may be any memory device disclosed in this disclosure.
  • Memory 100 or memory 200 e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)
  • drive transistors e.g., string drivers
  • memory controller 321 is also coupled to host 310 .
  • the memory controller 321 may manage data stored in the memory 100 or the memory 200 and communicate with the host 310 .
  • memory controller 321 is designed to operate in low duty cycle environments such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.
  • SD Secure Digital
  • CF Compact Flash
  • USB Universal Serial Bus
  • the memory controller 321 is designed for operation in high duty cycle environments solid-state drives (SSDs) or embedded multimedia cards (eMMCs) used as devices such as smartphones, tablets, laptops, etc. Data storage for mobile devices such as desktop computers and enterprise storage arrays.
  • SSDs solid-state drives
  • eMMCs embedded multimedia cards
  • the memory controller 321 may be configured to control operations of the memory 100 or the memory 200, such as read, erase, and program operations. Memory controller 321 may also be configured to manage various functions regarding data stored or to be stored in memory 100 or memory 200, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. . In some embodiments, memory controller 321 is also configured to process error correction code (ECC) on data read from or written to memory 100 or 200 .
  • ECC error correction code
  • Memory controller 321 may also perform any other suitable functions, such as formatting memory 100 or memory 200 .
  • the memory controller 321 may communicate with external devices (eg, the host 310) according to a specific communication protocol.
  • the memory controller 321 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.
  • various interface protocols such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol,
  • the memory controller 321 and one or more memories 100 or 200 may be integrated into various types of storage devices, for example, included in the same package (eg, Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 100 can be implemented and packaged into different types of terminal electronic products.
  • UFS Universal Flash Storage
  • eMMC embedded MultiMediaCard
  • the memory controller 321 and a single memory 100 may be integrated into a memory card 400 .
  • the memory card 400 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc.
  • the memory card 400 may also include a memory card connector 410 that couples the memory card 400 with a host (eg, host 310 in FIG. 9a ).
  • the memory controller 321 and the plurality of memories 100 may be integrated into a solid state drive (SSD) 500.
  • the solid state drive 500 may also include a solid state drive connector 510 that couples the solid state drive 500 to a host (eg, host 310 in FIG. 9a ).
  • a host eg, host 310 in FIG. 9a
  • the storage capacity and/or operating speed of the solid state drive 500 is greater than the storage capacity and/or operating speed of the memory card 400 .
  • the memory controller 321 may execute the program verification method or programming method provided in any embodiment of the present disclosure.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may be used as a single unit, or two or more units may be integrated into one unit; the above-mentioned integration
  • the unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

Abstract

一种存储器、存储器的编程方法及编程验证方法、存储器系统，所述编程验证方法包括：获取第i编程验证操作的第i验证结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态（S100）；根据所述第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的编程态范围（S110）；根据确定的所述第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作（S120）。

Description

存储器、存储器的编程方法及编程验证方法、存储器系统 技术领域
本公开实施例涉及但不限于半导体领域，尤其涉及一种存储器、存储器的编程方法及编程验证方法、存储器系统。
背景技术
快闪存储器作为例如移动电话、数字相机等便携式电子设备的存储媒介而被广泛使用。快闪存储器通常使用允许高存储器密度、高可靠性和低功耗的单晶体管存储器单元。通过对电荷存储结构(例如，浮栅或电荷阱)或其它物理现象(例如，相变或铁电)进行编程，存储器单元的阈值电压的改变决定每个存储器单元的数据状态(例如，数据值)。
相关技术中，对存储器施加编程脉冲以进行编程后，需要进行编程验证操作，施加编程脉冲的次数以及进行编程验证操作的次数，是决定编程时间的重要因素。因此，如何在保证编程质量的前提下，缩短编程时间，成为亟待解决的问题。
发明内容
本公开实施例提供一种存储器、存储器的编程方法及编程验证方法、存储器系统。
根据本公开实施例的第一方面，提供一种存储器的编程验证方法，包括：
获取第i编程验证操作的第i验证结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
根据所述第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的编程态范围；
根据确定的所述第i+1编程验证操作需要验证的编程态范围，执行第i+1 编程验证操作。
在一些实施例中，所述根据所述第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的的编程态范围，包括：
根据所述第i验证结果中第n态的验证子结果，确定所述第i+1编程验证操作需要验证的最低编程态；
根据所述第i验证结果中第n+k态的验证子结果，确定所述第i+1编程验证操作需要验证的最高编程态。
在一些实施例中，所述第i验证结果中第n态的验证子结果包括：第n态的第i统计数据，用于统计对第n态进行编程的失败比特数；
所述根据所述第i验证结果中第n态的验证子结果，确定所述第i+1编程验证操作需要验证的最低编程态，包括：
根据所述第n态的第i统计数据，确定对所述第n态进行编程的失败比特数；
当对所述第n态进行编程的失败比特数小于第一预设值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n+1态；
当对所述第n态进行编程的失败比特数大于或等于所述第一预设值时，确定所述第i+1编程验证操作需要验证的的最低编程态为第n态；
或者，
当对所述第n态进行编程的失败比特数与目标态为所述第n态的比特数的比值小于第一预设比值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n+1态；
当对所述第n态进行编程的失败比特数与目标态为所述第n态的比特数的比值大于或等于所述第一预设比值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n态。
在一些实施例中，所述方法还包括：
获取待编程存储单元的循环次数；
根据所述循环次数，确定所述第一预设值的取值范围或所述第一预设比值的取值范围。
在一些实施例中，所述第一预设值的取值范围是在对所述存储器进行的误差校正码纠错机制所允许范围内。
在一些实施例中，所述第i验证结果中第n+k态的验证子结果包括：第n+k态的第i统计数据，用于统计对第n+k态进行编程的成功比特数；
所述根据所述第i验证结果中第n+k态的验证子结果，确定所述第i+1编程验证操作需要验证的最高编程态，包括：
根据所述第n+k态的第i统计数据，确定对所述第n+k态进行编程的成功比特数；
当对所述第n+k态进行编程的成功比特数大于第二预设值，且所述第n+k态小于所述所述存储器的最高编程态时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
当对所述第n+k态进行编程的成功比特数小于或等于所述第二预设值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k态；
或者，
当对所述第n+k态进行编程的成功比特数与目标态为所述第n+k态的比特数的比值大于第二预设比值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
当对所述第n+k态进行编程的成功比特数与目标态为所述第n+k态的比特数的比值小于或等于所述第二预设比值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k态。
在一些实施例中，所述方法还包括：
获取增量步长脉冲编程的步长和/或编程电压斜率；根据所述步长和/或所述编程电压斜率，确定所述第二预设值或所述第二预设比值的取值范围；其中，所述编程验证方法应用于增量步长脉冲编程方法中；
或者，
获取待编程存储单元的循环次数；根据所述循环次数，确定所述第二预设值的取值范围或所述第二预设比值的取值范围。
在一些实施例中，所述第二预设比值的取值范围为2％至3％。
在一些实施例中，所述根据所述第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的编程态范围，包括：
对所述第i验证结果中的第n态的验证子结果以及第n+k态的验证子结果分别进行抽样，获得第n态的第i抽样统计数据和第n+k态的第i抽样统计数据；
根据所述第n态的第i抽样统计数据，确定所述第i+1编程验证操作需要验证的最低编程态；
根据所述第n+k态的第i抽样统计数据，确定所述第i+1编程验证操作需要验证的最高编程态。
根据本公开实施例的第二方面，提供一种存储器的编程方法，包括：
对所述存储器的待编程存储单元施加第i+1编程脉冲；
在施加所述第i+1编程脉冲的过程中，根据第i编程验证操作的第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，对第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得第i计数结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
根据所述第i计数结果，确定第i+1编程验证操作需要验证的编程态范围；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
根据确定的所述第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
在一些实施例中，所述第i计数结果包括：所述第i编程操作中对所述第n态进行编程的失败比特数；
所述根据所述第i计数结果，确定第i+1编程验证操作需要验证的编程态范围，包括：
当对所述第n态进行编程的失败比特数小于第一预设值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n+1态；
当对所述第n态进行编程的失败比特数大于或等于所述第一预设值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n态；
或者，
当对所述第n态进行编程的失败比特数与目标态为所述第n态的比特数的比值小于第一预设比值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n+1态；
当对所述第n态进行编程的失败比特数与目标态为所述第n态的比特数的比值大于或等于所述第一预设比值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n态。
在一些实施例中，所述第i计数结果包括：所述第i编程操作中对所述第n+k态进行编程的失败比特数；
所述根据所述第i计数结果，确定第i+1编程验证操作需要验证的编程态范围，包括：
当对所述第n+k态进行编程的成功比特数大于第二预设值，且所述第n+k态小于所述存储器的最高编程态时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
当对所述第n+k态进行编程的成功比特数小于或等于所述第二预设值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k态；
或者，
当对所述第n+k态进行编程的成功比特数与目标态为所述第n+k态的比特数的比值大于第二预设比值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
当对所述第n+k态进行编程的成功比特数与目标态为所述第n+k态的比特 数的比值小于或等于所述第二预设比值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k态。
在一些实施例中，所述根据第i编程验证操作的第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，对第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得第i计数结果，包括：
对所述第i验证结果中的第n态的验证子结果以及第n+k态的验证子结果分别进行抽样，获得所述第n态的第i抽样样本数据和第n+k态的第i抽样样本数据；
根据所述第n态的第i抽样样本数据和第n+k态的第i抽样样本数据，对所述第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得所述第i计数结果。
根据本公开实施例的第三方面，提供一种存储器，包括：
存储器单元阵列，所述存储器单元阵列包括多个存储器单元行；
多个字线，所述多个字线分别耦合到所述多个存储器单元行；以及
外围电路，所述外围电路耦合到所述多个字线并且被配置为对所述多个存储器单元行中的选定存储器单元行执行编程验证操作，所述选定存储器单元行耦合到选定字线，其中，为了执行所述编程验证操作，所述外围电路被配置为：
获取第i编程验证操作的第i验证结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
根据所述第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的编程态范围；
根据确定的所述第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
根据本公开实施例的第四方面，提供一种存储器，包括：
存储器单元阵列，所述存储器单元阵列包括多个存储器单元行；
多个字线，所述多个字线分别耦合到所述多个存储器单元行；以及
外围电路，所述外围电路耦合到所述多个字线并且被配置为对所述多个存储器单元行中的选定存储器单元行执行编程操作，所述选定存储器单元行耦合到选定字线，其中，为了执行所述编程操作，所述外围电路被配置为：
对所述存储器的待编程存储单元施加第i+1编程脉冲；
在施加所述第i+1编程脉冲的过程中，根据第i编程验证操作的第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，对第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得第i计数结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
根据所述第i计数结果，确定第i+1编程验证操作需要验证的编程态范围；
根据确定的所述第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
根据本公开实施例的第五方面，提供一种存储器系统，包括：
一个或多个如本公开实施例第三方面或本公开实施例第四方面所述的存储器；
耦合到所述存储器并且被配置为控制所述存储器的存储器控制器。
相关技术中，通常会根据经验值，对每个待验证的编程态确定一个固定的起始时刻(start loop)，例如，在施加第3编程脉冲(即施加第3个编程脉冲)之后开始对第2态执行编程验证(PV2)，那么第2态的验证起始循环即为3，如此，每次编程验证操作需要在验证的编程态范围就是固定的。然而，当编程速度变化时，这种根据经验值确定的固定的起始时刻，可能不是最适合的验证起始时刻。具体地，当设定的验证起始时刻早于最适合的验证起始时刻，过早开始该编程验证会延长编程验证操作的时间，进而延长编程时长。当设定的验证起始时刻晚于最适合的验证起始时刻，可能会出现过编程(over-program)现象，进而降低编程质量。
相较于每个编程验证操作有固定的需要验证的编程态范围，本公开实施例中，根据第i编程验证操作的验证结果，确定施加下一个编程脉冲之后执行的 第i+1编程验证操作的需要验证的编程态范围，即根据上一次编程验证操作的结果确定下一次编程验证操作需要验证的编程态范围，可以动态确定每个待验证的编程态的起始时刻，不仅方法简单，而且可以提高确定的每个待验证的编程态的起始时刻的准确性，一方面，可以减少因为编程验证起始时刻设定的过早导致编程时长增加，有利于缩短编程时长；另一方面，可以减少因为编程验证起始时刻设定的过晚导致的过编程，有利于保证编程质量较好。
此外，相较于对同一个编程态，以不同的单位(例如块或者字线)进行编程时都需要人为分别设置不同的固定起始时刻，本公开实施例无需人为设置固定起始时刻，并且可通过验证结果追踪存储器编程性能的差异，进而自动确定每一次编程验证操作需要验证的编程态范围，方式简单，且能够及时根据存储器性能调整编程验证操作的需要验证的编程态范围，有利于提高编程质量。
附图说明
图1是根据一示例性实施例示出的一种编程操作的阈值电压分布图；
图2是根据一示例性实施例示出的一种编程验证方法的流程图；
图3是根据一示例性实施例示出的一种编程方法的流程图；
图4是根据一示例性实施例示出的一种编程方法的局部流程图；
图5是根据一示例性实施例示出的一种存储器的示意图；
图6是根据一示例性实施例示出的一种包括NAND存储器串的存储器单元阵列的局部截面图；
图7是根据一示例性实施例示出的包括存储器单元阵列和外围电路的存储器的块图；
图8是根据一示例性实施例示出的另一种存储器的示意图；
图9a是根据一示例性实施例示出的一种存储器系统的块图；
图9b是根据一示例性实施例示出的另一种存储器系统的块图；
图10a是根据一示例性实施例示出的一种存储器卡的示意图；
图10b是根据一示例性实施例示出的一种固态驱动器(SSD)的示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
可以理解的是，本公开中的“在……上”、“在……之上”和“在……上方”的含义应当以最宽方式被解读，以使得“在……上”不仅表示其“在”某物“上”且其间没有居间特征或层(即直接在某物上)的含义，而且还包括在某物“上”且其间有居间特征或层的含义。
在本公开实施例中，术语“A与B相连”包含A、B两者相互接触地A与B相连的情形，或者A、B两者之间还间插有其他部件而A非接触地与B相连的情形。
在本公开实施例中，术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。可以理解地，“第一”、“第二”等在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
在本公开实施例中，术语“层”是指包括具有厚度的区域的材料部分。层可以在下方或上方结构的整体之上延伸，或者可以具有小于下方或上方结构范围的范围。此外，层可以是厚度小于连续结构厚度的均质或非均质连续结构的区域。例如，层可位于连续结构的顶表面和底表面之间，或者层可在连续结构顶表面和底表面处的任何水平面对之间。层可以水平、垂直和/或沿倾斜表面延 伸。层可以包括多个子层。例如，互连层可包括一个或多个导体和接触子层(其中形成互连线和/或过孔触点)、以及一个或多个电介质子层。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
需要说明的是，本公开实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
NAND存储器，属于非易失性存储设备(Non-volatile Memory Device)，其内部采用非线性宏单元模式，具有容量大，改写速度快等优点，适用于大量数据的存储。NAND存储器广泛应用于嵌入式产品中，如数码相机、MP3随身听记忆卡、体积小巧的U盘等。
在NAND存储器的发展中，早期NAND存储器颗粒的存储单元多为单级单元(Single-Level Cell，SLC)，即一个存储单元存储1比特(bit)数据，此时每个存储单元存在两种状态，具体为0和1。
随着NAND存储器的发展，NAND存储器颗粒的存储单元从单级单元逐渐演变为多级单元(Multi-Level Cell，MLC)，即一个存储单元存储2比特数据，接着推出了三级单元(Triple-Level Cell，TLC)，即一个存储单元存储3比特数据，甚至四级单元(Quad-Level Cell，QLC)，即一个存储单元存储4比特数据，相对应的，NAND存储器颗粒存储单元的状态也由2个变为4个、8个甚至16个。
NAND存储器的操作包括三部分：擦除操作、编程(写操作)以及读操作，可以以块(Block)为单位进行擦除操作，以页(Page)为单位进行编程和读操作。对于NAND存储器的编程操作，其过程例如又分为加压编程(即施加编程脉冲)、编程验证(Program Verify，PV)以及扫描验证结果三步操作。
对于NAND存储器而言，编程时长(t PROG)是衡量NAND存储器性能的重要指标。因此，研发人员一直致力于研究如何能够在保证编程质量(例如，保证读预算窗口，Read Budget Window)的前提下，提高编程速度，缩短编程时长。由于施加的编程脉冲的持续时间不能改变，因此，施加编程脉冲的个数、 进行编程验证的次数、每次进行编程验证的时间、以及进行扫描验证结果的时间，都是决定编程时长的重要因素。
以TLC存储单元为例，TLC存储单元具有1个擦除态和7个编程态，其编程态从第1态至第7态依次记为L1、L2、L3、L4、L5、L6和L7。对于TLC传统的编程方法是：在施加相邻两次编程脉冲之间启动对于每个态的编程验证操作。该方法存在的问题是：在施加第一个编程脉冲之后，实际上只有极少部分存储单元达到了L1态，而没有存储单元达到L2、L3、L4、L5、L6和L7态，如果此时就启动L2至L7至少任一态的编程验证操作，就会增加需要进行编程验证操作的次数以及编程验证操作的时间，甚至可能导致编程验证操作和扫描验证结果所用的时间会占据整个编程过程的至少一半以上，严重降低编程速度。
为了提高编程速度，表1示出改进后的相关编程验证方法中，每个编程验证态对应的起始时刻。
编程验证(PV) 起始时刻(start loop)
PV1 1
PV2 3
PV3 4
PV4 5
PV5 7
PV6 9
PV7 11
表1 不同编程态的编程验证操作与起始时刻表
其中，PV1表示对第1态(L1)进行编程验证操作，PV2表示对第2态(L2)进行编程验证操作，PV3表示对第3态(L3)进行编程验证操作，PV4表示对第4态(L4)进行编程验证操作，PV5表示对第5态(L5)进行编程验证操作，PV6表示对第6态(L6)进行编程验证操作，PV7表示对第7态(L7)进行编程验证操作。
编程验证操作的起始时刻，可以通过该编程验证操作是在施加第几个编程 脉冲之后开始的来定义，例如，第1态的编程验证操作的起始时刻为1，代表在施加第1个编程脉冲之后，且在施加第2个编程脉冲之前，开始对第1态进行编程验证。
在进行编程操作时，所有待编程的存储单元都是从擦除态开始进行编程的。通常，需要在施加数次编程脉冲之后，进行编程的存储单元的阈值电压才能够达到较高的编程态。因此，相关技术中，可以通过减少编程验证的次数提高编程速度。
具体地，在相关技术中，改进后的编程方法在早期施加的编程脉冲之后，可以不用进行较高编程态的编程验证操作。参照表1所示，该编程验证方法使用固定的起始时刻来控制何时启动每个编程态的编程验证。例如，对第3态进行编程验证操作的起始时刻设为4，也就是说，在施加了前3个编程脉冲之后，不用验证第3态，而是从施加第4个编程脉冲之后，开始进行第3态的编程验证操作(即PV3)。
相较于每次施加编程脉冲之后都对每个态进行编程验证，改进后的上述方法虽然在一定程度上减少了编程验证的次数，然而，考虑到同时进行编程的单位不同时会存在编程特性的差异，对每个态而言，对所有的裸片(die)、块(block)或者字线(Word Line，WL)都设置同样的起始时刻依旧会存在误差。因此，为了保证编程质量，在进行每个编程态的编程验证操作起始时刻设定时，需要留出足够的裕度(margin)，并在进行编程的单位不同时，需要根据经验值对每个单位分别设置对应的固定编程验证操作起始时刻，这种方式会需要消耗大量的电路资源，并且会增长测试时间。
另外，NAND的编程特性还受到许多其他因素的影响。例如，随着循环次数(cycling)或者温度等条件的变化，每个存储单元的性能会发生变化，导致NAND的编程性能不同。通过对每个编程验证操作均设置固定的起始时刻，就不能追踪到这些编程特性的变化，因此，固定的起始时刻并不是最适合的起始时刻。当编程验证操作设定的固定起始时刻早于最适合的起始时刻，过早开始该编程验证会延长验证操作的时间，进而延长编程时长。当编程验证操作设定 的固定起始时刻晚于最适合的起始时刻，可能会出现过编程进而降低编程质量。
以TLC为例，图1是根据一示例性实施例示出了一种存储器进行编程操作的阈值电压分布图。需要说明的是，TLC具有7种编程态，图1中仅示出了对5种编程态(即L1至L5)进行编程作为示例。
参照图1所示，图1示出了8个子曲线图，依次为图(a)、图(b)、图(c)、图(d)、图(e)、图(f)、图(g)和图(h)，每个子曲线图中均包括5条曲线，每条曲线均代表在施加编程脉冲之后，目标编程态相同的存储单元的分布情况。其中，V th1、V th2、V th3、V th4、V th5、V th6以及V th7依次分别代表：第1态的起始阈值电压、第2态的起始阈值电压、第3态的起始阈值电压、第4态的起始阈值电压、第5态的起始阈值电压、第6态的起始阈值电压以及第7态的起始阈值电压。具体地：
图(a)示出了从擦除态开始，施加第1个编程脉冲之后，对存储单元进行第1编程验证操作获得的阈值电压分布曲线。第1编程验证操作包括对第1态进行的编程验证(PV1)，即第1编程验证操作验证的编程态范围为L1。
图(b)示出了在图(a)的基础上，施加下一个编程脉冲之后，对存储单元进行第2编程验证操作获得的阈值电压分布曲线，即图(b)示出了从擦除态开始，施加第2个编程脉冲之后，对存储单元进行第2编程验证操作获得的阈值电压分布曲线。第2编程验证操作包括对第1态进行的编程验证(PV1)，即第2编程验证操作验证的编程态范围为L1。
可以理解的是，如果执行PV2的起始时刻设定为2，结合图1中(b)示出的曲线可知，在施加第2个编程脉冲之后，存储单元的阈值电压均小于第2态的阈值电压，因此，在施加第2个编程脉冲之后无需对第2态进行编程验证。
即，相较于把对第2态进行编程验证操作的起始时刻设为3(如图1中(c)所示)，把对第2态进行编程验证的起始时刻设为2的方案会增加编程验证的时间，进而增长编程时间。也就是说，当编程验证操作设定的固定起始时刻早于最适合的起始时刻，过早开始该编程验证会延长验证操作的时间，进而延长编程时长。
图(c)示出了在图(b)的基础上，施加下一个编程脉冲之后，对存储单元进行第3编程验证操作获得的阈值电压分布曲线，即图(c)示出了从擦除态开始，施加第3个编程脉冲之后，对存储单元进行第3编程验证操作获得的阈值电压分布曲线。需要强调的是，第3编程验证操作包括对第1态进行的编程验证(PV1)以及对第2态进行的编程验证(PV2)，第3编程验证操作验证的编程态范围为L1至L2。
图(d)示出了在图(c)的基础上，施加下一个编程脉冲之后，对存储单元进行第4编程验证操作获得的阈值电压分布曲线，即图(d)示出了从擦除态开始，施加第4个编程脉冲之后，对存储单元进行第4编程验证操作获得的阈值电压分布曲线。第4编程验证操作包括对第1态进行的编程验证(PV1)以及对第2态进行的编程验证(PV2)，第4编程验证操作验证的编程态范围为L1至L2。
图(e)示出了在图(d)的基础上，施加下一个编程脉冲之后，对存储单元进行第5编程验证操作获得的阈值电压分布曲线，即图(e)示出了从擦除态开始，施加第5个编程脉冲之后，对存储单元进行第5编程验证操作获得的阈值电压分布曲线。第5编程验证操作包括对第1态进行的编程验证(PV1)、对第2态进行的编程验证(PV2)以及对第3态进行的编程验证(PV3)，第5编程验证操作验证的编程态范围为L1至L3。
可以理解的是，如果执行PV2的起始时刻设定为5，结合图1中(e)示出的曲线可知，在施加第5个编程脉冲之后，部分存储单元的阈值电压已经大于了第3态的阈值电压，即出现了过编程。因此，在施加第5个编程脉冲之后才开始对第2态进行编程验证，会存在过编程。
即，相较于把对第2态进行编程验证操作的起始时刻设为3(如图1中(c)所示)，把对第2态进行编程验证的起始时刻设为5的方案会出现过编程现象，降低编程质量。也就是说，当编程验证操作设定的固定起始时刻晚于最适合的起始时刻，可能会出现过编程进而降低编程质量。
图(f)示出了在图(e)的基础上，施加下一个编程脉冲之后，对存储单 元进行第6编程验证操作获得的阈值电压分布曲线，即图(e)示出了从擦除态开始，施加第6个编程脉冲之后，对存储单元进行第6编程验证操作获得的阈值电压分布曲线。第6编程验证操作包括对第1态进行的编程验证(PV1)、对第2态进行的编程验证(PV2)以及对第3态进行的编程验证(PV3)，第6编程验证操作验证的编程态范围为L1至L3。
图(g)示出了在图(f)的基础上，施加下一个编程脉冲之后，对存储单元进行第7编程验证操作获得的阈值电压分布曲线，即图(g)示出了从擦除态开始，施加第7个编程脉冲之后，对存储单元进行第7编程验证操作获得的阈值电压分布曲线。第7编程验证操作包括对第2态进行的编程验证(PV2)、对第3态进行的编程验证(PV3)以及对第4态进行的编程验证(PV4)，第7编程验证操作验证的编程态范围为L2至L4。
图(h)示出了在图(g)的基础上，施加下一个编程脉冲之后，对存储单元进行第8编程验证操作获得的阈值电压分布曲线，即图(h)示出了从擦除态开始，施加第8个编程脉冲之后，对存储单元进行第8编程验证操作获得的阈值电压分布曲线。第8编程验证操作包括对第2态进行的编程验证(PV2)、对第3态进行的编程验证(PV3)以及对第4态进行的编程验证(PV4)，第8编程验证操作验证的编程态范围为L2至L4。以此类推，直至完成编程。
从图1可以看出，在施加编程脉冲之后，不同编程态的存储单元的阈值电压会同时移动。当一个存储单元的阈值电压达到它的目标阈值电压时，可以对这个存储单元施加编程禁止条件，以使在施加下一个编程脉冲时，达到目标阈值电压的存储单元的阈值电压就不会再发生移动。可以理解的是，在施加下一个编程脉冲的过程中，未达到目标阈值电压的存储单元的阈值电压会增大，阈值电压分布曲线会向更高的阈值电压方向进行移动。
示例性地，可以根据对较低编程态进行编程验证所获得的信息，预测较高编程态的阈值电压范围。
具体地：结合图1中(c)、(d)以及(e)所示，对于图1中(c)，进行编程验证的最高编程态为第2态，那么，根据对第2态进行编程验证操作(PV2) 获得的验证结果，就可以预测在施加下一个编程脉冲之后，有多少目标编程态是第3态的存储单元能够达到其目标态。
例如，如果目标态为第2态的存储单元中，只有极少数量存储单元、甚至没有存储单元达到了第2态，那么可以预测在施加下一个编程脉冲之后，没有目标编程态是第3态的存储单元能够达到第3态，即第3态不会编程成功，因此，在施加下一个编程脉冲之后就无须开始对第3态进行编程验证操作，如此，可以减少下一次编程验证操作需要验证的编程态数量，有利于缩短编程验证时间，并减少待处理的验证结果数量，提高编程效率。
又如，如果目标态为第2态的存储单元中，有较多存储单元达到了第2态，那么可以预测在施加下一个编程脉冲之后，会存在目标编程态是第3态的存储单元能够达到第3态，因此，在施加下一个编程脉冲之后就需要开始对第3态进行编程验证操作，如此，可以减少出现过编程的情况，提高编程质量。
有鉴于此，本公开提供一实施例的存储器的编程验证方法，参照图2所示，该编程验证方法包括以下步骤：
S100：获取第i编程验证操作的第i验证结果；其中，第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于存储器的最高编程态；
S110：根据第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的编程态范围；
S120：根据确定的第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
示例性地，存储器可包括多个存储单元组成的存储阵列，存储单元可包括单级单元(SLC)、多级单元(MLC)、三级单元(TLC)、四级单元(QLC)或者级数更多的单元等。
S100中，第i编程验证操作可理解为，从擦除态开始，在施加第i个编程脉冲之后、且在施加第i+1个编程脉冲之前，对待编程的存储单元进行的编程验证操作。
第i编程验证操作验证的编程态范围为第n态至第n+k态，即第i编程验证操作验证的最低态为第n态，最高态为第n+k态，且第i编程验证操作需要验证第n态与第n+k态之间的态。
第i验证结果，用于表示在施加i个编程脉冲之后，对待编程的存储单元的编程结果。第i验证结果可包括以下至少之一：指示验证的每个存储单元是否编程通过的第一类指示信息；指示验证的每个存储单元是否编程失败的第二类指示信息；指示达到目标编程态的存储单元个数的第三类指示信息。
S110中，第n态的验证子结果，用于表示在第i编程验证操作过程中，对于目标编程态为第n态的存储单元进行编程验证获得的结果。第n态的验证子结果可包括以下至少之一：指示目标编程态为第n态的每个存储单元是否编程通过的第一类指示信息；指示目标编程态为第n态的每个存储单元是否编程失败的第二类指示信息；指示达到第n态这一目标编程态的存储单元个数的第三类指示信息。
类似地，第n+k态的验证子结果，用于表示在第i编程验证操作过程中，对于目标编程态为第n+k态的存储单元进行编程验证获得的结果。第n+k态的验证子结果可包括以下至少之一：指示目标编程态为第n+k态的每个存储单元是否编程通过的第一类指示信息；指示目标编程态为第n+k态的每个存储单元是否编程失败的第二类指示信息；指示达到第n+k态这一目标编程态的存储单元个数的第三类指示信息。
需要强调的是，k的取值可等于0。当k等于0时，n的取值等于n+k的取值，即第i编程验证操作仅对第n态进行编程验证。
以TLC为例，存储器的最高编程态为第7态，因此，n+k的取值小于或等于7。以QLC为例，存储器的最高编程态为第15态，因此，n+k的取值小于或等于15。
在对不同的编程态进行编程验证时，起始验证电平不同。S110中，确定第i+1编程验证操作需要验证的编程态范围，可包括确定第i+1编程验证操作的验证电平范围。
在一些实施例中，S110包括：
根据第i验证结果中第n态的验证子结果，确定第i+1编程验证操作需要验证的最低编程态；
根据第i验证结果中第n+k态的验证子结果，确定第i+1编程验证操作需要验证的最高编程态。
S120中，可对目标态在第i+1编程验证操作需要验证的编程态范围内的所有存储单元均进行编程验证。
或者，S120中，也可仅对目标态在第i+1编程验证操作需要验证的编程态范围内、且上一次编程中并未编程成功的存储单元进行第i+1编程验证，如此，可减少需要验证的存储单元数量，缩短编程验证时间。需要强调的是，此时，获得的第i+1验证结果中，不仅包括了指示执行第i+1编程验证的存储单元是否编程成功的数据，还包括指示已经编程成功的存储单元数量的信息。
在实际应用过程中，可在施加第i+1编程脉冲之后，执行第i+1编程验证操作。可以理解的是，可以循环执行上述编程验证方法给出的步骤，直至完成编程，或者直至能够执行的编程验证次数达到最大值。
相较于每个编程验证操作有固定的需要验证的编程态范围，本公开实施例中，根据第i编程验证操作的验证结果，确定施加下一个编程脉冲之后执行的第i+1编程验证操作的需要验证的编程态范围，即根据上一次编程验证操作的结果确定下一次编程验证操作需要验证的编程态范围，可以动态确定每个待验证编程态的起始时刻，提高确定的每个待验证编程态的起始时刻的准确性，一方面，可以减少因为编程验证起始时刻设定的过早导致编程时长增加，有利于缩短编程时长；另一方面，可以减少因为编程验证起始时刻设定的过晚导致的过编程，有利于保证编程质量较好。
此外，相较于对同一个编程态，以不同的单位(例如以块为单位或者以字线为单位)进行编程时都需要人为分别设置不同的固定起始时刻，本公开实施例无需人为设置固定起始时刻，而是通过验证结果追踪存储器编程性能的差异，进而自动确定每一次编程验证操作需要验证的编程态范围，方式简单，且能够 及时根据存储器性能调整编程验证操作的需要验证的编程态范围，有利于提高编程质量。
在一些实施例中，第i验证结果中第n态的验证子结果包括：第n态的第i统计数据，用于统计对第n态进行编程的失败比特数；
所述根据第i验证结果中第n态的验证子结果，确定第i+1编程验证操作需要验证的最低编程态，包括：
根据第n态的第i统计数据，确定对第n态进行编程的失败比特数；
当对第n态进行编程的失败比特数小于第一预设值时，确定第i+1编程验证操作需要验证的最低编程态为第n+1态；
当对第n态进行编程的失败比特数大于或等于第一预设值时，确定第i+1编程验证操作需要验证的的最低编程态为第n态。
第n态的第i统计数据，可包括：表示对每一个目标态是第n态的存储单元进行第n编程验证操作是否通过的数据。根据第n态的第i统计数据，可确定对第n态进行第i编程操作的失败比特数。
示例性地，可以采用二进制编码来表示存储单元是否编程通过，例如，可以用0表示编程通过，1表示编程不通过；也可以用1表示编程通过，用0表示编程不通过。在实施时，本领域技术人员可以根据实际情况选择合适的方式表示存储单元是否编程通过，本公开实施例对此并不限定。
可以理解的是，当对第n态进行编程的失败比特数小于第一预设值时，可认为对第n态的编程成功完成，因此，在下一次编程验证过程中，无需再对第n态进行编程验证。如此，相较于每次都验证第n态，可缩短编程验证时间，提高编程速度。
当对第n态进行编程的失败比特数大于或等于第一预设值时，可认为对第n态的编程尚未成功，因此，在下一次编程验证过程中，需要继续对第n态进行编程验证。
在一些实施例中，当对第n态进行编程的失败比特数与目标态为第n态的比特数的比值小于第一预设比值时，确定第i+1编程验证操作需要验证的最低 编程态为第n+1态；
当对第n态进行编程的失败比特数与目标态为第n态的比特数的比值大于或等于第一预设比值时，确定第i+1编程验证操作需要验证的最低编程态为第n态。
类似地，当对第n态进行编程的失败比特数与目标态为第n态的比特数的比值小于第一预设值时，可认为对第n态的编程成功完成，因此，在下一次编程验证过程中，无需再对第n态进行编程验证。如此，相较于每次都验证第n态，可缩短编程验证时间，提高编程速度。
当对第n态进行编程的失败比特数与目标态为第n态的比特数的比值大于或等于第一预设值时，我们可认为对第n态的编程尚未成功，因此，在下一次编程验证过程中，需要继续对第n态进行编程验证。
在一些实施例中，所述方法还包括：
获取待编程存储单元的循环次数；
根据循环次数，确定第一预设值的取值范围或第一预设比值的取值范围。
对于存储器进行一次擦除操作和一次写入操作，称为一个循环(cycle)。随着循环次数的增加，存储器的编程性能可能会发生改变，导致编程速度的变化。可以理解的是，循环是以编程的最小单位来定义的。例如，以块为最小单位进行编程时，该块中每个存储单元的循环次数基本相同。
需要强调的是，当存储器以不同的最小单元进行编程时，获取的循环次数为该编程进行的最小单元的循环次数。
相较于提供固定的第一预设值，本公开实施例中，通过获取待编程存储单元的循环次数，并根据循环次数确定第一预设值，可以在编程验证过程中追踪到随着循环次数变化而变化的编程特性，进而灵活调整第一预设值的范围，减少因为第一预设值确定不当导致的编程速度慢，有利于提高编程速度，保证编程质量较好。
在一些实施例中，第一预设值的取值范围是在对存储器进行的误差校正码(Error Correcting Code，ECC)纠错机制所允许范围内。
需要强调的是，为了保证编程质量，需要在对第n态的编程完成之后，才停止对第n态的编程验证操作。由于存在ECC纠错机制，因此，当对第n态编程失败的比特数在ECC纠错机制允许的范围内时，可通过ECC纠错对至少部分失败的比特进行纠错，保证可以从存储器中读取到正确的数据。
本公开实施例中，由于第一预设值的取值范围在ECC机制所允许的范围内，因此，当对第n态进行编程的失败比特数小于第一预设值时，可通过ECC纠错机制对失败的比特进行纠错，保证第n态的编程能够顺利完成，且下一次编程验证无需验证第n态，有利于减少需要验证的编程态数量，提高编程效率。
在一些实施例中，第一预设比值的取值范围为0.4％至0.6％。例如，第一预设比值的取值可为0.5％。
在一些实施例中，第i验证结果中第n+k态的验证子结果包括：第n+k态的第i统计数据，用于统计对第n+k态进行编程的成功比特数；
所述根据第i验证结果中第n+k态的验证子结果，确定第i+1编程验证操作需要验证的最高编程态，包括：
根据第n+k态的第i统计数据，确定对第n+k态进行编程的成功比特数；
当对第n+k态进行编程的成功比特数大于第二预设值，且第n+k态小于存储器的最高编程态时，确定第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
当对第n+k态进行编程的成功比特数小于或等于第二预设值时，确定第i+1编程验证操作需要验证的最高编程态为第n+k态。
第n+k态的第i统计数据，可包括：表示对每一个目标态是第n+k态的存储单元进行第n编程验证操作是否通过的数据。根据第n+k态的第i统计数据，可确定对第n+k态进行第i编程操作的失败比特数。
当对第n+k态进行编程的成功比特数大于第二预设值，且第n+k态小于存储器的最高编程态时，可认为下一次施加编程脉冲后，可能有很多目标编程态为第n+k态的存储单元会达到目标态，且可能存在目标态为第n+k+1态的存储单元会达到目标态，因此，在下一次编程验证过程中，需要对第n+k+1态进行 编程验证，以减少由于对第n+k+1态开始验证的过晚导致的过编程。
当对第n+k态进行编程的成功比特数小于或等于第二预设值时，可认为对第n+k态的编程尚未成功，且下一次施加编程脉冲之后，目标态为第n+k+1态的存储单元达到目标态的几率很低，因此，在下一次编程验证过程中，无需开始验证第n+k+1态，下一次编程验证操作需要验证的最高态依旧是第n+k态。
在一些实施例中，当对第n+k态进行编程的成功比特数与目标态为第n+k态的比特数的比值大于第二预设比值时，确定第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
当对第n+k态进行编程的成功比特数与目标态为第n+k态的比特数的比值小于或等于第二预设比值时，确定第i+1编程验证操作需要验证的最高编程态为第n+k态。
类似地，当对第n+k态进行编程的成功比特数与目标态为第n+k态的比特数的比值大于第二预设值，且第n+k态小于存储器的最高编程态时，可认为下一次施加编程脉冲后，可能有很多目标编程态为第n+k态的存储单元会达到目标态，且可能存在目标态为第n+k+1态的存储单元会达到目标态，因此，在下一次编程验证过程中，需要开始对第n+k+1态进行编程验证，以减少由于对第n+k+1态开始验证的过晚导致的过编程。
当对第n+k态进行编程的成功比特数与目标态为第n+k态的比特数的比值小于或等于第二预设值时，我们可认为对第n+k态的编程尚未成功，且下一次施加编程脉冲之后，出现目标态为第n+k+1态的存储单元达到目标态的几率很低，因此，在下一次编程验证过程中，无需对第n+k+1态进行验证，下一次编程验证操作需要验证的最高态依旧是第n+k态。
在一些实施例中，所述方法还包括：
获取待编程存储单元的循环次数；
根据循环次数，确定第二预设值的取值范围或第二预设比值的取值范围。
相较于提供固定的第二预设值，本公开实施例中，通过获取待编程存储单元的循环次数，并根据循环次数确定第二预设值，可以在编程验证过程中追踪 到随着循环次数变化而变化的编程特性，进而灵活调整第二预设值的范围，减少因为第二预设值设定不当导致的编程速度慢，有利于提高编程速度，保证编程质量较好。
在一些实施例中，第二预设比值的取值范围为2％至3％。例如，第二预设比值的取值可为2.3％。
在一些实施例中，基于PVS(Program Vt distribution sigma)的理念，以TLC为例，每个编程脉冲都会将阈值电压分布移动～2倍的西格玛(sigma)，不同编程态的验证电平之间的差值在3倍的西格玛左右。为了避免在施加下一个编程脉冲之后，目标编程态为第n+k+1态的存储单元发生过编程，导致其阈值电压超过目标阈值电压，因此，第二预设值的取值可设为正度2倍的西格玛之外(即2.3％)。
当对所述第n+k态进行编程的成功比特数与目标态为第n+k态的比特数的比值大于2.3％时，可认为下一次施加编程脉冲后，可能有很多(例如50％)目标编程态为第n+k态的存储单元会达到目标态，并且，由于第n+k+1态的目标阈值电压分布在负的3倍西格玛处，因此，也会开始出现目标态为第n+k+1态的存储单元达到目标阈值电压的情况，因此，下一次编程验证时就需要开始对第n+k+1态进行验证。
在一些实施例中，所述编程验证方法应用于增量步长脉冲编程方法中，所述编程验证方法还包括：
获取增量步长脉冲编程的步长和/或编程电压斜率(slope)；
根据步长和/或编程电压斜率，确定第二预设值的取值范围；或者，根据步长以及编程电压斜率，确定第二预设比值的取值范围。
示例性地，可采用增量步长脉冲编程(Incremental Step Pulse Programing，ISPP)的方式对存储器进行编程操作。需要指出的是，当步长和/或编程电压斜率发生变化时，存储单元的阈值电压的变化速度也会发生变化，因此，可对应调整第二预设值和第二预设比值的取值范围。
具体地，以步长为例，当步长较大时，施加每一个编程脉冲之后存储单元 的阈值电压较大地增加，因此，第二预设值和第二预设比值的取值可以相对较小。当步长较小时，施加每一个编程脉冲之后存储单元的阈值电压较小地增加，因此，第二预设值和第二预设比值的取值可以相对较大。
例如，以QLC为例，可采用粗调编程(corase programming)或者微调编程(fine programming)，粗调编程的步长大于微调编程的步长，因此，采用粗调编程时第二预设值的取值，小于采用微调编程时第二预设值的取值；或者，采用粗调编程时第二预设比值的取值，小于采用微调编程时第二预设比值的取值。
相较于提供固定的第二预设值以及第二预设比值，本公开实施例中，通过获取增量步长脉冲编程的步长和/或编程电压斜率，并根据步长和/或编程电压斜率，确定第二预设值的取值范围；或者，根据步长以及编程电压斜率，确定第二预设比值的取值范围，可以灵活调整第二预设值以及第二预设比值的范围，减少因为第二预设值以及第二预设比值设定不当导致的编程速度慢，有利于提高编程速度，保证编程质量较好。
在一些实施例中，S110包括：
对第i验证结果中的第n态的验证子结果以及第n+k态的验证子结果分别进行抽样，获得第n态的第i抽样统计数据和第n+k态的第i抽样统计数据；
根据第n态的第i抽样统计数据，确定第i+1编程验证操作需要验证的最低编程态；
根据第n+k态的第i抽样统计数据，确定第i+1编程验证操作需要验证的最高编程态。
在进行编程验证操作的过程中，产生的验证结果可以寄存在页面缓存器(page buffer)中，这些数据可用于在后续施加编程脉冲的过程中，确定需要施加编程禁止电压的存储单元。具体地，验证结果可以寄存在页面缓存器中的特定锁存器(dedicated latch)中，该特定锁存器仅用于暂存编程验证操作的验证结果。或者，验证结果还可以寄存在页面缓存器中的一些其他锁存器中，这些锁存器还可用于存储编程数据、或者编程禁止信息等。
第n态的第i抽样统计数据可包括：对目标编程态为第n态的所有存储单元的验证结果进行随机抽样，并对抽样结果进行失败比特数统计得到的统计数据。
第n+k态的第i抽样统计数据可包括：对目标编程态为第n+k态的所有存储单元的验证结果进行随机抽样，并对抽样结果进行失败比特数统计得到的统计数据。
示例性地，当页面缓存器中有16KB个锁存器用于存储上述验证结果时，可随机选择其中4KB个锁存器存储的验证结果作为抽样样本数据，以确定第i+1编程验证操作需要验证的最低编程态和最高编程态。
可以理解的是，在一些实施例中，还可以随机选择其中2KB个或者8KB个锁存器存储的数据作为抽样样本数据，以确定第i+1编程验证操作需要验证的最低编程态和最高编程态。
需要强调的是，在对失败比特数统计数据进行抽样，以获得第n态的第i抽样统计数据和第n+k态的第i抽样统计数据时，不局限于需要以一整个锁存器为单位获取数据，也可以仅获取某个锁存器中的部分数据作为抽样统计数据。
每一次编程验证操作之后，产生的验证结果包括的数据量较大，尤其是对每个待编程存储单元都进行编程验证时。因此，若对所有的存储单元的验证结果都进行计数统计，那么会延长执行失败比特数计数所需要的时间，导致编程时间增加。
本公开实施例中，通过对第n态的验证子结果以及第n+k态的验证子结果分别进行抽样，获得第n态的第i抽样统计数据和第n+k态的第i抽样统计数据，并根据第n态的第i抽样统计数据，确定第i+1编程验证操作需要验证的最低编程态，根据第n+k态的第i抽样统计数据，确定第i+1编程验证操作需要验证的最高编程态，可以减少每次进行失败比特数统计所需要统计的数据总量，有利于缩短失败比特数统计的时间，提高第i+1编程验证操作需要验证的编程态的确定范围，进而提高编程速度，缩短编程时长，提高存储器性能。
在相关技术中，存储器的编程通常利用以下迭代过程执行：向存储单元施 加编程脉冲，并响应所述编程脉冲验证所述存储单元是否已达到所需的数据状态(即目标编程态)，并且在存储单元编程验证通过之前一直重复所述迭代过程。当存储单元通过验证后，则禁止进行进一步编程，但是其它并未达到目标编程态的存储单元仍可针对后续编程脉冲进行编程。
在每次验证操作之后，通常需要对本次编程操作中验证不通过的存储单元的数量进行统计，也即执行失败比特数统计(Fail Bit Count，FBC)。相关技术中，在时序上，统计失败比特数的操作是在当前编程操作和下一次编程操作之间执行的，需要占用额外的时间，导致编程时间较长。
有鉴于此，图3是根据一示例性实施例示出的一种存储器的编程方法的流程图。参照图3所示，所述编程方法包括以下步骤：
S200：对存储器的待编程存储单元施加第i+1编程脉冲；
S210：在施加第i+1编程脉冲的过程中，根据第i编程验证操作的第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，对第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得第i计数结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
S220：根据第i计数结果，确定第i+1编程验证操作需要验证的编程态范围；
S230：根据确定的第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
S200中，可以通过存储器设备的外围电路中的编程操作电路，对存储单元阵列执行编程脉冲施加操作，以控制选择的存储器单元阵列的位线的电位水平。
S210中，第i+1编程脉冲的过程中，可包括第i+1编程准备操作阶段和第i+1编程稳定执行阶段。其中，第i+1编程准备操作为执行第i+1编程操作相关的状态和数据的准备操作，在电压时序上对应对选择字线施加第i+1通过电压(Vpass)的阶段，第i+1编程稳定执行阶段为在编程脉冲施加操作期间响应编程数据来控制存储器单元阵列的位线的电位水平，在电压时序上对应对选择字线 施加第i+1编程电压的阶段。
在一些实施例中，可以在第i+1编程准备操作之后，也即对选择字线施加第i+1通过电压之后，在第i+1编程稳定执行阶段读取第i统计数据。
S220中，第i计数结果可包括上述编程验证方法中的第n态的第i统计数据和第n+k态的第i统计数据。或者，第i计数结果可包括上述编程验证方法中的第i抽样统计数据，如此，根据第i计数结果确定第i+1编程验证操作需要验证的编程态范围，可参照本公开实施例提供的编程验证方法中，在此不再赘述。
相较于在施加第i编程脉冲和第i+1编程脉冲之间进行失败比特数计数，以确定第i+1编程脉冲之后进行的第i+1编程验证操作需要验证的编程态范围，本公开实施例提供的编程方法，可以在施加第i+1编程脉冲的过程中，根据第i编程验证操作的第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，对第n态的编程结果以及第n+k态的编程结果分别进行失败比特数计数，以确定第i+1编程验证操作需要验证的编程态范围，这样，在整个编程操作的迭代过程中进行失败比特数计数的操作不占用额外的时间，从而可以节省整个编程操作的迭代过程的执行时间，提高对存储器单元编程的效率。
并且，本公开实施例通过将失败比特数计数过程隐藏在施加编程脉冲的过程中，可以节约逻辑开销(logic overhead)。
示例性地，在时序上，S220可在S210和S230之间执行。
优选地，在时序上，S220可与S210重叠。具体地，可以在施加第i+1编程脉冲的过程中，且在得到第i计数结果之后，执行S220。如此，可将确定第i+1编程验证操作需要验证的编程态范围隐藏在施加第i+1编程脉冲的过程中，这样，在整个编程操作的迭代过程中，确定第i+1编程验证操作需要验证的编程态范围的操作不占用额外的时间，从而可以进一步节省整个编程操作的迭代过程的执行时间，提高对存储器单元编程的效率。
在一些实施例中，第i计数结果包括：第i编程操作中对第n态进行编程的失败比特数；
S220可包括：
当对第n态进行编程的失败比特数小于第一预设值时，确定第i+1编程验证操作需要验证的最低编程态为第n+1态；
当对所述第n态进行编程的失败比特数大于或等于所述第一预设值时，确定第i+1编程验证操作需要验证的最低编程态为第n态。
在一些实施例中，S220可包括：
当对所述第n态进行编程的失败比特数与目标态为第n态的比特数的比值小于第一预设比值时，确定第i+1编程验证操作需要验证的最低编程态为第n+1态；
当对所述第n态进行编程的失败比特数与目标态为第n态的比特数的比值大于或等于第一预设比值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n态。
在一些实施例中，第i计数结果包括：第i编程操作中对第n+k态进行编程的失败比特数；
S220可包括：
当对第n+k态进行编程的成功比特数大于第二预设值，且第n+k态小于所述存储器的最高编程态时，确定第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
当对第n+k态进行编程的成功比特数小于或等于第二预设值时，确定第i+1编程验证操作需要验证的最高编程态为第n+k态。
在一些实施例中，S220可包括：
当对第n+k态进行编程的成功比特数与目标态为所述第n+k态的比特数的比值大于第二预设比值时，确定第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
当对第n+k态进行编程的成功比特数与目标态为第n+k态的比特数的比值小于或等于第二预设比值时，确定第i+1编程验证操作需要验证的最高编程态为第n+k态。
在一些实施例中，S210可包括：
对第i验证结果中的第n态的验证子结果以及第n+k态的验证子结果分别进行抽样，获得第n态的第i抽样样本数据和第n+k态的第i抽样样本数据；
根据第n态的第i抽样样本数据和第n+k态的第i抽样样本数据，对第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得第i计数结果。
第i计数结果可包括第n态的第i抽样统计数据和第n+k态的第i抽样统计数据。
示例性地，可对目标编程态为第n态的所有存储单元的验证结果进行随机抽样，获得第n态的第i抽样样本数据，然后对第n态的第i抽样样本数据进行失败比特数统计得到第n态的第i抽样统计数据。
类似地，可对目标编程态为第n+k态的所有存储单元的验证结果进行随机抽样，获得第n+k态的第i抽样样本数据，然后对第n+k态的第i抽样样本数据进行失败比特数统计得到第n+k态的第i抽样统计数据。
本公开实施例中，通过对第n态的验证子结果以及第n+k态的验证子结果分别进行抽样，获得第n态的第i抽样样本数据和第n+k态的第i抽样样本数据，并根据第n态的第i抽样样本数据和第n+k态的第i抽样样本数据，获得第i计数结果，可以减少每次进行失败比特数统计所需要统计的数据总量，有利于缩短失败比特数统计的时间，提高第i+1编程验证操作需要验证的编程态的确定范围，进而提高编程速度，缩短编程时长，提高存储器性能。
下面，参照图4所示，以TLC为例，示出一种三维NAND存储器进行编程操作的局部流程图，该编程方法包括以下步骤：
S300：执行第i编程验证，以对目标态为第n态至第n+k态的存储单元执行编程验证(即验证(PVn，……，PVn+k))；其中，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
S310：在执行第i编程验证之后，施加第i+1编程脉冲；在施加第i+1编程脉冲的过程中，根据第i编程验证操作的第i验证结果中第n态的验证子结果以 及第n+k态的验证子结果，对第i编程操作中第n态的编程和第n+k态的编程分别进行失败比特数计数，获得第i计数结果；
S320：根据第i计数结果，判断对第n态进行编程验证(即PVn)时的失败比特数是否小于第一预设值；
S330：根据第i计数结果，判断对第n+k态进行编程验证(即PVn+k)时的成功比特数是否大于第二预设值；
当对第n态进行编程验证(即PVn)时的失败比特数小于第一预设值，且对第n+k态进行编程验证(即PVn+k)时的成功比特数大于第二预设值时，可确定第i+1编程验证操作需要验证的编程态范围为第n+1态至第n+k+1态，因此，跳转至执行S331；
当对第n态进行编程验证(即PVn)时的失败比特数小于第一预设值，且对第n+k态进行编程验证(即PVn+k)时的成功比特数小于或等于第二预设值时，可确定第i+1编程验证操作需要验证的编程态范围为第n+1态至第n+k态，因此，跳转至执行S332；
当对第n态进行编程验证(即PVn)时的失败比特数大于或等于第一预设值，且对第n+k态进行编程验证(即PVn+k)时的成功比特数大于第二预设值时，可确定第i+1编程验证操作需要验证的编程态范围为第n态至第n+k+1态，因此，跳转至执行S341；
当对第n态进行编程验证(即PVn)时的失败比特数大于或等于第一预设值，且对第n+k态进行编程验证(即PVn+k)时的成功比特数小于或等于第二预设值时，可确定第i+1编程验证操作需要验证的编程态范围为第n态至第n+k态，因此，跳转至执行S342；
S331：执行第i+1编程验证，以对目标态为第n+1态至第n+k+1态的存储单元执行编程验证(即验证(PVn+1，……，PVn+k+1))；其中，第n+k+1态小于或等于所述存储器的最高编程态；
S332：执行第i+1编程验证，以对目标态为第n+1态至第n+k态的存储单元执行编程验证(即验证(PVn+1，……，PVn+k))；
S341：执行第i+1编程验证，以对目标态为第n态至第n+k+1态的存储单元执行编程验证(即验证(PVn，……，PVn+k+1))；其中，第n+k+1态小于或等于所述存储器的最高编程态；
S342：执行第i+1编程验证，以对目标态为第n态至第n+k态的存储单元执行编程验证(即验证(PVn，……，PVn+k))；
S350：在完成第i+1编程验证之后，施加编程脉冲，并在施加编程脉冲的过程中，根据第i+1编程验证操作的第i+1验证结果中最低态的验证子结果以及最高态的验证子结果，对第i+1编程操作中最低态的编程和最高态的编程分别进行失败比特数计数，获得第i+1计数结果。
需要强调的是，每次执行编程验证时，验证的最高态一定小于或等于该存储器能够被编程的最高态。当根据S330确定出的下一次编程验证的最高态大于该存储器能够被编程的最高态时，执行下一次编程验证时的最高态依旧为该存储器能够被编程的最高态。
以TLC为例，能够被编程的最高态为L7，那么当第i编程验证操作的最高态为L7，且PV7的成功比特数大于第二预设值时，第i+1编程验证操作的最高态依旧为L7。
具体地，以TLC为例，i的取值为4，n的取值为1，k的取值为1时，所述方法包括以下步骤：
步骤一：执行第4编程验证操作(即执行S300)，第4编程验证操作的验证态范围为第1态至第2态，获得如图1中(d)所示的阈值电压分布曲线；
步骤二：在执行第4编程验证之后，施加第5编程脉冲，并且，在施加第5编程脉冲的过程中，根据第4编程验证操作的验证结果中最低态(即第1态)的验证子结果以及最高态(即第2态)的验证子结果，对第4编程操作中第1态的编程和第2态的编程分别进行失败比特数计数，获得第4计数结果(即第一次执行S310)；
随后，根据第4计数结果，确定第5编程验证操作需要验证的编程态范围。具体地，可执行步骤三：根据第4计数结果，判断第4编程验证操作中对第1 态进行编程验证时的失败比特数是否小于第一预设值(即执行S320)；根据第4计数结果，判断第2态进行编程验证时的成功比特数是否大于第二预设值(即执行S330)；
步骤四：当第4计数结果表示第4编程验证操作中，对第1态进行编程验证时的失败比特数小于第一预设值，且对第2态进行编程验证时的成功比特数大于第二预设值时，跳转至执行步骤五(即执行S331)；
当第4计数结果表示第4编程验证操作中，对第1态进行编程验证时的失败比特数小于第一预设值，且对第2态进行编程验证时的成功比特数小于或等于第二预设值时，跳转至执行步骤六(即执行S332)；
当第4计数结果表示第4编程验证操作中，对第1态进行编程验证时的失败比特数大于或等于第一预设值时，且对第2态进行编程验证时的成功比特数大于第二预设值时，跳转至执行步骤七(即执行S341)；
当第4计数结果表示第4编程验证操作中，对第1态进行编程验证时的失败比特数大于或等于第一预设值，且对第2态进行编程验证时的通过比特数小于或等于第二预设值时，跳转至执行步骤八(即执行S342)；
步骤五：进行第5编程验证操作，其中，第5编程验证操作需要验证的目标态范围为第2态至第3态；随后执行步骤九；
步骤六：进行第5编程验证操作，其中，第5编程验证操作需要验证的目标态为第2态；随后执行步骤九；
步骤七：进行第5编程验证操作，其中，第5编程验证操作需要验证的目标态范围为第1态至第3态；随后执行步骤九；
步骤八：进行第5编程验证操作，其中，第5编程验证操作需要验证的目标态范围为第1态至第2态；随后执行步骤九；
步骤九：施加第6编程脉冲；并且，在施加第6编程脉冲的过程中，对第5编程验证操作中验证的最低编程态进行失败比特数计数，并对第5编程验证操作中验证的最高编程态进行失败比特数计数，获得第5计数结果(即执行S350)。
可以理解的是，在实际编程操作过程中，可循环执行上述编程方法，直至完成编程，或者直至施加编程脉冲的次数达到最大次数，或者直至进行编程验证的次数达到最大值。
图5是根据一示例性实施例示出的一种存储器100的示意图。参照图5所示，存储器100包括：
存储器单元阵列110，存储器单元阵列110包括多个存储器单元行；
多个字线120，多个字线120分别耦合到多个存储器单元行；
外围电路130，外围电路130耦合到多个字线120并且被配置为对多个存储器单元行中的选定存储器单元行执行编程验证操作，选定存储器单元行耦合到选定字线，其中，为了执行编程验证操作，外围电路130被配置为：
获取第i编程验证操作的第i验证结果；其中，第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于存储器的最高编程态；
根据第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的编程态范围；
根据确定的第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
存储器单元阵列110可以是NAND闪存存储器单元阵列，其中，存储器单元阵列110以NAND存储器串111的阵列的形式提供，每个NAND存储器串111在衬底(未示出)上方垂直地延伸。在一些实施方式中，每个NAND存储器串111包括串联耦合并且垂直地堆叠的多个存储器单元112。每个存储器单元112可以保持连续模拟值，例如，电压或电荷，其取决于在存储器单元112的区域内捕获的电子的数量。每个存储器单元112可以是包括浮栅晶体管的浮栅类型的存储器单元，或者是包括电荷捕获晶体管的电荷捕获类型的存储器单元。
在一些实施方式中，每个存储器单元112是具有两种可能的存储器状态并且因此可以存储一位数据的单级单元。例如，第一存储器状态“0”可以对应于 第一电压范围，并且第二存储器状态“1”可以对应于第二电压范围。
在一些实施方式中，每个存储器单元112是能够在多于四个的存储器状态中存储多于单个位的数据的单元。例如，可以每单元存储两位(又被称为多级单元)，可以每单元存储三位(又被称为三级单元)，或者可以每单元存储四位(又被称为四级单元)。每个MLC可以被编程为采取可能的标称存储值的范围。在一个示例中，如果每个MLC存储两位数据，则MLC可以被编程为通过将三个可能的标称存储值中的一个写入到该单元而从擦除状态采取三个可能的编程级中的一个。第四标称存储值可以用于擦除状态。
如图5中所示，每个NAND存储器串111可以包括在其源极端处的源极选择栅极(SSG)113和在其漏极端处的漏极选择栅极(DSG)114。源极选择栅极113和漏极选择栅极114可以被配置为在读取和编程操作期间激活选定的NAND存储器串111(阵列的列)。
在一些实施方式中，同一块115中的NAND存储器串111的源极通过同一源极线(SL)116(例如，公共SL)耦合。换句话说，根据一些实施方式，同一块115中的所有NAND存储器串111具有阵列公共源极(ACS)。
根据一些实施方式，每个NAND存储器串111的漏极选择栅极114耦合到相应的位线117，可以经由输出总线(未示出)从位线117读取或写入数据。
在一些实施方式中，每个NAND存储器串111被配置为通过经由一个或多个DSG线118将选择电压(例如，高于具有漏极选择栅极114的晶体管的阈值电压)或取消选择电压(例如，0V)施加到相应的漏极选择栅极114。和/或，在一些实施方式中，每个NAND存储器串111被配置为通过经由一个或多个SSG线119将选择电压(例如，高于具有源极选择栅极113的晶体管的阈值电压)或取消选择电压(例如，0V)施加到相应的源极选择栅极113而被选择或被取消选择。
如图5中所示，NAND存储器串111可以被组织为多个块115，多个块115的每一个可以具有公共源极线116(例如，耦合到地)。在一些实施方式中，每个块115是用于擦除操作的基本数据单位，即，同一块115上的所有存储器单 元112同时被擦除。为了擦除选定块中的存储器单元112，可以用擦除电压(Vers)(例如，高正电压(例如，20V或更高))偏置耦合到选定块以及与该选定块在同一面中的未选定块的源极线。
应当理解，在一些示例中，可以在半块级、在四分之一块级或者在具有任何合适数量的块或块的任何合适的分数的级执行擦除操作。相邻NAND存储器串111的存储器单元112可以通过字线120耦合，字线120选择存储器单元112的哪一行受读取和编程操作的影响。
在一些实施方式中，每个字线120耦合到存储器单元112的页130，页130是用于编程操作的基本数据单位。以位为单位的一页130的大小，可以与一个块115中由字线120耦合的NAND存储器串111的数量相关。每个字线120可以包括在相应页130中的每个存储器单元112处的多个控制栅极(栅极电极)以及耦合控制栅极的栅极线。可以理解的是，一个存储器单元行即为位于同一页130的多个存储器单元112。
图6示出了根据本公开的一些方面的包括NAND存储器串111的示例性存储器单元阵列110的截面的侧视图。如图6中所示，NAND存储器串111可以在衬底101上方垂直地延伸穿过存储器堆叠层102。衬底101可以包括硅(例如，单晶硅)、硅锗(SiGe)、砷化镓(GaAs)、锗(Ge)、绝缘体上硅(SOI)、绝缘体上锗(GOI)或者任何其他合适的材料。
存储器堆叠层102可以包括交替的栅极导电层103和栅极到栅极电介质层104。存储器堆叠层102中的栅极导电层103和栅极到栅极电介质层104的对的数量可以确定存储器单元阵列110中的存储器单元112的数量。
栅极导电层103可以包括导电材料，导电材料包括但不限于钨(W)、钴(Co)、铜(Cu)、铝(Al)、多晶硅、掺杂硅、硅化物或其任何组合。在一些实施方式中，每个栅极导电层103包括金属层，例如，钨层。在一些实施方式中，每个栅极导电层103包括掺杂多晶硅层。每个栅极导电层103可以包括围绕存储器单元112的控制栅极，并且可以在存储器堆叠层102的顶部处横向地延伸作为DSG线118、在存储器堆叠层102的底部处横向地延伸作为SSG线 119、或者在DSG线118与SSG线119之间横向地延伸作为字线120。
如图6中所示，NAND存储器串111包括垂直地延伸穿过存储器堆叠层102的沟道结构105。在一些实施方式中，沟道结构105包括填充有(一种或多种)半导体材料(例如，作为半导体沟道106)和(一种或多种)电介质材料(例如，作为存储器膜107)的沟道孔。在一些实施方式中，半导体沟道106包括硅，例如，多晶硅。在一些实施方式中，存储器膜107是包括隧穿层108、存储层109(又称为“电荷捕获/存储层”)和阻挡层1010的复合电介质层。沟道结构105可以具有圆柱形状(例如，柱形状)。根据一些实施方式，半导体沟道106、隧穿层108、存储层109和阻挡层1010以此顺序从圆柱的中心朝向圆柱的外表面径向布置。隧穿层108可以包括氧化硅、氮氧化硅或其任何组合。存储层109可以包括氮化硅、氮氧化硅或其任何组合。阻挡层1010可以包括氧化硅、氮氧化硅、高介电常数(高k)电介质或其任何组合。在一个示例中，存储器膜107可以包括氧化硅/氮氧化硅/氧化硅(ONO)的复合层。
根据一些实施方式，如图6中所示，阱414(例如，P阱和/或N阱)形成在衬底101中，并且NAND存储器串111的源极端与阱414接触。例如，源极线116可以耦合到阱414，以在擦除操作期间将擦除电压施加到阱414(即，NAND存储器串111的源极)。在一些实施方式中，NAND存储器串111还包括在NAND存储器串111的漏极端处的沟道插塞416。应当理解，尽管在图6中未示出，但是可以形成存储器单元阵列110的附加部件，附加部件包括但不限于栅极线缝隙/源极触点、局部触点、互连层等。
返回参考图5，外围电路130可以通过位线117、字线120、源极线116、SSG线119和DSG线118耦合到存储器单元阵列110。外围电路130可以包括任何合适的模拟、数字以及混合信号电路，以用于通过经由位线117、字线120、源极线116、SSG线119和DSG线118将电压信号和/或电流信号施加到每个目标存储器单元112以及从每个目标存储器单元112感测电压信号和/或电流信号来促进存储器单元阵列110的操作。
外围电路130可以包括使用金属-氧化物-半导体(MOS)技术形成的各种 类型的外围电路。例如，图7示出了一些示例性外围电路130，外围电路130包括页缓冲器/感测放大器504、列解码器/位线(BL)驱动器506、行解码器/字线(WL)驱动器508、电压发生器510、控制逻辑单元512、寄存器514、接口516和数据总线518。应当理解，在一些示例中，还可以包括图7中未示出的附加外围电路。
页缓冲器/感测放大器504可以被配置为根据来自控制逻辑单元512的控制信号从存储器单元阵列110读取数据以及向存储器单元阵列110编程(写入)数据。在一个示例中，页缓冲器/感测放大器504可以存储要被编程到存储器单元阵列110的一个页130中的一页编程数据(写入数据)。在另一示例中，页缓冲器/感测放大器504可以执行编程验证操作，以确保数据已经被正确地编程到耦合到选定字线120的存储器单元112中。在又一示例中，页缓冲器/感测放大器504还可以感测来自位线117的表示存储在存储器单元112中的数据位的低功率信号，并且在读取操作中将小电压摆幅放大到可识别的逻辑电平。列解码器/位线驱动器506可以被配置为由控制逻辑单元512控制，并且通过施加从电压发生器510生成的位线电压来选择一个或多个NAND存储器串111。
行解码器/字线驱动器508可以被配置为由控制逻辑单元512控制，并且选择/取消选择存储器单元阵列110的块115并且选择/取消选择块115的字线120。行解码器/字线驱动器508还可以被配置为使用从电压发生器510生成的字线电压(V WL)来驱动字线120。在一些实施方式中，行解码器/字线驱动器508还可以选择/取消选择并且驱动SSG线119和DSG线118。如下文详细描述的，行解码器/字线驱动器508被配置为对耦合到(一个或多个)选定字线120的存储器单元112执行擦除操作。电压发生器510可以被配置为由控制逻辑单元512控制，并且生成要被供应到存储器单元阵列110的字线电压(例如，读取电压、编程电压、通过电压、局部电压、验证电压等)、位线电压和源极线电压。
控制逻辑单元512可以耦合到上文描述的每个外围电路，并且被配置为控制每个外围电路的操作。寄存器514可以耦合到控制逻辑单元512，并且包括状态寄存器、命令寄存器和地址寄存器，以用于存储用于控制每个外围电路的 操作的状态信息、命令操作码(OP码)和命令地址。接口516可以耦合到控制逻辑单元512，并且充当控制缓冲器，以缓冲从主机(未示出)接收的控制命令并且并将其中继到控制逻辑单元512，以及缓冲从控制逻辑单元512接收的状态信息并且将其中继到主机。接口516还可以经由数据总线518耦合到列解码器/位线驱动器506，并且充当数据I/O接口和数据缓冲器，以缓冲数据并且将其中继到存储器单元阵列110或从存储器单元阵列110中继或缓冲数据。
需要强调的是，外围电路130被配置为对多个存储器单元行中的选定存储器单元行执行本公开实施例提供的编程验证操作。
图8是根据一示例性实施例示出的一种存储器200的示意图。参照图8所示，存储器200包括：
存储器单元阵列110，存储器单元阵列110包括多个存储器单元行；
多个字线120，多个字线120分别耦合到多个存储器单元行；以及
外围电路230，外围电路230耦合到多个字线120并且被配置为对多个存储器单元行中的选定存储器单元行执行编程操作，选定存储器单元行耦合到选定字线，其中，为了执行编程操作，外围电路230被配置为：
对存储器的待编程存储单元施加第i+1编程脉冲；
在施加第i+1编程脉冲的过程中，根据第i编程验证操作的第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，对第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得第i计数结果；其中，第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于存储器的最高编程态；
根据第i计数结果，确定第i+1编程验证操作需要验证的编程态范围；
根据确定的第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
需要强调的是，外围电路230被配置为对多个存储器单元行中的选定存储器单元行执行本公开实施例提供的编程操作。
示例性地，外围电路230的结构可与外围电路130的结构可相同。
图9a是根据一示例性实施例示出的一种存储器系统300的示意图，图9b是根据一示例性实施例示出的另一种存储器系统300的示意图。参照图9a和图9b所示，存储器系统300包括：
一个或多个存储器100或存储器200；
耦合到存储器100或存储器200并且被配置为控制存储器100或存储器200的存储器控制器321。
系统300可以是移动电话、台式计算机、膝上型计算机、平板计算机、车辆计算机、游戏控制台、打印机、定位设备、可穿戴电子设备、智能传感器、虚拟现实(VR)设备、增强现实(AR)设备或者其中具有储存器的任何其他合适的电子设备。
如图9a中所示，系统300可以包括主机310和存储子系统320，存储子系统320具有一个或多个存储器100或存储器200，存储子系统还包括存储器控制器321。主机310可以是电子设备的处理器(例如，中央处理单元(CPU))或者片上系统(SoC)(例如，应用处理器(AP))。主机310可以被配置为将数据发送到存储器100或存储器200。或者，主机310可以被配置为从存储器100或存储器200接收数据。
存储器100或存储器200可以是本公开中公开的任何存储器器件。存储器100或存储器200(例如，NAND闪存存储器器件(例如，三维(3D)NAND闪存存储器器件))可以在擦除操作期间具有来自耦合到未选定字线的驱动晶体管(例如，串驱动器)的减小的漏电流，这允许驱动晶体管的进一步尺寸缩小。
根据一些实施方式，存储器控制器321还耦合到主机310。存储器控制器321可以管理存储在存储器100或存储器200中的数据，并且与主机310通信。
在一些实施方式中，存储器控制器321被设计为用于在低占空比环境中操作，如安全数字(SD)卡、紧凑型闪存(CF)卡、通用串行总线(USB)闪存驱动器、或用于在诸如个人计算器、数字相机、移动电话等的电子设备中使用的其他介质。
在一些实施方式中，存储器控制器321被设计为用于在高占空比环境固态 硬盘(SSD)或嵌入式多媒体卡(eMMC)中操作，SSD或eMMC用作诸如智能电话、平板计算机、膝上型计算机等的移动设备的数据储存器以及企业存储阵列。
存储器控制器321可以被配置为控制存储器100或存储器200的操作，例如读取、擦除和编程操作。存储器控制器321还可以被配置为管理关于存储在或要存储在存储器100或存储器200中的数据的各种功能，包括但不限于坏块管理、垃圾收集、逻辑到物理地址转换、损耗均衡等。在一些实施方式中，存储器控制器321还被配置为处理关于从存储器100或存储器200读取的或者被写入到存储器100或存储器200的数据的纠错码(ECC)。
存储器控制器321还可以执行任何其他合适的功能，例如，格式化存储器100或存储器200。存储器控制器321可以根据特定通信协议与外部设备(例如，主机310)通信。例如，存储器控制器321可以通过各种接口协议中的至少一种与外部设备通信，接口协议例如USB协议、MMC协议、外围部件互连(PCI)协议、PCI高速(PCI-E)协议、高级技术附件(ATA)协议、串行ATA协议、并行ATA协议、小型计算机小型接口(SCSI)协议、增强型小型磁盘接口(ESDI)协议、集成驱动电子设备(IDE)协议、Firewire协议等。
存储器控制器321和一个或多个存储器100或存储器200可以集成到各种类型的存储设备中，例如，包括在相同封装(例如，通用闪存存储(UFS)封装或eMMC封装)中。也就是说，存储器系统100可以实施并且封装到不同类型的终端电子产品中。
在如图10a中所示的一个示例中，存储器控制器321和单个存储器100可以集成到存储器卡400中。存储器卡400可以包括PC卡(PCMCIA，个人计算机存储器卡国际协会)、CF卡、智能媒体(SM)卡、存储器棒、多媒体卡(MMC、RS-MMC、MMCmicro)、SD卡(SD、miniSD、microSD、SDHC)、UFS等。存储器卡400还可以包括将存储器卡400与主机(例如，图9a中的主机310)耦合的存储器卡连接器410。
在如图10b中所示的另一示例中，存储器控制器321和多个存储器100可 以集成到固态驱动器(SSD)500中。固态驱动器500还可以包括将固态驱动器500与主机(例如，图9a中的主机310)耦合的固态驱动器连接器510。在一些实施方式中，固态驱动器500的存储容量和/或操作速度大于存储器卡400的存储容量和/或操作速度。
可以理解的是，存储器控制器321可以执行如本公开任一实施例提供的编程验证方法或者编程方法。
以上存储器设备实施例的描述，与上述方法实施例的描述是类似的，具有同方法实施例相似的有益效果。对于本公开存储器设备实施例中未披露的技术细节，请参照本公开方法实施例的描述而理解。
应理解，说明书通篇中提到的“一些实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一些实施例中”或“在另一些实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽 略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本公开各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本公开的实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种存储器的编程验证方法，包括：
    获取第i编程验证操作的第i验证结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
    根据所述第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的编程态范围；
    根据确定的所述第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
  2. 根据权利要求1所述的方法，其中，所述根据所述第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的的编程态范围，包括：
    根据所述第i验证结果中第n态的验证子结果，确定所述第i+1编程验证操作需要验证的最低编程态；
    根据所述第i验证结果中第n+k态的验证子结果，确定所述第i+1编程验证操作需要验证的最高编程态。
  3. 根据权利要求2所述的方法，其中，所述第i验证结果中第n态的验证子结果包括：第n态的第i统计数据，用于统计对第n态进行编程的失败比特数；
    所述根据所述第i验证结果中第n态的验证子结果，确定所述第i+1编程验证操作需要验证的最低编程态，包括：
    根据所述第n态的第i统计数据，确定对所述第n态进行编程的失败比特数；
    当对所述第n态进行编程的失败比特数小于第一预设值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n+1态；
    当对所述第n态进行编程的失败比特数大于或等于所述第一预设值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n态；
    或者，
    当对所述第n态进行编程的失败比特数与目标态为所述第n态的比特数的比值小于第一预设比值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n+1态；
    当对所述第n态进行编程的失败比特数与目标态为所述第n态的比特数的比值大于或等于所述第一预设比值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n态。
  4. 根据权利要求3所述的方法，其中，所述方法还包括：
    获取待编程存储单元的循环次数；
    根据所述循环次数，确定所述第一预设值的取值范围或所述第一预设比值的取值范围。
  5. 根据权利要求3所述的方法，其中，
    所述第一预设值的取值范围是在对所述存储器进行的误差校正码纠错机制所允许范围内。
  6. 根据权利要求2所述的方法，其中，所述第i验证结果中第n+k态的验证子结果包括：第n+k态的第i统计数据，用于统计对第n+k态进行编程的成功比特数；
    所述根据所述第i验证结果中第n+k态的验证子结果，确定所述第i+1编程验证操作需要验证的最高编程态，包括：
    根据所述第n+k态的第i统计数据，确定对所述第n+k态进行编程的成功比特数；
    当对所述第n+k态进行编程的成功比特数大于第二预设值，且所述第n+k态小于所述存储器的最高编程态时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
    当对所述第n+k态进行编程的成功比特数小于或等于所述第二预设值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k态；
    或者，
    当对所述第n+k态进行编程的成功比特数与目标态为所述第n+k态的比特数的比值大于第二预设比值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
    当对所述第n+k态进行编程的成功比特数与目标态为所述第n+k态的比特数的比值小于或等于所述第二预设比值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k态。
  7. 根据权利要求6所述的方法，其中，所述方法还包括：
    获取增量步长脉冲编程的步长和/或编程电压斜率；根据所述步长和/或所述编程电压斜率，确定所述第二预设值或所述第二预设比值的取值范围；其中，所述编程验证方法应用于增量步长脉冲编程方法中；
    或者，
    获取待编程存储单元的循环次数；根据所述循环次数，确定所述第二预设值的取值范围或所述第二预设比值的取值范围。
  8. 根据权利要求6所述的方法，其中，所述第二预设比值的取值范围为2％至3％。
  9. 根据权利要求1所述的方法，其中，所述根据所述第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的编程态范围，包括：
    对所述第i验证结果中的第n态的验证子结果以及第n+k态的验证子结果分别进行抽样，获得第n态的第i抽样统计数据和第n+k态的第i抽样统计数据；
    根据所述第n态的第i抽样统计数据，确定所述第i+1编程验证操作需要验证的最低编程态；
    根据所述第n+k态的第i抽样统计数据，确定所述第i+1编程验证操作需要验证的最高编程态。
  10. 一种存储器的编程方法，包括：
    对所述存储器的待编程存储单元施加第i+1编程脉冲；
    在施加所述第i+1编程脉冲的过程中，根据第i编程验证操作的第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，对第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得第i计数结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
    根据所述第i计数结果，确定第i+1编程验证操作需要验证的编程态范围；
    根据确定的所述第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
  11. 根据权利要求10所述的方法，其中，所述第i计数结果包括：所述第i编程操作中对所述第n态进行编程的失败比特数；
    所述根据所述第i计数结果，确定第i+1编程验证操作需要验证的编程态范围，包括：
    当对所述第n态进行编程的失败比特数小于第一预设值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n+1态；
    当对所述第n态进行编程的失败比特数大于或等于所述第一预设值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n态；
    或者，
    当对所述第n态进行编程的失败比特数与目标态为所述第n态的比特数的比值小于第一预设比值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n+1态；
    当对所述第n态进行编程的失败比特数与目标态为所述第n态的比特数的比值大于或等于所述第一预设比值时，确定所述第i+1编程验证操作需要验证的最低编程态为第n态。
  12. 根据权利要求10所述的方法，其中，所述第i计数结果包括：所述第i编程操作中对所述第n+k态进行编程的失败比特数；
    所述根据所述第i计数结果，确定第i+1编程验证操作需要验证的编程态范围，包括：
    当对所述第n+k态进行编程的成功比特数大于第二预设值，且所述第n+k态小于所述存储器的最高编程态时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
    当对所述第n+k态进行编程的成功比特数小于或等于所述第二预设值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k态；
    或者，
    当对所述第n+k态进行编程的成功比特数与目标态为所述第n+k态的比特数的比值大于第二预设比值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k+1态；
    当对所述第n+k态进行编程的成功比特数与目标态为所述第n+k态的比特数的比值小于或等于所述第二预设比值时，确定所述第i+1编程验证操作需要验证的最高编程态为第n+k态。
  13. 根据权利要求10所述的方法，其中，所述根据第i编程验证操作的第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，对第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得第i计数结果，包括：
    对所述第i验证结果中的第n态的验证子结果以及第n+k态的验证子结果分别进行抽样，获得所述第n态的第i抽样样本数据和第n+k态的第i抽样样本数据；
    根据所述第n态的第i抽样样本数据和第n+k态的第i抽样样本数据，对所述第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得所述第i计数结果。
  14. 一种存储器，包括：
    存储器单元阵列，所述存储器单元阵列包括多个存储器单元行；
    多个字线，所述多个字线分别耦合到所述多个存储器单元行；以及
    外围电路，所述外围电路耦合到所述多个字线并且被配置为对所述多个存储器单元行中的选定存储器单元行执行编程验证操作，所述选定存储器单元行 耦合到选定字线，其中，为了执行所述编程验证操作，所述外围电路被配置为：
    获取第i编程验证操作的第i验证结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
    根据所述第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，确定第i+1编程验证操作需要验证的编程态范围；
    根据确定的所述第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
  15. 一种存储器，包括：
    存储器单元阵列，所述存储器单元阵列包括多个存储器单元行；
    多个字线，所述多个字线分别耦合到所述多个存储器单元行；以及
    外围电路，所述外围电路耦合到所述多个字线并且被配置为对所述多个存储器单元行中的选定存储器单元行执行编程操作，所述选定存储器单元行耦合到选定字线，其中，为了执行所述编程操作，所述外围电路被配置为：
    对所述存储器的待编程存储单元施加第i+1编程脉冲；
    在施加所述第i+1编程脉冲的过程中，根据第i编程验证操作的第i验证结果中第n态的验证子结果以及第n+k态的验证子结果，对第i编程操作中第n态的编程和第n+k态的编程进行失败比特数计数，获得第i计数结果；其中，所述第i编程验证操作验证的编程态范围为第n态至第n+k态，i和n为正整数，k为自然数，且第n+k态小于或等于所述存储器的最高编程态；
    根据所述第i计数结果，确定第i+1编程验证操作需要验证的编程态范围；
    根据确定的所述第i+1编程验证操作需要验证的编程态范围，执行第i+1编程验证操作。
  16. 一种存储器系统，包括：
    一个或多个如权利要求14或15所述的存储器；
    耦合到所述存储器并且被配置为控制所述存储器的存储器控制器。
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