JP4749714B2 - 不揮発性セルを備えたeprom - Google Patents
不揮発性セルを備えたeprom Download PDFInfo
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- JP4749714B2 JP4749714B2 JP2004519081A JP2004519081A JP4749714B2 JP 4749714 B2 JP4749714 B2 JP 4749714B2 JP 2004519081 A JP2004519081 A JP 2004519081A JP 2004519081 A JP2004519081 A JP 2004519081A JP 4749714 B2 JP4749714 B2 JP 4749714B2
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- 239000003990 capacitor Substances 0.000 claims abstract description 13
- 230000000295 complement effect Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 30
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000004973 liquid crystal related substance Substances 0.000 claims description 3
- 210000004027 cell Anatomy 0.000 description 56
- 230000008569 process Effects 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/045—Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/10—Floating gate memory cells with a single polysilicon layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Medicines Containing Material From Animals Or Micro-Organisms (AREA)
- Immobilizing And Processing Of Enzymes And Microorganisms (AREA)
- Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
Description
Claims (8)
- ソースとドレインとゲートとを有する第一のトランジスタと、
フローティングゲートと制御ゲートとを有し、前記フローティングゲートが前記第一のトランジスタの前記ゲートに接続されているフローティングキャパシタと、
セルが消去又は書き込みされたかの状態を検知する手段とを有する不揮発性セルを備えたEPROMであって、
前記セルの状態を検知する手段はソースとドレインとゲートとを有する第二のトランジスタを備え、該第二のトランジスタは前記第一のトランジスタと相補的であり、前記第二のトランジスタの前記ゲートが前記フローティングゲートに接続されており、
前記第一のトランジスタに第一のドレイン電圧が与えられ、前記フローティングキャパシタの前記制御ゲートに第一の制御電圧が与えられ、前記第二のトランジスタの前記ドレインがフローティングとされ、前記第一のトランジスタの前記ソースが第一の固定電位に接続され、そして、前記第二のトランジスタの前記ソースが第二の固定電位に接続されて、前記セルが書き込み状態とされ、
前記第二のトランジスタに第二のドレイン電圧が与えられ、前記フローティングキャパシタの前記制御ゲートに第二の制御電圧が与えられ、前記第一のトランジスタの前記ドレインがフローティングとされ、前記第一のトランジスタの前記ソースが前記第一の固定電位に接続され、そして、前記第二のトランジスタの前記ソースが前記第二の固定電位に接続されて、前記セルが読み出し状態とされることを特徴とするEPROM。 - 前記第一のトランジスタはnチャネルトランジスタであり、前記第二のトランジスタはpチャネルトランジスタであることを特徴とする請求項1に記載のEPROM。
- 前記第一及び第二のトランジスタはMOSFETトランジスタであることを特徴とする請求項2に記載のEPROM。
- 前記pチャネルトランジスタのnウエル拡散領域は前記フローティングキャパシタの前記制御ゲートであることを特徴とする請求項1乃至3いずれかに記載のEPROM。
- 請求項1乃至4いずれかに記載のEPROMを備えた液晶表示装置。
- 請求項1乃至4いずれかに記載のEPROMを備えた携帯電話、計算機、ポケットベル等のバッテリ駆動携帯機器。
- 集積回路の電気的パラメータを校正するための請求項1乃至4いずれかに記載のEPROMの使用。
- 不揮発性セルを備えたEPROMの動作方法であって、
前記セルは、
ソースとドレインとゲートとを有する第一のトランジスタと、
フローティングゲートと制御ゲートとを有し、前記フローティングゲートが前記第一のトランジスタの前記ゲートに接続されているフローティングキャパシタと、
ソースとドレインとゲートとを有する第二のトランジスタであって、該第二のトランジスタは前記第一のトランジスタと相補的であり、前記第二のトランジスタの前記ゲートが前記フローティングゲートに接続されている、第二のトランジスタを備え、
前記第一のトランジスタに第一のドレイン電圧を与え、前記フローティングキャパシタの前記制御ゲートに第一の制御電圧を与え、前記第二のトランジスタの前記ドレインをフローティングにし、前記第一のトランジスタの前記ソースを第一の固定電位に接続し、そして、前記第二のトランジスタの前記ソースを第二の固定電位に接続して、前記セルを書き込み状態とし、
前記第二のトランジスタに第二のドレイン電圧を与え、前記フローティングキャパシタの前記制御ゲートに第二の制御電圧を与え、前記第一のトランジスタの前記ドレインをフローティングとし、前記第一のトランジスタの前記ソースを前記第一の固定電位に接続し、そして、前記第二のトランジスタの前記ソースを前記第二の固定電位に接続して、前記セル読み出し状態とすることを特徴とする方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02015181.7 | 2002-07-08 | ||
EP02015181 | 2002-07-08 | ||
PCT/IB2003/002807 WO2004006264A2 (en) | 2002-07-08 | 2003-06-25 | Erasable and programmable non-volatile cell |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005532684A JP2005532684A (ja) | 2005-10-27 |
JP4749714B2 true JP4749714B2 (ja) | 2011-08-17 |
Family
ID=30011062
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004519081A Expired - Fee Related JP4749714B2 (ja) | 2002-07-08 | 2003-06-25 | 不揮発性セルを備えたeprom |
Country Status (8)
Country | Link |
---|---|
US (1) | US7289362B2 (ja) |
EP (1) | EP1522078B1 (ja) |
JP (1) | JP4749714B2 (ja) |
CN (1) | CN100431050C (ja) |
AT (1) | ATE371933T1 (ja) |
AU (1) | AU2003242913A1 (ja) |
DE (1) | DE60315985T2 (ja) |
WO (1) | WO2004006264A2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4889268B2 (ja) * | 2005-09-22 | 2012-03-07 | ルネサスエレクトロニクス株式会社 | Eepromとeepromの駆動方法 |
FR2904464A1 (fr) * | 2006-07-27 | 2008-02-01 | St Microelectronics Sa | Circuit eeprom de retention de charges pour mesure temporelle |
DE602007007219D1 (de) * | 2006-07-27 | 2010-07-29 | St Microelectronics Sa | Selements zur zeitmessung |
US8331203B2 (en) * | 2006-07-27 | 2012-12-11 | Stmicroelectronics S.A. | Charge retention circuit for a time measurement |
FR2904463A1 (fr) * | 2006-07-27 | 2008-02-01 | St Microelectronics Sa | Programmation d'un circuit de retention de charges pour mesure temporelle |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03179780A (ja) * | 1989-12-07 | 1991-08-05 | Fujitsu Ltd | 半導体装置 |
JPH0685275A (ja) * | 1990-12-31 | 1994-03-25 | Sgs Thomson Microelettronica Spa | プログラム回路に向かうインターフェイスから分離された外部回路に向かうインターフェイスを有する単一金属レベルのゲートを有するeepromセル |
JPH10335505A (ja) * | 1997-05-09 | 1998-12-18 | Motorola Inc | 単一レベル・ゲート不揮発性メモリ素子およびそのアクセス方法 |
JP2001298100A (ja) * | 2000-02-01 | 2001-10-26 | Semiconductor Energy Lab Co Ltd | 不揮発性メモリ、半導体装置、およびその作製方法 |
EP1306854A1 (en) * | 2001-10-29 | 2003-05-02 | Dialog Semiconductor GmbH | Floating gate programmable cell array for standard CMOS |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5247478A (en) * | 1992-03-06 | 1993-09-21 | Altera Corporation | Programmable transfer-devices |
US5615150A (en) * | 1995-11-02 | 1997-03-25 | Advanced Micro Devices, Inc. | Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors |
US5646901A (en) * | 1996-03-26 | 1997-07-08 | Advanced Micro Devices, Inc. | CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors |
US5838040A (en) * | 1997-03-31 | 1998-11-17 | Gatefield Corporation | Nonvolatile reprogrammable interconnect cell with FN tunneling in sense |
JP4000654B2 (ja) * | 1997-02-27 | 2007-10-31 | セイコーエプソン株式会社 | 半導体装置及び電子機器 |
WO1998047151A1 (en) * | 1997-04-11 | 1998-10-22 | Programmable Silicon Solutions | Electrically erasable nonvolatile memory |
US5933732A (en) * | 1997-05-07 | 1999-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nonvolatile devices with P-channel EEPROM devices as injector |
US6816154B2 (en) * | 2001-05-30 | 2004-11-09 | Palmone, Inc. | Optical sensor based user interface for a portable electronic device |
-
2003
- 2003-06-25 DE DE60315985T patent/DE60315985T2/de not_active Expired - Lifetime
- 2003-06-25 AT AT03762837T patent/ATE371933T1/de not_active IP Right Cessation
- 2003-06-25 WO PCT/IB2003/002807 patent/WO2004006264A2/en active IP Right Grant
- 2003-06-25 CN CNB038161680A patent/CN100431050C/zh not_active Expired - Fee Related
- 2003-06-25 JP JP2004519081A patent/JP4749714B2/ja not_active Expired - Fee Related
- 2003-06-25 US US10/520,340 patent/US7289362B2/en not_active Expired - Fee Related
- 2003-06-25 AU AU2003242913A patent/AU2003242913A1/en not_active Abandoned
- 2003-06-25 EP EP03762837A patent/EP1522078B1/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03179780A (ja) * | 1989-12-07 | 1991-08-05 | Fujitsu Ltd | 半導体装置 |
JPH0685275A (ja) * | 1990-12-31 | 1994-03-25 | Sgs Thomson Microelettronica Spa | プログラム回路に向かうインターフェイスから分離された外部回路に向かうインターフェイスを有する単一金属レベルのゲートを有するeepromセル |
JPH10335505A (ja) * | 1997-05-09 | 1998-12-18 | Motorola Inc | 単一レベル・ゲート不揮発性メモリ素子およびそのアクセス方法 |
JP2001298100A (ja) * | 2000-02-01 | 2001-10-26 | Semiconductor Energy Lab Co Ltd | 不揮発性メモリ、半導体装置、およびその作製方法 |
EP1306854A1 (en) * | 2001-10-29 | 2003-05-02 | Dialog Semiconductor GmbH | Floating gate programmable cell array for standard CMOS |
Also Published As
Publication number | Publication date |
---|---|
DE60315985D1 (de) | 2007-10-11 |
EP1522078A2 (en) | 2005-04-13 |
AU2003242913A1 (en) | 2004-01-23 |
JP2005532684A (ja) | 2005-10-27 |
EP1522078B1 (en) | 2007-08-29 |
CN1666295A (zh) | 2005-09-07 |
DE60315985T2 (de) | 2008-05-21 |
CN100431050C (zh) | 2008-11-05 |
ATE371933T1 (de) | 2007-09-15 |
WO2004006264A2 (en) | 2004-01-15 |
WO2004006264A3 (en) | 2004-03-18 |
US7289362B2 (en) | 2007-10-30 |
US20050259488A1 (en) | 2005-11-24 |
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