JP4669246B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP4669246B2 JP4669246B2 JP2004236770A JP2004236770A JP4669246B2 JP 4669246 B2 JP4669246 B2 JP 4669246B2 JP 2004236770 A JP2004236770 A JP 2004236770A JP 2004236770 A JP2004236770 A JP 2004236770A JP 4669246 B2 JP4669246 B2 JP 4669246B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
表層に導電層が設けられた半導体基板と、
前記半導体基板の表面のうち平坦な部分上に設けられた容量膜と、
前記容量膜上に設けられ、前記容量膜を挟んで対向する前記導電層との間で容量素子を構成する上部電極と、
前記半導体基板に設けられたトランジスタと、
前記トランジスタ上に設けられた層間窒化膜と、
前記層間窒化膜上に設けられた絶縁膜と、を備え、
前記容量膜は、前記トランジスタのゲート絶縁膜に比して厚く、
前記絶縁膜は、前記容量膜と一体となって設けられている、半導体装置が提供される。
半導体基板に、不純物を導入して形成される不純物拡散層を形成する導電層形成工程と、
前記半導体基板上にトランジスタを形成する工程と、
前記トランジスタ上に層間窒化膜を形成する工程と、
前記層間窒化膜上、および前記導電層が形成された前記半導体基板の表面のうち平坦な部分上に容量膜を形成する容量膜形成工程と、
前記容量膜上に、前記容量膜を挟んで対向する前記導電層との間で容量素子を構成する上部電極を形成する電極形成工程と、をこの順番で含み、
前記容量膜は、前記トランジスタのゲート絶縁膜に比して厚く形成されている、半導体装置の製造方法が提供される。
1a 半導体装置
1b 半導体装置
10 半導体基板
20 容量素子形成領域
22 N型ウエル
23 拡散層
24,25 容量膜
24a 金属元素拡散防止膜
26,27 上部電極
30 トランジスタ形成領域
32 P型ウエル
34 ソース・ドレイン領域
36 ゲート絶縁膜
38 ゲート電極
40 サイドウォール
42 層間窒化膜
44 絶縁膜
52,54,56,58 コンタクト
60 層間絶縁膜
72 シリサイドブロック
74,76 レジスト
62,64,66,68 STI
Claims (7)
- 表層に導電層が設けられた半導体基板と、
前記半導体基板の表面のうち平坦な部分上に設けられた容量膜と、
前記容量膜上に設けられ、前記容量膜を挟んで対向する前記導電層との間で容量素子を構成する上部電極と、
前記半導体基板に設けられたトランジスタと、
前記トランジスタ上に設けられた層間窒化膜と、
前記層間窒化膜上に設けられた絶縁膜と、を備え、
前記容量膜は、前記トランジスタのゲート絶縁膜に比して厚く、
前記絶縁膜は、前記容量膜と一体となって設けられている、半導体装置。 - 請求項1に記載の半導体装置において、
前記容量膜は、前記半導体基板側の表層に設けられた、金属元素の拡散を防止する絶縁膜を有する、半導体装置。 - 請求項1または2に記載の半導体装置において、
前記容量膜は、シリコン酸化膜よりも高い誘電率をもつ高誘電率膜である、半導体装置。 - 請求項1から3の何れか一項に記載の半導体装置において、
前記容量膜は、前記トランジスタのゲート絶縁膜に比して電気的換算膜厚が薄い、半導体装置。 - 請求項1から4の何れか一項に記載の半導体装置において、
前記半導体基板における前記容量膜が設けられている部分は、シリサイド化されていない、半導体装置。 - 半導体基板に、不純物を導入して形成される不純物拡散層を形成する導電層形成工程と、
前記半導体基板上にトランジスタを形成する工程と、
前記トランジスタ上に層間窒化膜を形成する工程と、
前記層間窒化膜上、および前記導電層が形成された前記半導体基板の表面のうち平坦な部分上に容量膜を形成する容量膜形成工程と、
前記容量膜上に、前記容量膜を挟んで対向する前記導電層との間で容量素子を構成する上部電極を形成する電極形成工程と、をこの順番で含み、
前記容量膜は、前記トランジスタのゲート絶縁膜に比して厚く形成されている、半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記半導体基板は、トランジスタ形成領域と容量素子形成領域とを有し、
前記トランジスタ形成領域に前記トランジスタを形成する工程と、
前記容量素子形成領域にシリサイドブロックを形成するシリサイドブロック形成工程と、をこの順番で含み、
前記トランジスタを形成する前記工程および前記シリサイドブロック形成工程よりも後に、前記半導体基板の表面における前記シリサイドブロックが形成されていない部分をシリサイド化するシリサイド工程を行い、
前記シリサイド工程よりも後に前記シリサイドブロックを除去するシリサイドブロック除去工程を行い、
前記容量膜形成工程は、前記シリサイドブロック除去工程よりも後に実行される、半導体装置の製造方法。
Priority Applications (2)
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JP2004236770A JP4669246B2 (ja) | 2004-08-16 | 2004-08-16 | 半導体装置およびその製造方法 |
US11/204,163 US7498626B2 (en) | 2004-08-16 | 2005-08-16 | Semiconductor device and method of manufacturing the same |
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JP2004236770A JP4669246B2 (ja) | 2004-08-16 | 2004-08-16 | 半導体装置およびその製造方法 |
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JP2006054402A JP2006054402A (ja) | 2006-02-23 |
JP4669246B2 true JP4669246B2 (ja) | 2011-04-13 |
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JP (1) | JP4669246B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US20070141776A1 (en) * | 2005-12-19 | 2007-06-21 | Jung-Ching Chen | Semiconductor device having capacitor and fabricating method thereof |
JP2011138885A (ja) * | 2009-12-28 | 2011-07-14 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US9412883B2 (en) | 2011-11-22 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for MOS capacitors in replacement gate process |
CN104752422B (zh) * | 2013-12-30 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
US10418364B2 (en) * | 2016-08-31 | 2019-09-17 | Globalfoundries Inc. | Semiconductor device structure with self-aligned capacitor device |
US10680120B2 (en) * | 2018-04-05 | 2020-06-09 | Vanguard International Semiconductor Corporation | Semiconductor device and method for manufacturing the same |
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JPH06291262A (ja) * | 1993-03-31 | 1994-10-18 | Sony Corp | 半導体装置の製造方法 |
JP2000124336A (ja) * | 1998-10-12 | 2000-04-28 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
JP2000174216A (ja) * | 1998-10-02 | 2000-06-23 | Sony Corp | 半導体装置の製造方法 |
JP2001308274A (ja) * | 2000-04-24 | 2001-11-02 | Nec Corp | 電圧履歴記録素子およびそれを用いた電子デバイスの印加電圧履歴記録方法 |
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- 2004-08-16 JP JP2004236770A patent/JP4669246B2/ja active Active
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- 2005-08-16 US US11/204,163 patent/US7498626B2/en active Active
Patent Citations (9)
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JPH01222468A (ja) * | 1988-03-02 | 1989-09-05 | Toshiba Corp | 半導体装置用キャパシタ |
JPH05259115A (ja) * | 1992-03-11 | 1993-10-08 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH06291262A (ja) * | 1993-03-31 | 1994-10-18 | Sony Corp | 半導体装置の製造方法 |
JP2000174216A (ja) * | 1998-10-02 | 2000-06-23 | Sony Corp | 半導体装置の製造方法 |
JP2000124336A (ja) * | 1998-10-12 | 2000-04-28 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
JP2001308274A (ja) * | 2000-04-24 | 2001-11-02 | Nec Corp | 電圧履歴記録素子およびそれを用いた電子デバイスの印加電圧履歴記録方法 |
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JP2003158197A (ja) * | 2001-11-22 | 2003-05-30 | Sony Corp | 半導体装置の製造方法 |
WO2004021440A1 (en) * | 2002-09-02 | 2004-03-11 | Advanced Micro Devices, Inc. | Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area |
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JP2006054402A (ja) | 2006-02-23 |
US7498626B2 (en) | 2009-03-03 |
US20060033139A1 (en) | 2006-02-16 |
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