JP4668729B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP4668729B2
JP4668729B2 JP2005236591A JP2005236591A JP4668729B2 JP 4668729 B2 JP4668729 B2 JP 4668729B2 JP 2005236591 A JP2005236591 A JP 2005236591A JP 2005236591 A JP2005236591 A JP 2005236591A JP 4668729 B2 JP4668729 B2 JP 4668729B2
Authority
JP
Japan
Prior art keywords
tab
semiconductor chip
frame
resin
die attach
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005236591A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007053195A (ja
JP2007053195A5 (enExample
Inventor
洋一 河田
敏弘 塩月
光一 金本
真由美 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2005236591A priority Critical patent/JP4668729B2/ja
Publication of JP2007053195A publication Critical patent/JP2007053195A/ja
Publication of JP2007053195A5 publication Critical patent/JP2007053195A5/ja
Application granted granted Critical
Publication of JP4668729B2 publication Critical patent/JP4668729B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP2005236591A 2005-08-17 2005-08-17 半導体装置の製造方法 Expired - Fee Related JP4668729B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005236591A JP4668729B2 (ja) 2005-08-17 2005-08-17 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005236591A JP4668729B2 (ja) 2005-08-17 2005-08-17 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2007053195A JP2007053195A (ja) 2007-03-01
JP2007053195A5 JP2007053195A5 (enExample) 2008-10-02
JP4668729B2 true JP4668729B2 (ja) 2011-04-13

Family

ID=37917443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005236591A Expired - Fee Related JP4668729B2 (ja) 2005-08-17 2005-08-17 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP4668729B2 (enExample)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6215844A (ja) * 1985-07-15 1987-01-24 Hitachi Ltd 半導体リ−ドフレ−ム
JPS63248155A (ja) * 1987-04-03 1988-10-14 Mitsubishi Electric Corp 半導体装置
US5233222A (en) * 1992-07-27 1993-08-03 Motorola, Inc. Semiconductor device having window-frame flag with tapered edge in opening
JPH06236899A (ja) * 1992-09-29 1994-08-23 Toshiba Corp 樹脂封止型半導体装置
JPH06268146A (ja) * 1993-03-15 1994-09-22 Toshiba Corp 半導体装置
JPH10303352A (ja) * 1997-04-22 1998-11-13 Toshiba Corp 半導体装置および半導体装置の製造方法
JP3605651B2 (ja) * 1998-09-30 2004-12-22 日立化成工業株式会社 半導体装置の製造方法
JP3062691B1 (ja) * 1999-02-26 2000-07-12 株式会社三井ハイテック 半導体装置
JP3895570B2 (ja) * 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
JP2003332522A (ja) * 2002-05-17 2003-11-21 Mitsubishi Electric Corp 半導体装置
JP2005203401A (ja) * 2004-01-13 2005-07-28 Sumitomo Bakelite Co Ltd 半導体装置の製造方法および半導体装置

Also Published As

Publication number Publication date
JP2007053195A (ja) 2007-03-01

Similar Documents

Publication Publication Date Title
KR100551641B1 (ko) 반도체 장치의 제조 방법 및 반도체 장치
CN102420217B (zh) 多芯片半导体封装体及其组装
JP2520575B2 (ja) 集積回路チップ・パッケ―ジを基板の表面に電気的に且つ機械的に接続する弾力性リ―ド及びこれの製造方法
JP3238004B2 (ja) 半導体装置の製造方法
US8810016B2 (en) Semiconductor device, substrate and semiconductor device manufacturing method
JP2001015679A (ja) 半導体装置及びその製造方法
CN101162712A (zh) 半导体装置及其制造方法
US20110241187A1 (en) Lead frame with recessed die bond area
JP5100967B2 (ja) リードフレーム、これを利用した半導体チップパッケージ及びその製造方法
US10269583B2 (en) Semiconductor die attachment with embedded stud bumps in attachment material
US20080135990A1 (en) Stress-improved flip-chip semiconductor device having half-etched leadframe
KR100825784B1 (ko) 휨 및 와이어 단선을 억제하는 반도체 패키지 및 그제조방법
JP3847602B2 (ja) 積層型半導体装置及びその製造方法並びに半導体装置搭載マザーボード及び半導体装置搭載マザーボードの製造方法
KR20120018756A (ko) Ｉｃ 패키지용 리드프레임 및 제조방법
JP4668729B2 (ja) 半導体装置の製造方法
JP3682468B2 (ja) 半導体集積回路装置
CN119028830B (zh) 引线框制作工艺及引线框
WO2015129185A1 (ja) 樹脂封止型半導体装置、およびその製造方法、ならびにその実装体
US6278183B1 (en) Semiconductor device and method for manufacturing the same
KR20090069382A (ko) 반도체 패키지
EP3024025A1 (en) Die arrangement
KR100608331B1 (ko) 멀티 칩 패키지
JP2004172647A (ja) 半導体装置
JP2007073763A (ja) 半導体装置およびその製造方法
JP2017092212A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080808

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080808

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100528

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100929

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101005

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101203

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101228

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110113

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140121

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4668729

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees