JP4649257B2 - マルチｃｐｕシステム - Google Patents

マルチｃｐｕシステム Download PDF

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Publication number
JP4649257B2
JP4649257B2 JP2005107921A JP2005107921A JP4649257B2 JP 4649257 B2 JP4649257 B2 JP 4649257B2 JP 2005107921 A JP2005107921 A JP 2005107921A JP 2005107921 A JP2005107921 A JP 2005107921A JP 4649257 B2 JP4649257 B2 JP 4649257B2
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JP
Japan
Prior art keywords
cpu
semaphore
bus
access
bus bridge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005107921A
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English (en)
Japanese (ja)
Other versions
JP2006285872A (ja
JP2006285872A5 (enExample
Inventor
勝也 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2005107921A priority Critical patent/JP4649257B2/ja
Priority to US11/397,485 priority patent/US7472212B2/en
Publication of JP2006285872A publication Critical patent/JP2006285872A/ja
Publication of JP2006285872A5 publication Critical patent/JP2006285872A5/ja
Application granted granted Critical
Publication of JP4649257B2 publication Critical patent/JP4649257B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
JP2005107921A 2005-04-04 2005-04-04 マルチｃｐｕシステム Expired - Fee Related JP4649257B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005107921A JP4649257B2 (ja) 2005-04-04 2005-04-04 マルチｃｐｕシステム
US11/397,485 US7472212B2 (en) 2005-04-04 2006-04-04 Multi CPU system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005107921A JP4649257B2 (ja) 2005-04-04 2005-04-04 マルチｃｐｕシステム

Publications (3)

Publication Number Publication Date
JP2006285872A JP2006285872A (ja) 2006-10-19
JP2006285872A5 JP2006285872A5 (enExample) 2010-04-22
JP4649257B2 true JP4649257B2 (ja) 2011-03-09

Family

ID=37071962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005107921A Expired - Fee Related JP4649257B2 (ja) 2005-04-04 2005-04-04 マルチｃｐｕシステム

Country Status (2)

Country Link
US (1) US7472212B2 (enExample)
JP (1) JP4649257B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8850250B2 (en) 2010-06-01 2014-09-30 Intel Corporation Integration of processor and input/output hub
US8782456B2 (en) 2010-06-01 2014-07-15 Intel Corporation Dynamic and idle power reduction sequence using recombinant clock and power gating
US9146610B2 (en) 2010-09-25 2015-09-29 Intel Corporation Throttling integrated link
CN117971763A (zh) * 2024-01-09 2024-05-03 安科讯(福建)科技有限公司 一种CPU之间的shell命令交互方法与存储介质

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4419724A (en) * 1980-04-14 1983-12-06 Sperry Corporation Main bus interface package
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4805098A (en) * 1986-05-05 1989-02-14 Mips Computer Systems, Inc. Write buffer
JPH01205362A (ja) * 1988-02-12 1989-08-17 Sanyo Electric Co Ltd バス制御装置
US5050072A (en) * 1988-06-17 1991-09-17 Modular Computer Systems, Inc. Semaphore memory to reduce common bus contention to global memory with localized semaphores in a multiprocessor system
US5167022A (en) * 1988-10-25 1992-11-24 Hewlett-Packard Company Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests
US5175829A (en) * 1988-10-25 1992-12-29 Hewlett-Packard Company Method and apparatus for bus lock during atomic computer operations
JPH0387958A (ja) * 1989-06-30 1991-04-12 Nec Corp バスロツク制御方式
JPH0374759A (ja) * 1989-08-16 1991-03-29 Toshiba Corp マルチプロセッサシステム
US5293491A (en) * 1990-12-28 1994-03-08 International Business Machines Corp. Data processing system and memory controller for lock semaphore operations
JP2825983B2 (ja) * 1991-03-08 1998-11-18 富士通株式会社 情報処理装置
JPH0520279A (ja) 1991-07-15 1993-01-29 Japan Steel Works Ltd:The データ交換方法とそれに用いる調停回路
GB9123264D0 (en) * 1991-11-01 1991-12-18 Int Computers Ltd Semaphone arrangement for a data processing system
US5469575A (en) * 1992-10-16 1995-11-21 International Business Machines Corporation Determining a winner of a race in a data processing system
TW400483B (en) * 1994-03-01 2000-08-01 Intel Corp High performance symmetric arbitration protocol with support for I/O requirements
US5774731A (en) * 1995-03-22 1998-06-30 Hitachi, Ltd. Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage
US6549961B1 (en) * 1999-10-27 2003-04-15 Infineon Technologies North America Corporation Semaphore access in a multiprocessor system
JP2003050789A (ja) * 2001-08-07 2003-02-21 Fujitsu Ltd 回路、プロセッサ、及びマルチプロセッサシステム
JP2006119724A (ja) * 2004-10-19 2006-05-11 Canon Inc Ｃｐｕシステム、バスブリッジ、その制御方法、及びコンピュータシステム

Also Published As

Publication number Publication date
US20060224806A1 (en) 2006-10-05
JP2006285872A (ja) 2006-10-19
US7472212B2 (en) 2008-12-30

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