JP4608392B2 - 物理的設計システム及び方法 - Google Patents

物理的設計システム及び方法 Download PDF

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JP4608392B2
JP4608392B2 JP2005233945A JP2005233945A JP4608392B2 JP 4608392 B2 JP4608392 B2 JP 4608392B2 JP 2005233945 A JP2005233945 A JP 2005233945A JP 2005233945 A JP2005233945 A JP 2005233945A JP 4608392 B2 JP4608392 B2 JP 4608392B2
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design
pattern
glyph
grid
unit
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JP2006059348A (ja
JP2006059348A5 (enExample
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ジョン・エム・コーン
ジェームス・エイ・カルプ
ウルリケ・エイ・フィンクラー
フー・リエン・ヘン
マーク・エイ・ラビン
ジン・フー・リー
ラース・ダブリュ・リーブマン
グレゴリー・エイ・ノースロップ
ナクゲオン・ソン
ラマ・エヌ・シン
レオン・シュトック
ピーター・ジェイ・ボルトゲン
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2005233945A 2004-08-12 2005-08-12 物理的設計システム及び方法 Expired - Fee Related JP4608392B2 (ja)

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US10/917,193 US7536664B2 (en) 2004-08-12 2004-08-12 Physical design system and method

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JP2006059348A JP2006059348A (ja) 2006-03-02
JP2006059348A5 JP2006059348A5 (enExample) 2008-07-24
JP4608392B2 true JP4608392B2 (ja) 2011-01-12

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JP (1) JP4608392B2 (enExample)
CN (1) CN100570855C (enExample)
TW (1) TWI349864B (enExample)

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7400167B2 (en) * 2005-08-16 2008-07-15 Altera Corporation Apparatus and methods for optimizing the performance of programmable logic devices
US7536664B2 (en) * 2004-08-12 2009-05-19 International Business Machines Corporation Physical design system and method
US7458045B2 (en) * 2004-10-29 2008-11-25 Synopsys, Inc. Silicon tolerance specification using shapes as design intent markers
US7302651B2 (en) * 2004-10-29 2007-11-27 International Business Machines Corporation Technology migration for integrated circuits with radical design restrictions
WO2006063147A2 (en) * 2004-12-08 2006-06-15 Kenneth Robert Hepp Software system for automated design in multi-step sheet metal forming
US7657852B2 (en) * 2005-08-16 2010-02-02 Pulsic Limited System and technique of pattern matching and pattern replacement
US7624343B2 (en) * 2005-09-16 2009-11-24 Microsoft Corporation Performance optimization for text layout processing
US7712068B2 (en) * 2006-02-17 2010-05-04 Zhuoxiang Ren Computation of electrical properties of an IC layout
WO2008015111A2 (en) * 2006-08-04 2008-02-07 Sagantec Israel Ltd Method and system for adapting a circuit layout to a predefined grid
US20080168410A1 (en) * 2006-10-09 2008-07-10 Mentor Graphics Corporation Properties In Electronic Design Automation
US7814443B2 (en) * 2007-01-16 2010-10-12 International Business Machines Corporation Graph-based pattern matching in L3GO designs
JP4335933B2 (ja) * 2007-03-22 2009-09-30 Ｎｅｃエレクトロニクス株式会社 半導体集積回路及び半導体集積回路の設計プログラム
US7765020B2 (en) * 2007-05-04 2010-07-27 Applied Materials, Inc. Graphical user interface for presenting multivariate fault contributions
US8042070B2 (en) 2007-10-23 2011-10-18 International Business Machines Corporation Methods and system for analysis and management of parametric yield
US7873936B2 (en) * 2008-01-04 2011-01-18 International Business Machines Corporation Method for quantifying the manufactoring complexity of electrical designs
US20090187867A1 (en) * 2008-01-22 2009-07-23 Lawrence Jay A Techniques for Verifying Error Detection of a Design Rule Checking Runset
US7900178B2 (en) * 2008-02-28 2011-03-01 International Business Machines Corporation Integrated circuit (IC) design method, system and program product
US8423947B2 (en) * 2008-03-13 2013-04-16 International Business Machines Corporation Gridded glyph geometric objects (L3GO) design method
US8051391B2 (en) * 2008-08-04 2011-11-01 Texas Instruments Incorporated Method for layout of random via arrays in the presence of strong pitch restrictions
US9341936B2 (en) 2008-09-01 2016-05-17 D2S, Inc. Method and system for forming a pattern on a reticle using charged particle beam lithography
US7901850B2 (en) 2008-09-01 2011-03-08 D2S, Inc. Method and system for design of a reticle to be manufactured using variable shaped beam lithography
US8669023B2 (en) 2008-09-01 2014-03-11 D2S, Inc. Method for optical proximity correction of a reticle to be manufactured using shaped beam lithography
US8057970B2 (en) 2008-09-01 2011-11-15 D2S, Inc. Method and system for forming circular patterns on a surface
US7799489B2 (en) * 2008-09-01 2010-09-21 D2S, Inc. Method for design and manufacture of a reticle using variable shaped beam lithography
US20120219886A1 (en) 2011-02-28 2012-08-30 D2S, Inc. Method and system for forming patterns using charged particle beam lithography with variable pattern dosage
US9323140B2 (en) 2008-09-01 2016-04-26 D2S, Inc. Method and system for forming a pattern on a reticle using charged particle beam lithography
US8039176B2 (en) 2009-08-26 2011-10-18 D2S, Inc. Method for fracturing and forming a pattern using curvilinear characters with charged particle beam lithography
GB0818308D0 (en) * 2008-10-07 2008-11-12 Helic S A Expert system-based integrated inductor synthesis and optimization
US8443322B2 (en) * 2009-03-19 2013-05-14 International Business Machines Corporation Using layout enumeration to facilitate integrated circuit development
US20120278770A1 (en) 2011-04-26 2012-11-01 D2S, Inc. Method and system for forming non-manhattan patterns using variable shaped beam lithography
US9164372B2 (en) 2009-08-26 2015-10-20 D2S, Inc. Method and system for forming non-manhattan patterns using variable shaped beam lithography
US9448473B2 (en) 2009-08-26 2016-09-20 D2S, Inc. Method for fracturing and forming a pattern using shaped beam charged particle beam lithography
US8912012B2 (en) 2009-11-25 2014-12-16 Qualcomm Incorporated Magnetic tunnel junction device and fabrication
US8458635B2 (en) * 2009-12-04 2013-06-04 Synopsys, Inc. Convolution computation for many-core processor architectures
US8543958B2 (en) * 2009-12-11 2013-09-24 Synopsys, Inc. Optical proximity correction aware integrated circuit design optimization
US8775979B2 (en) * 2010-01-30 2014-07-08 Synopsys. Inc. Failure analysis using design rules
US8631379B2 (en) * 2010-02-09 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Decomposing integrated circuit layout
FR2960992B1 (fr) * 2010-06-02 2013-05-10 St Microelectronics Rousset Procede de conception de masques pour la formation de composants electroniques
US9033253B2 (en) * 2010-07-28 2015-05-19 Hewlett-Packard Development Company, L.P. Designer-adaptive visual codes
CN102479273A (zh) * 2010-11-26 2012-05-30 英业达股份有限公司 布局侦错方法
US9165403B2 (en) * 2011-01-14 2015-10-20 Intel Corporation Planetary scale object rendering
US9057956B2 (en) * 2011-02-28 2015-06-16 D2S, Inc. Method and system for design of enhanced edge slope patterns for charged particle beam lithography
US9612530B2 (en) 2011-02-28 2017-04-04 D2S, Inc. Method and system for design of enhanced edge slope patterns for charged particle beam lithography
US9034542B2 (en) 2011-06-25 2015-05-19 D2S, Inc. Method and system for forming patterns with charged particle beam lithography
CN102890730B (zh) * 2011-07-20 2016-08-10 清华大学 一种集成电路版图验证中矩形包含规则的验证方法
US8719739B2 (en) 2011-09-19 2014-05-06 D2S, Inc. Method and system for forming patterns using charged particle beam lithography
US9152039B2 (en) * 2011-10-18 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple patterning technology method and system for achieving minimal pattern mismatch
US8769475B2 (en) 2011-10-31 2014-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method, system and software for accessing design rules and library of design features while designing semiconductor device layout
TWI574136B (zh) * 2012-02-03 2017-03-11 應用材料以色列公司 基於設計之缺陷分類之方法及系統
US9117052B1 (en) 2012-04-12 2015-08-25 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns
US9003349B1 (en) 2013-06-28 2015-04-07 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks
US9251299B1 (en) 2013-06-28 2016-02-02 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs
US9343267B2 (en) 2012-04-18 2016-05-17 D2S, Inc. Method and system for dimensional uniformity using charged particle beam lithography
US9720792B2 (en) 2012-08-28 2017-08-01 Synopsys, Inc. Information theoretic caching for dynamic problem generation in constraint solving
US11468218B2 (en) * 2012-08-28 2022-10-11 Synopsys, Inc. Information theoretic subgraph caching
US9104830B1 (en) 2013-06-28 2015-08-11 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design
US9213793B1 (en) 2012-08-31 2015-12-15 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks
US8850378B2 (en) * 2012-10-31 2014-09-30 International Business Machines Corporation Hierarchical design of integrated circuits with multi-patterning requirements
US8601419B1 (en) * 2012-11-05 2013-12-03 Synopsys, Inc. Accurate process hotspot detection using critical design rule extraction
US9690880B2 (en) 2012-11-27 2017-06-27 Autodesk, Inc. Goal-driven computer aided design workflow
CN103019729B (zh) * 2012-12-21 2017-01-25 曙光信息产业(北京)有限公司 格点转换的实现方法和装置
US9087174B1 (en) 2013-03-15 2015-07-21 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designs
US8863048B1 (en) 2013-03-15 2014-10-14 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design
US9286432B1 (en) * 2013-03-15 2016-03-15 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing correct-by-construction physical designs with multiple-patterning-awareness
US8762898B1 (en) * 2013-04-12 2014-06-24 Freescale Semiconductor, Inc. Double patterning aware routing without stitching
KR102224518B1 (ko) * 2013-06-24 2021-03-08 삼성전자주식회사 더블 패터닝 레이아웃 설계 방법
US9165103B1 (en) 2013-06-28 2015-10-20 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for tessellating and labeling routing space for routing electronic designs
US9355202B2 (en) 2013-11-05 2016-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Promoting efficient cell usage to boost QoR in automated design
US9659125B2 (en) * 2014-01-28 2017-05-23 Arm Limited Computer implemented system and method for generating a layout of a cell defining a circuit component
US10083269B2 (en) 2013-11-19 2018-09-25 Arm Limited Computer implemented system and method for generating a layout of a cell defining a circuit component
US9697313B2 (en) * 2014-09-19 2017-07-04 Synopsys, Inc. Organization for virtual-flat expansion of physical data in physically-hierarchical IC designs
US9594867B2 (en) 2014-10-30 2017-03-14 Synopsys, Inc. DRC-based hotspot detection considering edge tolerance and incomplete specification
CN105989202B (zh) * 2015-02-04 2019-04-09 中芯国际集成电路制造(上海)有限公司 一种对版图进行drc验证的方法
US9846934B2 (en) 2015-04-13 2017-12-19 Anchor Semiconductor Inc. Pattern weakness and strength detection and tracking during a semiconductor device fabrication process
US10783311B2 (en) * 2016-10-31 2020-09-22 Synopsys, Inc. DRC processing tool for early stage IC layout designs
KR102563127B1 (ko) 2018-11-26 2023-08-02 에이에스엠엘 네델란즈 비.브이. 반도체 제조 프로세스의 이벤트의 근본 원인을 결정하고 반도체 제조 프로세스를 모니터링하기 위한 방법
CN112668271A (zh) 2019-10-15 2021-04-16 台湾积体电路制造股份有限公司 集成电路器件设计方法和系统
CN120259463B (zh) * 2025-03-19 2025-11-14 西安电子科技大学广州研究院 一种基于边界跟踪扫描线算法的芯片版图图像生成方法

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0638266B2 (ja) * 1985-03-18 1994-05-18 株式会社日立製作所 設計支援方法及びその装置
US5287290A (en) * 1989-03-10 1994-02-15 Fujitsu Limited Method and apparatus for checking a mask pattern
US5416722A (en) * 1992-11-19 1995-05-16 Vlsi Technology, Inc. System and method for compacting integrated circuit layouts
US5694578A (en) * 1992-12-18 1997-12-02 Silicon Graphics, Inc. Computer-implemented method and apparatus for converting data according to a selected data transformation
JP3227056B2 (ja) * 1994-06-14 2001-11-12 富士通株式会社 図形処理方法及び図形処理装置
JP2778483B2 (ja) * 1994-09-26 1998-07-23 日本電気株式会社 デザインルール検証システム
JP3351651B2 (ja) * 1995-04-07 2002-12-03 富士通株式会社 会話型回路設計装置
US5754826A (en) * 1995-08-04 1998-05-19 Synopsys, Inc. CAD and simulation system for targeting IC designs to multiple fabrication processes
JP3934719B2 (ja) * 1995-12-22 2007-06-20 株式会社東芝 光近接効果補正方法
US5705301A (en) * 1996-02-27 1998-01-06 Lsi Logic Corporation Performing optical proximity correction with the aid of design rule checkers
JPH1092938A (ja) * 1996-09-10 1998-04-10 Fujitsu Ltd レイアウト方法、レイアウト装置、及び、データベース
JP3063828B2 (ja) * 1997-03-27 2000-07-12 日本電気株式会社 集積回路の自動概略配線方法
US6952811B1 (en) * 1998-07-30 2005-10-04 Mitsubishi Denki Kabushiki Kaisha Ladder circuit editing system
US6460166B1 (en) * 1998-12-16 2002-10-01 International Business Machines Corporation System and method for restructuring of logic circuitry
JP2000260879A (ja) * 1999-03-12 2000-09-22 Hitachi Ltd レイアウト設計支援装置、コンピュータ読み取り可能な記録媒体
JP3349989B2 (ja) * 1999-06-18 2002-11-25 エヌイーシーマイクロシステム株式会社 半導体集積回路装置及びそのレイアウト方法及び装置
JP2001014368A (ja) * 1999-06-30 2001-01-19 Mitsubishi Electric Corp クロック解析装置およびクロック解析方法
JP3372918B2 (ja) * 1999-12-21 2003-02-04 日本電気株式会社 設計支援システム及びセル配置方法
JP3805936B2 (ja) * 1999-12-28 2006-08-09 株式会社東芝 マスクパターン補正方法及びマスクパターン作成システム
US20020166104A1 (en) * 2000-12-14 2002-11-07 Yu-Liang Wu System and method for alternative wiring using pre-analyzed patterns
US6493858B2 (en) * 2001-03-23 2002-12-10 The Board Of Trustees Of The Leland Stanford Jr. University Method and system for displaying VLSI layout data
US6574779B2 (en) * 2001-04-12 2003-06-03 International Business Machines Corporation Hierarchical layout method for integrated circuits
JP2002312414A (ja) * 2001-04-13 2002-10-25 Toshiba Corp 半導体集積回路装置のレイアウト設計システム、配線設計方法、配線設計プログラム及び半導体集積回路装置の製造方法
JP4187947B2 (ja) * 2001-04-26 2008-11-26 株式会社東芝 パターン補正方法、パターン補正装置、およびパターン補正プログラムを記録した記録媒体
JP4929437B2 (ja) * 2001-08-03 2012-05-09 富士通セミコンダクター株式会社 集積回路の配線レイアウト方法
US7155698B1 (en) * 2001-09-11 2006-12-26 The Regents Of The University Of California Method of locating areas in an image such as a photo mask layout that are sensitive to residual processing effects
JP3615182B2 (ja) * 2001-11-26 2005-01-26 株式会社東芝 光近接効果補正方法及び光近接効果補正システム
US6842881B2 (en) * 2002-07-30 2005-01-11 Photronics, Inc. Rule based system and method for automatically generating photomask orders in a specified order format
JP4224541B2 (ja) * 2002-03-20 2009-02-18 富士通マイクロエレクトロニクス株式会社 自動配置配線方法、装置及びプログラム
US6735749B2 (en) * 2002-03-21 2004-05-11 Sun Microsystems, Inc. (Design rule check)/(electrical rule check) algorithms using a system resolution
US6928634B2 (en) * 2003-01-02 2005-08-09 Yuri Granik Matrix optical process correction
US6869739B1 (en) * 2003-01-28 2005-03-22 International Business Machines Corporation Integrated lithographic print and detection model for optical CD
JP2004240801A (ja) * 2003-02-07 2004-08-26 Renesas Technology Corp 半導体集積回路の寄生容量抽出装置及び寄生容量抽出方法
US7093226B2 (en) * 2003-02-28 2006-08-15 Synopsys, Inc. Method and apparatus of wafer print simulation using hybrid model with mask optical images
US7010770B2 (en) * 2003-04-04 2006-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wide wire identification
US7075532B2 (en) * 2003-05-23 2006-07-11 International Business Machines Corporation Robust tetrahedralization and triangulation method with applications in VLSI layout design and manufacturability
US6961920B2 (en) * 2003-09-18 2005-11-01 International Business Machines Corporation Method for interlayer and yield based optical proximity correction
US7047511B2 (en) * 2003-09-26 2006-05-16 International Business Machines Corporation Electronic circuit design
US7134103B2 (en) * 2003-12-17 2006-11-07 International Business Machines Corporation Method, system, and product for verifying voltage drop across an entire integrated circuit package
US7039896B2 (en) * 2003-12-18 2006-05-02 Lsi Logic Corporation Gradient method of mask edge correction
US7523429B2 (en) * 2004-02-20 2009-04-21 Takumi Technology Corporation System for designing integrated circuits with enhanced manufacturability
US7536660B2 (en) * 2004-02-24 2009-05-19 Konstantinos Adam OPC simulation model using SOCS decomposition of edge fragments
US7653890B2 (en) * 2004-04-02 2010-01-26 Cadence Design Systems, Inc. Modeling resolution enhancement processes in integrated circuit fabrication
US20050229130A1 (en) * 2004-04-07 2005-10-13 Aprio Technologies, Inc. Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements
US7536664B2 (en) * 2004-08-12 2009-05-19 International Business Machines Corporation Physical design system and method

Also Published As

Publication number Publication date
TW200609782A (en) 2006-03-16
US8473885B2 (en) 2013-06-25
CN100570855C (zh) 2009-12-16
US20060036977A1 (en) 2006-02-16
CN1734744A (zh) 2006-02-15
US20090204930A1 (en) 2009-08-13
US7536664B2 (en) 2009-05-19
TWI349864B (en) 2011-10-01
US8219943B2 (en) 2012-07-10
JP2006059348A (ja) 2006-03-02
US20120167029A1 (en) 2012-06-28

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