JP4599578B2 - 半導体デバイス製造過程におけるパターンの変形とフォトマスクの汚染の抑制方法 - Google Patents

半導体デバイス製造過程におけるパターンの変形とフォトマスクの汚染の抑制方法 Download PDF

Info

Publication number
JP4599578B2
JP4599578B2 JP2004525039A JP2004525039A JP4599578B2 JP 4599578 B2 JP4599578 B2 JP 4599578B2 JP 2004525039 A JP2004525039 A JP 2004525039A JP 2004525039 A JP2004525039 A JP 2004525039A JP 4599578 B2 JP4599578 B2 JP 4599578B2
Authority
JP
Japan
Prior art keywords
amorphous carbon
layer
hard mask
capping
upper layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004525039A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005535119A5 (enExample
JP2005535119A (ja
Inventor
ジェイ. ボンサー ダグラス
ブイ. プラット マリーナ
ユ ヤン チ
エイ. ベル スコット
エイ. チャン ダリン
エイ. フィッシャー フィリップ
エフ. ライアンズ クリストファー
エス. チャン マーク
ガオ ペイ−ユアン
アイ. ライト マリリン
ユー ルー
ダクシナ−マーシー スリカンテスワラ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2005535119A publication Critical patent/JP2005535119A/ja
Publication of JP2005535119A5 publication Critical patent/JP2005535119A5/ja
Application granted granted Critical
Publication of JP4599578B2 publication Critical patent/JP4599578B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
JP2004525039A 2002-07-31 2003-07-29 半導体デバイス製造過程におけるパターンの変形とフォトマスクの汚染の抑制方法 Expired - Fee Related JP4599578B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US40045302P 2002-07-31 2002-07-31
US10/334,392 US6764949B2 (en) 2002-07-31 2002-12-30 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication
PCT/US2003/023746 WO2004012246A2 (en) 2002-07-31 2003-07-29 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication

Publications (3)

Publication Number Publication Date
JP2005535119A JP2005535119A (ja) 2005-11-17
JP2005535119A5 JP2005535119A5 (enExample) 2006-09-14
JP4599578B2 true JP4599578B2 (ja) 2010-12-15

Family

ID=31190859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004525039A Expired - Fee Related JP4599578B2 (ja) 2002-07-31 2003-07-29 半導体デバイス製造過程におけるパターンの変形とフォトマスクの汚染の抑制方法

Country Status (9)

Country Link
US (1) US6764949B2 (enExample)
EP (1) EP1576657B1 (enExample)
JP (1) JP4599578B2 (enExample)
KR (1) KR101001346B1 (enExample)
CN (1) CN100341114C (enExample)
AU (1) AU2003254254A1 (enExample)
DE (1) DE60330998D1 (enExample)
TW (1) TWI307917B (enExample)
WO (1) WO2004012246A2 (enExample)

Families Citing this family (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6573030B1 (en) * 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US6939808B2 (en) * 2002-08-02 2005-09-06 Applied Materials, Inc. Undoped and fluorinated amorphous carbon film as pattern mask for metal etch
US7084071B1 (en) * 2002-09-16 2006-08-01 Advanced Micro Devices, Inc. Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon
US6803313B2 (en) * 2002-09-27 2004-10-12 Advanced Micro Devices, Inc. Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes
US6855627B1 (en) * 2002-12-04 2005-02-15 Advanced Micro Devices, Inc. Method of using amorphous carbon to prevent resist poisoning
US6972255B2 (en) * 2003-07-28 2005-12-06 Freescale Semiconductor, Inc. Semiconductor device having an organic anti-reflective coating (ARC) and method therefor
US7132201B2 (en) 2003-09-12 2006-11-07 Micron Technology, Inc. Transparent amorphous carbon structure in semiconductor devices
US7129180B2 (en) * 2003-09-12 2006-10-31 Micron Technology, Inc. Masking structure having multiple layers including an amorphous carbon layer
US6838347B1 (en) * 2003-09-23 2005-01-04 International Business Machines Corporation Method for reducing line edge roughness of oxide material using chemical oxide removal
US7064078B2 (en) * 2004-01-30 2006-06-20 Applied Materials Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
US7172969B2 (en) * 2004-08-26 2007-02-06 Tokyo Electron Limited Method and system for etching a film stack
US7151040B2 (en) * 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7910288B2 (en) * 2004-09-01 2011-03-22 Micron Technology, Inc. Mask material conversion
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7655387B2 (en) * 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
US7390746B2 (en) * 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7253118B2 (en) * 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
US7371627B1 (en) 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7429536B2 (en) * 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7560390B2 (en) * 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) * 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7541632B2 (en) * 2005-06-14 2009-06-02 Micron Technology, Inc. Relaxed-pitch method of aligning active area to digit line
US7271108B2 (en) * 2005-06-28 2007-09-18 Lam Research Corporation Multiple mask process with etch mask stack
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7413981B2 (en) * 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US8123968B2 (en) * 2005-08-25 2012-02-28 Round Rock Research, Llc Multiple deposition for integration of spacers in pitch multiplication process
US7816262B2 (en) * 2005-08-30 2010-10-19 Micron Technology, Inc. Method and algorithm for random half pitched interconnect layout with constant spacing
US7829262B2 (en) * 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7416943B2 (en) * 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US7759197B2 (en) 2005-09-01 2010-07-20 Micron Technology, Inc. Method of forming isolated features using pitch multiplication
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7776744B2 (en) * 2005-09-01 2010-08-17 Micron Technology, Inc. Pitch multiplication spacers and methods of forming the same
US7572572B2 (en) * 2005-09-01 2009-08-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7687342B2 (en) * 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7557032B2 (en) * 2005-09-01 2009-07-07 Micron Technology, Inc. Silicided recessed silicon
JP2007149768A (ja) * 2005-11-24 2007-06-14 Nec Electronics Corp 半導体装置の製造方法
US7842558B2 (en) 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US8003310B2 (en) 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US7488685B2 (en) 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US7795149B2 (en) * 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US7723009B2 (en) 2006-06-02 2010-05-25 Micron Technology, Inc. Topography based patterning
US7611980B2 (en) * 2006-08-30 2009-11-03 Micron Technology, Inc. Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
US7666578B2 (en) 2006-09-14 2010-02-23 Micron Technology, Inc. Efficient pitch multiplication process
KR100772706B1 (ko) 2006-09-28 2007-11-02 주식회사 하이닉스반도체 반도체 소자의 콘택홀 제조 방법
KR100834396B1 (ko) * 2006-12-27 2008-06-04 주식회사 하이닉스반도체 반도체 소자의 패턴 형성 방법
KR100808056B1 (ko) * 2006-12-27 2008-02-28 주식회사 하이닉스반도체 하드마스크를 이용한 패턴 형성 방법
KR100792405B1 (ko) * 2007-01-03 2008-01-09 주식회사 하이닉스반도체 벌브형 리세스 패턴의 제조 방법
US20080254233A1 (en) * 2007-04-10 2008-10-16 Kwangduk Douglas Lee Plasma-induced charge damage control for plasma enhanced chemical vapor deposition processes
US9732416B1 (en) 2007-04-18 2017-08-15 Novellus Systems, Inc. Wafer chuck with aerodynamic design for turbulence reduction
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7718546B2 (en) * 2007-06-27 2010-05-18 Sandisk 3D Llc Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US20090098701A1 (en) * 2007-10-15 2009-04-16 Jurgen Faul Method of manufacturing an integrated circuit
US7737039B2 (en) 2007-11-01 2010-06-15 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US7659208B2 (en) 2007-12-06 2010-02-09 Micron Technology, Inc Method for forming high density patterns
US7790531B2 (en) 2007-12-18 2010-09-07 Micron Technology, Inc. Methods for isolating portions of a loop of pitch-multiplied material and related structures
US8030218B2 (en) 2008-03-21 2011-10-04 Micron Technology, Inc. Method for selectively modifying spacing between pitch multiplied structures
US8110476B2 (en) * 2008-04-11 2012-02-07 Sandisk 3D Llc Memory cell that includes a carbon-based memory element and methods of forming the same
US8076208B2 (en) 2008-07-03 2011-12-13 Micron Technology, Inc. Method for forming transistor with high breakdown voltage using pitch multiplication technique
US8557685B2 (en) * 2008-08-07 2013-10-15 Sandisk 3D Llc Memory cell that includes a carbon-based memory element and methods of forming the same
US8419964B2 (en) 2008-08-27 2013-04-16 Novellus Systems, Inc. Apparatus and method for edge bevel removal of copper from silicon wafers
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
US8492282B2 (en) 2008-11-24 2013-07-23 Micron Technology, Inc. Methods of forming a masking pattern for integrated circuits
US8172646B2 (en) 2009-02-27 2012-05-08 Novellus Systems, Inc. Magnetically actuated chuck for edge bevel removal
US8304175B2 (en) * 2009-03-25 2012-11-06 Macronix International Co., Ltd. Patterning method
TWI419201B (zh) * 2009-04-27 2013-12-11 Macronix Int Co Ltd 圖案化的方法
DE102009046259B4 (de) * 2009-10-30 2019-10-10 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Stärkere Haftung eines PECVD-Kohlenstoffs auf dielektrischen Materialien durch Vorsehen einer Haftungsgrenzfläche
US8252699B2 (en) * 2010-11-22 2012-08-28 Applied Materials, Inc. Composite removable hardmask
KR20130075158A (ko) 2011-12-27 2013-07-05 삼성전자주식회사 반도체 소자의 제조 방법
US9881788B2 (en) 2014-05-22 2018-01-30 Lam Research Corporation Back side deposition apparatus and applications
KR102477091B1 (ko) * 2015-07-24 2022-12-13 삼성전자주식회사 2차원 물질 하드마스크와 그 제조방법 및 하드 마스크를 이용한 물질층 패턴 형성방법
US9806161B1 (en) * 2016-04-07 2017-10-31 Globalfoundries Inc. Integrated circuit structure having thin gate dielectric device and thick gate dielectric device
CN108695162B (zh) 2017-04-12 2021-04-09 联华电子股份有限公司 鳍状结构的制造方法
US10345702B2 (en) 2017-08-24 2019-07-09 International Business Machines Corporation Polymer brushes for extreme ultraviolet photolithography
US10522750B2 (en) 2018-02-19 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multiply spin-coated ultra-thick hybrid hard mask for sub 60nm MRAM devices
US12272608B2 (en) 2020-01-03 2025-04-08 Lam Research Corporation Station-to-station control of backside bow compensation deposition
WO2021154641A1 (en) 2020-01-30 2021-08-05 Lam Research Corporation Uv cure for local stress modulation
CN113948377A (zh) * 2021-10-19 2022-01-18 长江存储科技有限责任公司 一种半导体结构及一种硬掩膜层的制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0517627A1 (en) * 1991-06-07 1992-12-09 Eastman Kodak Company Deposited carbon mask for dry etch processing of Si
FR2687844A1 (fr) * 1992-02-26 1993-08-27 Chouan Yannick Procede de fabrication d'un transistor en couches minces a double grille et a masque optique.
US5656128A (en) * 1993-03-26 1997-08-12 Fujitsu Limited Reduction of reflection by amorphous carbon
US5759746A (en) * 1996-05-24 1998-06-02 Kabushiki Kaisha Toshiba Fabrication process using a thin resist
JP3047832B2 (ja) * 1996-10-03 2000-06-05 日本電気株式会社 半導体装置の製造方法
US6143476A (en) * 1997-12-12 2000-11-07 Applied Materials Inc Method for high temperature etching of patterned layers using an organic mask stack
TWI246633B (en) * 1997-12-12 2006-01-01 Applied Materials Inc Method of pattern etching a low k dielectric layen
JP2000058830A (ja) * 1998-05-28 2000-02-25 Texas Instr Inc <Ti> 反射防止構造体とその製造法
US6664639B2 (en) * 2000-12-22 2003-12-16 Matrix Semiconductor, Inc. Contact and via structure and method of fabrication

Also Published As

Publication number Publication date
KR20050019905A (ko) 2005-03-03
TW200405414A (en) 2004-04-01
DE60330998D1 (de) 2010-03-04
AU2003254254A1 (en) 2004-02-16
US6764949B2 (en) 2004-07-20
WO2004012246A3 (en) 2004-05-13
CN1672243A (zh) 2005-09-21
KR101001346B1 (ko) 2010-12-14
CN100341114C (zh) 2007-10-03
EP1576657B1 (en) 2010-01-13
TWI307917B (en) 2009-03-21
JP2005535119A (ja) 2005-11-17
US20040023475A1 (en) 2004-02-05
EP1576657A2 (en) 2005-09-21
WO2004012246A2 (en) 2004-02-05

Similar Documents

Publication Publication Date Title
JP4599578B2 (ja) 半導体デバイス製造過程におけるパターンの変形とフォトマスクの汚染の抑制方法
CN112750760B (zh) 自对准双图案化
US6803313B2 (en) Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes
US6750127B1 (en) Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance
KR100190261B1 (ko) 집적회로의 게이트 스택 제조 방법
JP5100198B2 (ja) 半導体素子の微細パターンの形成方法
KR100834396B1 (ko) 반도체 소자의 패턴 형성 방법
CN101207008B (zh) 制造半导体器件的方法
US8247878B2 (en) Semiconductor device and method of manufacturing the same
JP4606967B2 (ja) 半導体素子の製造方法
WO2004034442A2 (en) Method for semiconductor gate width reduction
US7585727B2 (en) Method for fabricating semiconductor device having bulb-shaped recess gate
US6764947B1 (en) Method for reducing gate line deformation and reducing gate line widths in semiconductor devices
US10460939B1 (en) Patterning method
TWI623084B (zh) 半導體結構及其製造方法
US7049245B2 (en) Two-step GC etch for GC profile and process window improvement
JP2002110967A (ja) 半導体装置の製造方法および半導体装置
US6812077B1 (en) Method for patterning narrow gate lines
JP2006128613A (ja) 半導体素子の製造方法
KR20050106917A (ko) 반도체소자의 게이트라인 제조 방법
KR19990015596A (ko) 게이트 스페이서 형성공정에서 언더컷을 억제한 트랜지스터제조방법
KR20090045717A (ko) 반도체 소자의 제조 방법
KR20100053896A (ko) 반도체 장치 제조 방법
KR20100019707A (ko) 반도체 소자 및 그 형성 방법
JP2007273526A (ja) 半導体集積回路装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060727

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060727

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090729

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090804

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20091104

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091105

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20091111

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100323

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100421

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100618

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100804

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100902

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100903

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131008

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees