CN100341114C - 减少在半导体装置制造过程中图案变形及光刻胶中毒的方法 - Google Patents
减少在半导体装置制造过程中图案变形及光刻胶中毒的方法 Download PDFInfo
- Publication number
- CN100341114C CN100341114C CNB038182580A CN03818258A CN100341114C CN 100341114 C CN100341114 C CN 100341114C CN B038182580 A CNB038182580 A CN B038182580A CN 03818258 A CN03818258 A CN 03818258A CN 100341114 C CN100341114 C CN 100341114C
- Authority
- CN
- China
- Prior art keywords
- layer
- amorphous carbon
- substance
- capping
- hard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US40045302P | 2002-07-31 | 2002-07-31 | |
| US60/400,453 | 2002-07-31 | ||
| US10/334,392 | 2002-12-30 | ||
| US10/334,392 US6764949B2 (en) | 2002-07-31 | 2002-12-30 | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1672243A CN1672243A (zh) | 2005-09-21 |
| CN100341114C true CN100341114C (zh) | 2007-10-03 |
Family
ID=31190859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038182580A Expired - Lifetime CN100341114C (zh) | 2002-07-31 | 2003-07-29 | 减少在半导体装置制造过程中图案变形及光刻胶中毒的方法 |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US6764949B2 (enExample) |
| EP (1) | EP1576657B1 (enExample) |
| JP (1) | JP4599578B2 (enExample) |
| KR (1) | KR101001346B1 (enExample) |
| CN (1) | CN100341114C (enExample) |
| AU (1) | AU2003254254A1 (enExample) |
| DE (1) | DE60330998D1 (enExample) |
| TW (1) | TWI307917B (enExample) |
| WO (1) | WO2004012246A2 (enExample) |
Families Citing this family (85)
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| US6803313B2 (en) * | 2002-09-27 | 2004-10-12 | Advanced Micro Devices, Inc. | Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes |
| US6855627B1 (en) * | 2002-12-04 | 2005-02-15 | Advanced Micro Devices, Inc. | Method of using amorphous carbon to prevent resist poisoning |
| US6972255B2 (en) * | 2003-07-28 | 2005-12-06 | Freescale Semiconductor, Inc. | Semiconductor device having an organic anti-reflective coating (ARC) and method therefor |
| US7132201B2 (en) | 2003-09-12 | 2006-11-07 | Micron Technology, Inc. | Transparent amorphous carbon structure in semiconductor devices |
| US7129180B2 (en) * | 2003-09-12 | 2006-10-31 | Micron Technology, Inc. | Masking structure having multiple layers including an amorphous carbon layer |
| US6838347B1 (en) * | 2003-09-23 | 2005-01-04 | International Business Machines Corporation | Method for reducing line edge roughness of oxide material using chemical oxide removal |
| US7064078B2 (en) * | 2004-01-30 | 2006-06-20 | Applied Materials | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
| US7172969B2 (en) * | 2004-08-26 | 2007-02-06 | Tokyo Electron Limited | Method and system for etching a film stack |
| US7151040B2 (en) * | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
| US7910288B2 (en) * | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
| US7115525B2 (en) * | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
| US7655387B2 (en) * | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
| US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
| US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
| US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
| US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
| US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
| US7429536B2 (en) * | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
| US7560390B2 (en) * | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
| US7396781B2 (en) * | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
| US7541632B2 (en) * | 2005-06-14 | 2009-06-02 | Micron Technology, Inc. | Relaxed-pitch method of aligning active area to digit line |
| US7271108B2 (en) * | 2005-06-28 | 2007-09-18 | Lam Research Corporation | Multiple mask process with etch mask stack |
| US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
| US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
| US7413981B2 (en) * | 2005-07-29 | 2008-08-19 | Micron Technology, Inc. | Pitch doubled circuit layout |
| US8123968B2 (en) * | 2005-08-25 | 2012-02-28 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
| US7816262B2 (en) * | 2005-08-30 | 2010-10-19 | Micron Technology, Inc. | Method and algorithm for random half pitched interconnect layout with constant spacing |
| US7829262B2 (en) * | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
| US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
| US7416943B2 (en) * | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
| US7759197B2 (en) | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
| US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
| US7776744B2 (en) * | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
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| JP2007149768A (ja) * | 2005-11-24 | 2007-06-14 | Nec Electronics Corp | 半導体装置の製造方法 |
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| US7476933B2 (en) | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
| US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
| US8003310B2 (en) | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
| US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
| US7795149B2 (en) * | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
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| US7611980B2 (en) * | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
| US7517804B2 (en) * | 2006-08-31 | 2009-04-14 | Micron Technologies, Inc. | Selective etch chemistries for forming high aspect ratio features and associated structures |
| US7666578B2 (en) | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
| KR100772706B1 (ko) | 2006-09-28 | 2007-11-02 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택홀 제조 방법 |
| KR100834396B1 (ko) * | 2006-12-27 | 2008-06-04 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성 방법 |
| KR100808056B1 (ko) * | 2006-12-27 | 2008-02-28 | 주식회사 하이닉스반도체 | 하드마스크를 이용한 패턴 형성 방법 |
| KR100792405B1 (ko) * | 2007-01-03 | 2008-01-09 | 주식회사 하이닉스반도체 | 벌브형 리세스 패턴의 제조 방법 |
| US20080254233A1 (en) * | 2007-04-10 | 2008-10-16 | Kwangduk Douglas Lee | Plasma-induced charge damage control for plasma enhanced chemical vapor deposition processes |
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| US7718546B2 (en) * | 2007-06-27 | 2010-05-18 | Sandisk 3D Llc | Method for fabricating a 3-D integrated circuit using a hard mask of silicon-oxynitride on amorphous carbon |
| US8563229B2 (en) | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
| US20090098701A1 (en) * | 2007-10-15 | 2009-04-16 | Jurgen Faul | Method of manufacturing an integrated circuit |
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| DE102009046259B4 (de) * | 2009-10-30 | 2019-10-10 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Stärkere Haftung eines PECVD-Kohlenstoffs auf dielektrischen Materialien durch Vorsehen einer Haftungsgrenzfläche |
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| KR20130075158A (ko) | 2011-12-27 | 2013-07-05 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
| US9881788B2 (en) | 2014-05-22 | 2018-01-30 | Lam Research Corporation | Back side deposition apparatus and applications |
| KR102477091B1 (ko) * | 2015-07-24 | 2022-12-13 | 삼성전자주식회사 | 2차원 물질 하드마스크와 그 제조방법 및 하드 마스크를 이용한 물질층 패턴 형성방법 |
| US9806161B1 (en) * | 2016-04-07 | 2017-10-31 | Globalfoundries Inc. | Integrated circuit structure having thin gate dielectric device and thick gate dielectric device |
| CN108695162B (zh) | 2017-04-12 | 2021-04-09 | 联华电子股份有限公司 | 鳍状结构的制造方法 |
| US10345702B2 (en) | 2017-08-24 | 2019-07-09 | International Business Machines Corporation | Polymer brushes for extreme ultraviolet photolithography |
| US10522750B2 (en) | 2018-02-19 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiply spin-coated ultra-thick hybrid hard mask for sub 60nm MRAM devices |
| US12272608B2 (en) | 2020-01-03 | 2025-04-08 | Lam Research Corporation | Station-to-station control of backside bow compensation deposition |
| WO2021154641A1 (en) | 2020-01-30 | 2021-08-05 | Lam Research Corporation | Uv cure for local stress modulation |
| CN113948377A (zh) * | 2021-10-19 | 2022-01-18 | 长江存储科技有限责任公司 | 一种半导体结构及一种硬掩膜层的制造方法 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5656128A (en) * | 1993-03-26 | 1997-08-12 | Fujitsu Limited | Reduction of reflection by amorphous carbon |
| US5759746A (en) * | 1996-05-24 | 1998-06-02 | Kabushiki Kaisha Toshiba | Fabrication process using a thin resist |
| US5869365A (en) * | 1996-10-03 | 1999-02-09 | Nec Corporation | Method of forming T electrode in field effect transistor |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0517627A1 (en) * | 1991-06-07 | 1992-12-09 | Eastman Kodak Company | Deposited carbon mask for dry etch processing of Si |
| FR2687844A1 (fr) * | 1992-02-26 | 1993-08-27 | Chouan Yannick | Procede de fabrication d'un transistor en couches minces a double grille et a masque optique. |
| US6143476A (en) * | 1997-12-12 | 2000-11-07 | Applied Materials Inc | Method for high temperature etching of patterned layers using an organic mask stack |
| TWI246633B (en) * | 1997-12-12 | 2006-01-01 | Applied Materials Inc | Method of pattern etching a low k dielectric layen |
| JP2000058830A (ja) * | 1998-05-28 | 2000-02-25 | Texas Instr Inc <Ti> | 反射防止構造体とその製造法 |
| US6664639B2 (en) * | 2000-12-22 | 2003-12-16 | Matrix Semiconductor, Inc. | Contact and via structure and method of fabrication |
-
2002
- 2002-12-30 US US10/334,392 patent/US6764949B2/en not_active Expired - Lifetime
-
2003
- 2003-07-29 EP EP03772065A patent/EP1576657B1/en not_active Expired - Lifetime
- 2003-07-29 JP JP2004525039A patent/JP4599578B2/ja not_active Expired - Fee Related
- 2003-07-29 DE DE60330998T patent/DE60330998D1/de not_active Expired - Lifetime
- 2003-07-29 WO PCT/US2003/023746 patent/WO2004012246A2/en not_active Ceased
- 2003-07-29 KR KR1020057000968A patent/KR101001346B1/ko not_active Expired - Fee Related
- 2003-07-29 CN CNB038182580A patent/CN100341114C/zh not_active Expired - Lifetime
- 2003-07-29 AU AU2003254254A patent/AU2003254254A1/en not_active Abandoned
- 2003-07-31 TW TW092120947A patent/TWI307917B/zh not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5656128A (en) * | 1993-03-26 | 1997-08-12 | Fujitsu Limited | Reduction of reflection by amorphous carbon |
| US5759746A (en) * | 1996-05-24 | 1998-06-02 | Kabushiki Kaisha Toshiba | Fabrication process using a thin resist |
| US5998100A (en) * | 1996-05-24 | 1999-12-07 | Kabushiki Kaisha Toshiba | Fabrication process using a multi-layer antireflective layer |
| US5869365A (en) * | 1996-10-03 | 1999-02-09 | Nec Corporation | Method of forming T electrode in field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20050019905A (ko) | 2005-03-03 |
| TW200405414A (en) | 2004-04-01 |
| DE60330998D1 (de) | 2010-03-04 |
| AU2003254254A1 (en) | 2004-02-16 |
| US6764949B2 (en) | 2004-07-20 |
| WO2004012246A3 (en) | 2004-05-13 |
| CN1672243A (zh) | 2005-09-21 |
| KR101001346B1 (ko) | 2010-12-14 |
| EP1576657B1 (en) | 2010-01-13 |
| TWI307917B (en) | 2009-03-21 |
| JP2005535119A (ja) | 2005-11-17 |
| JP4599578B2 (ja) | 2010-12-15 |
| US20040023475A1 (en) | 2004-02-05 |
| EP1576657A2 (en) | 2005-09-21 |
| WO2004012246A2 (en) | 2004-02-05 |
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