Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
  • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
  • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

Definitions

• Embodiments of the invention relate to semiconductor fabrication, and in particular, to methods of eliminating pattern deformation in semiconductor devices.
• Related Art The use of amorphous carbon film as part of a hardmask stack for patterning MOSFET features has been found to be beneficial due to the ease with which amorphous carbon may be patterned and the high selectivity of amorphous carbon relative to typically used capping or protective materials such as silicon oxide, silicon nitride and silicon oxynitride.
• Figure 1 shows a structure including amorphous carbon that may be used in the formation of a MOSFET.
• the structure includes a semiconductor substrate 2 having field oxides 4 that bound source/drain regions of a MOSFET.
• a layer of a gate insulating material 6 such as Si0 2 is formed over the substrate.
• a layer of a gate conductive material 8 such as doped polysilicon is formed over the substrate and will be patterned to form a gate line of the MOSFET.
• a hardmask stack including an amorphous carbon layer 10 and a capping material layer 12 such as SiON.
• a photoresist mask 14 for defining the pattern of the gate is formed on the SiON capping material layer 12.
• a first etch is used to transfer the photoresist mask pattern to the SiON layer
• a second etch is used to transfer the SiON mask pattern to the amorphous carbon layer
• a third etch is used to remove oxide from the surface of the gate conductive layer
• a further etches are performed to etch the underlying gate conductive layer using the SiON and amorphous carbon patterns as a hardmask.
• amorphous carbon material has relatively poor selectivity with respect to the polysilicon gate conductive material during the polysilicon etch, and as a result the amorphous carbon is also etched during etching of the polysilicon, resulting in degradation of the transferred pattern.
• a proposed solution to this problem is to dope the amorphous carbon with nitrogen, which enhances its selectivity with respect to polysilicon.
• the nitrogen doping technique creates other problems that become more significant as device dimensions are reduced.
• One problem involves poisoning of the photoresist with nitrogen from the amorphous carbon layer. Poisoning is enabled by pinholes in the SiON cap layer that randomly occur during SiON deposition. The pinholes extend partly or entirely through the SiON layer, enabling nitrogen dopant from the amorphous carbon to diffuse into the photoresist. Poisoned photoresist is difficult to remove by conventional developing techniques and therefore the poisoned photoresist degrades the quality of the photoresist mask. As SiON cap layers become thinner, the poisoning problem becomes more pronounced.
• a second problem of amo ⁇ hous carbon is delamination of etched amorphous carbon from the underlying polysilicon.
• Figures 2a and 2b illustrate this problem.
• Figure 2a shows a top view of a patterned amorphous carbon line.
• the line is subject to compressive forces 16 resulting from differences in the thermal expansion coefficients of amorphous carbon, polysilicon and SiON.
• the compressive forces along the length of the line become significantly greater than those across the width of the line. So long as a SiON top layer is present on the amorphous carbon line, the compressive forces do not deform the line.
• an etch for removing oxide from the polysilicon layer is performed after patterning the amorphous carbon, and this etch typically removes most or all of the SiON overlying the amorphous carbon line.
• a hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon.
• the undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination.
• the stack is provided with a top capping material layer.
• the layer beneath the capping material layer is preferably undoped amorphous carbon to reduce photoresist poisoning.
• a hardmask stack is comprised of alternating layers of a capping material and amorphous carbon.
• the amorphous carbon layers may be doped or undoped.
• the capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination.
• the top layer of the stack is formed of the capping material.
• the layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning.
• the lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from the underlying materials by an ashing process.
• Figure 1 shows a structure formed during fabrication of a semiconductor device using an amorphous carbon layer.
• Figures 2a and 2b illustrate doped amorphous carbon line deformation.
• Figures 3a and 3b show structures formed during fabrication of a semiconductor device in accordance with a first preferred embodiment of the invention.
• Figure 4 shows a process flow encompassing the first preferred embodiment and alternative embodiments.
• Figures 5 shows a structure formed during fabrication of a semiconductor device in accordance with a second preferred embodiment of the invention.
• Figure 6 shows a process flow encompassing the second preferred embodiment and alternative embodiments.
• Figures 3 a and 3b show alternative structure formed in accordance with a first preferred embodiment of the invention.
• the structure of Figure 3a includes a semiconductor substrate 2 having field oxides 4 that bound source/drain regions of a MOSFET.
• Layers of a gate insulating material 6 such as Si0 2 and a gate conductive material 8 such as doped polysilicon are formed over the substrate and will be patterned to form a gate line and gate insulator of the MOSFET.
• a hardmask stack including an amorphous carbon portion formed in contact with the underlying polysilicon.
• the amorphous carbon portion is comprised of discrete alternating layers of doped amorphous carbon 22 containing dopant such as nitrogen for enhancing its etch selectivity relative to the polysilicon, and undoped amorphous carbon 20 that contains essentially none of the etch selectivity enhancing dopant of the doped layers 22.
• a capping layer 12 of SiON, silicon oxide or silicon nitride is formed over the amorphous carbon portion of the hardmask stack, and a photoresist mask 14 for defining the pattern of the gate line is formed on the capping layer 12.
• the total height of the hardmask stack is preferably approximately 500 angstroms.
• the structure of Figure 3a differs from the structure of Figure 1 in its use of undoped amorphous carbon layers 20 in conjunction with one or more doped amorphous carbon layers 22.
• the undoped layers 20 serve as buffering layers that constrain the compressive stresses within the doped layers 22 to prevent delamination. While any number and order of doped and undoped layers may be employed in accordance with this embodiment, it is preferred to provide an uppermost layer of undoped amorphous carbon in contact with the capping layer to reduce photoresist poisoning, and to provide a lowermost layer of undoped amorphous carbon formed on the underlying polysilicon layer to increase resistance to delamination.
• the layers of the amorphous carbon portion illustrated in Figure 3a are formed as discrete layers in independent processing steps.
• the doped and undoped layers may be formed as continuous layers as illustrated in Figure 3b. This is done by varying dopant source gas flow rates during a single continuous deposition process to produce a dopant profile having a desired gradient through the amorphous carbon portion of the hardmask.
• FIG. 3a and 3b may employ a greater number of layers of doped and undoped amorphous carbon, and may arrange those layers in a different order, such as by having a doped layer formed on the underlying polysilicon.
• alternative capping materials such as silicon rich oxide, or silicon rich nitride may be employed.
• such hardmask structures may be formed over a different material to be etched, such as a metal wiring layer, or may be used to form a different type of patterned structure, such as a contact or interconnect.
• Figure 4 shows a process flow for manufacture of a semiconductor device encompassing the first preferred embodiment, its aforementioned alternatives, and further alternative embodiments not explicitly discussed.
• a substrate comprising an upper layer of material is provided (30).
• a hardmask stack is then formed on the upper layer of material (32).
• the hardmask stack is comprised of an amorphous carbon portion formed in contact with the layer of material, and a capping layer formed on the amorphous carbon portion.
• the amorphous carbon portion is comprised of alternating layers of doped amorphous carbon containing dopant for enhancing etch selectivity with respect to the material, and undoped amorphous carbon that contains essentially none of the dopant.
• a photoresist mask is then formed over the hardmask (34).
• the photoresist mask may be trimmed by a photoresist trimming process.
• the hardmask stack is then etched using the photoresist mask as an initial etch mask to form a hardmask for patterning the underlying material (36).
• Further processing may also be performed such as patterning the upper layer of material and removing the hardmask.
• Figure 5 shows a structure formed in accordance with a second preferred embodiment of the invention.
• the structure of Figure 5 includes a semiconductor substrate 2 having field oxides 4 that bound source/drain regions of a MOSFET.
• Layers of a gate insulating material 6 such as silicon oxide and a gate conductive material 8 such as doped polysilicon are formed over the substrate.
• the gate conductive layer 8 will be patterned to form a gate line of a MOSFET.
• Formed over the gate conductive layer 8 is a hardmask stack including alternating layers of amorphous carbon 40 and a layer of a capping material 42 such as silicon oxide, silicon nitride, or silicon oxynitride.
• the amorphous carbon may be doped or undoped.
• a photoresist mask 14 for defining the pattern of the gate line is formed on the upper layer of capping material.
• the total height of the hardmask stack is preferably approximately 500 angstroms.
• the layers of capping material are preferably 20 - 50 angstroms in height.
• the structure of Figure 5 differs from the structure of Figure 1 in its use of multiple alternating layers of amorphous carbon and capping material.
• the layers of capping material 42 serve as buffering layers that constrain compressive stresses within amorphous carbon layers 40 to prevent delamination. While the uppermost layer of capping material will typically be removed during the course of etching the hardmask, the remaining layer or layers of capping material will remain to resist delamination.
• the lowermost layer of the hardmask stack is amorphous carbon in order to enable removal of the hardmask by an ashing process, and to form the uppermost amorphous carbon layer of the hardmask stack from undoped amorphous carbon to reduce photoresist poisoning.
• the lowermost layer may be formed of a capping material, and the uppermost amorphous carbon layer may be doped.
• alternative capping materials such as silicon rich oxide, or silicon rich nitride may be employed, and different capping materials may be used in different layers within the same hardmask stack.
• such hardmask structures may be formed over a different material to be etched, such as a metal wiring layer, or may be used to form a different type of patterned structure, such as a contact or interconnect.
• Figure 6 shows a process flow for manufacture of a semiconductor device encompassing the second preferred embodiment, its aforementioned alternatives, and further alternative embodiments not explicitly discussed.
• a substrate comprising an upper layer of material is provided (50).
• a hardmask stack is then formed on the upper layer of material (52).
• the hardmask stack is comprised of alternating layers of capping material and amorphous carbon including at least a first upper layer of capping material, a layer of amorphous carbon underlying the first upper layer of capping material, and a second layer of capping material underlying the layer of amorphous carbon.
• a photoresist mask is then formed over the hardmask (54). The photoresist mask may be trimmed by a photoresist trimming process.
• the hardmask stack is then etched using the photoresist mask as an initial etch mask to form a hardmask for patterning the underlying upper layer of material (56).
• Further processing may also be performed such as patterning the underlying material and removing the hardmask.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Chemical & Material Sciences (AREA)
• Inorganic Chemistry (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Drying Of Semiconductors (AREA)
• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Junction Field-Effect Transistors (AREA)

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Publications (2)

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• 2002
  • 2002-12-30 US US10/334,392 patent/US6764949B2/en not_active Expired - Lifetime
• 2003
  • 2003-07-29 EP EP03772065A patent/EP1576657B1/en not_active Expired - Lifetime
  • 2003-07-29 JP JP2004525039A patent/JP4599578B2/ja not_active Expired - Fee Related
  • 2003-07-29 DE DE60330998T patent/DE60330998D1/de not_active Expired - Lifetime
  • 2003-07-29 WO PCT/US2003/023746 patent/WO2004012246A2/en not_active Ceased
  • 2003-07-29 KR KR1020057000968A patent/KR101001346B1/ko not_active Expired - Fee Related
  • 2003-07-29 CN CNB038182580A patent/CN100341114C/zh not_active Expired - Lifetime
  • 2003-07-29 AU AU2003254254A patent/AU2003254254A1/en not_active Abandoned
  • 2003-07-31 TW TW092120947A patent/TWI307917B/zh not_active IP Right Cessation

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