JP4551191B2 - 基準のx線識別を用いて内層パネルおよび印刷回路板を製造する方法 - Google Patents
基準のx線識別を用いて内層パネルおよび印刷回路板を製造する方法 Download PDFInfo
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- JP4551191B2 JP4551191B2 JP2004331013A JP2004331013A JP4551191B2 JP 4551191 B2 JP4551191 B2 JP 4551191B2 JP 2004331013 A JP2004331013 A JP 2004331013A JP 2004331013 A JP2004331013 A JP 2004331013A JP 4551191 B2 JP4551191 B2 JP 4551191B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09763—Printed component having superposed conductors, but integrated in one circuit layer
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/167—Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
- H05K3/0082—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49131—Assembling to base an electrical component, e.g., capacitor, etc. by utilizing optical sighting device
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
以下の組成:
ビヒクル 8.85%
TEXANOL(登録商標)溶媒 5.23%
ガラス粉末 27.50%
タングステン粉末 58.42%
を有するペーストを形成した。
以下の組成:
ビヒクル 16.65%
TEXANOL(登録商標)溶媒 4.37%
ガラス粉末 25.26%
タングステン粉末 53.72%
を有するペーストを形成した。
以下の組成:
ビヒクル 29.51%
TEXANOL(登録商標)溶媒 4.8 %
ガラス粉末 21.01%
タングステン粉末 44.67%
を有するペーストを形成した。
以下の組成:
ビヒクル 8.85%
TEXANOL(登録商標)溶媒 5.23%
ガラス粉末 20.92%
タングステン粉末 65.00%
を有するペーストを形成した。
以下に、本発明の好ましい態様を示す。
[1] 金属フォイルを提供する工程と;
該フォイル上に少なくとも1つの基準を形成する工程と;
該フォイル上に少なくとも1つの部品を形成する工程と;
該少なくとも1つの部品および少なくとも1つの基準上に誘電体を付着させ、該少なくとも1つの基準および少なくとも1つの部品を埋め込む工程と;
X線を用いて、該少なくとも1つの基順の位置を識別する工程と
を含むことを特徴とする、内層パネルを作成する方法。
[2] 金属フォイルを提供する工程は、銅を含むフォイルを形成する工程を含むことを特徴とする[1]に記載の方法。
[3] 少なくとも1つの基準を形成する工程は、タングステンを含む少なくとも1つの基準を形成する工程を含むことを特徴とする[1]に記載の方法。
[4] 該少なくとも1つの基準は、ガラス、および53質量%超のタングステンを含有するペーストから形成されることを特徴とする[3]に記載の方法。
[5] 該少なくとも1つの基準の乾燥印刷厚さは、少なくとも15μmであることを特徴とする[3]に記載の方法。
[6] 少なくとも1つの部品を形成する工程および少なくとも1つの基準を形成する工程は、少なくとも1つの焼成工程を含むことを特徴とする[1]に記載の方法。
[7] 少なくとも1つの基準を形成する工程は、厚膜ポリマーペーストを硬化させる工程を含むことを特徴とする[1]に記載の方法。
[8] 該少なくとも1つの基準の位置を識別する前に、該誘電体に対して第2のフォイルを付着する工程と;
該少なくとも1つの基準の識別された位置にしたがって内層パネル中に少なくとも1つのレジスタホールを形成する工程と;
該少なくとも1つのレジスタホールの位置にしたがって光ツールを配置する工程と;
該光ツールを用いてフォイルを画像形成する工程と;
該フォイルをエッチングする工程であって、エッチングが前記埋め込まれた少なくとも1つの部品の終端を与える工程と
をさらに含むことを特徴とする[1]に記載の方法。
[8] 該少なくとも1つの部品は、少なくとも1つのキャパシタまたは抵抗体を含むことを特徴とする[1]に記載の方法。
[10] 該誘電体を付着する前に、該少なくとも1つの基準上に封止剤を付着する工程をさらに含むことを特徴とする[1]に記載の方法。
[11] 該誘電体はプリプレグであることを特徴とする[1]に記載の方法。
[12] [1]に記載の方法によって形成される複数の積み重ねられた内層パネルを含むことを特徴とする印刷配線板。
[13] 誘電体と;
該誘電体中に少なくとも部分的に埋め込まれる少なくとも1つの部品と;
該誘電体中に少なくとも部分的に埋め込まれる少なくとも1つの基準であって、タングステン、タンタル、金、イリジウム、レニウム、オスミウム、ウランおよび白金からなる群から選択される少なくとも1つの元素を含む少なくとも1つの基準と;
該誘電体と接触し、かつ該少なくとも1つの部品と電気的に結合されている少なくとも1つの導電性終端または関連する回路配線と
を含むことを特徴とする内層パネル。
[14] 該少なくとも1つの基準は、ガラスをさらに含むことを特徴とする[13]に記載の内層パネル。
[15] 該少なくとも1つの部品は、少なくとも1つのキャパシタおよび抵抗体を含むことを特徴とする[13]に記載の内層パネル。
[16] 該少なくとも1つの部品と該誘電体との間に配置される封入剤をさらに含むことを特徴とする[13]に記載の内層パネル。
[17] 複数の積層された[13]に記載の内層パネルを含むことを特徴とする印刷配線板。
12 部品
20 基準
25 封入剤
30 誘電体材料
35 レジスタホール
42 回路配線
50 終端
100、1100、1200、1300 内層パネル
1000 印刷配線板
1021、1022 接続回路配線
Claims (10)
- 金属フォイルを提供する工程であって、前記金属フォイルは、銅、銅−インバール−銅、インバール、ニッケル、ニッケル被覆された銅、およびこれらの組み合わせから選択される群からなる工程と;
該フォイル上に少なくとも1つの基準を形成する工程であって、前記基準は、タングステン、タンタル、金、イリジウム、レニウム、オスミウム、ウランおよび白金からなる群から選択される少なくとも1つの元素を含む工程と;
該フォイル上に少なくとも1つの部品を形成する工程であって、前記部品は、キャパシタ、抵抗体またはこれらの組み合わせを含む工程と;
該少なくとも1つの部品および少なくとも1つの基準上に誘電体を付着させ、該少なくとも1つの基準および少なくとも1つの部品を埋め込む工程と;
X線を用いて、該少なくとも1つの基準の位置を識別する工程と
を含むことを特徴とする、内層パネルを作成する方法。 - 該少なくとも1つの基準は、ガラス、および53質量%超のタングステンを含有するペーストから形成され、および該少なくとも1つの基準の乾燥印刷厚さは少なくとも15μmであることを特徴とする請求項1に記載の方法。
- 少なくとも1つの基準を形成する工程は、厚膜ポリマーペーストを硬化させる工程を含み、および、少なくとも1つの部品を形成する工程および少なくとも1つの基準を形成する工程は、少なくとも1つの焼成工程を含むことを特徴とする請求項1または2に記載の方法。
- 該少なくとも1つの基準の位置を識別する前に、該誘電体に対して第2のフォイルを付着する工程と;
該少なくとも1つの基準の識別された位置にしたがって内層パネル中に少なくとも1つの位置合わせのためのホールを形成する工程と;
前記金属フォイルおよび第2のフォイル上にフォトレジストを付着する工程と;
該少なくとも1つの位置合わせのためのホールの位置にしたがって光ツールを配置する工程と;
該光ツールを用いて前記金属フォイルおよび第2のフォイル上のフォトレジストを画像形成する工程と;
フォトレジストを現像する工程と;
現像されたフォトレジストにしたがって前記金属フォイルおよび第2のフォイルをエッチングする工程であって、エッチングが前記埋め込まれた少なくとも1つの部品の終端を与える工程と;
現像されたフォトレジストを除去する工程と
をさらに含むことを特徴とする請求項1から3のいずれかに記載の方法。 - 該誘電体を付着する前に、該少なくとも1つの基準上に封入剤を付着する工程をさらに含むことを特徴とする請求項1から4のいずれかに記載の方法。
- 該誘電体はプリプレグであることを特徴とする請求項1から5のいずれかに記載の方法。
- 請求項1に記載の方法によって形成される複数の積み重ねられた内層パネルを含むことを特徴とする印刷配線板。
- 誘電体と;
該誘電体中に少なくとも部分的に埋め込まれる少なくとも1つの部品と;
該誘電体中に少なくとも部分的に埋め込まれる少なくとも1つの基準であって、ガラスと、タングステン、タンタル、金、イリジウム、レニウム、オスミウム、ウランおよび白金からなる群から選択される少なくとも1つの元素とを含む少なくとも1つの基準と;
該誘電体と接触し、かつ該少なくとも1つの部品と電気的に結合されている少なくとも1つの導電性終端または関連する回路配線と
を含むことを特徴とする内層パネル。 - 該少なくとも1つの部品と該誘電体との間に配置される封入剤をさらに含むことを特徴とする請求項8に記載の内層パネル。
- 複数の積層された請求項8に記載の内層パネルを含むことを特徴とする印刷配線板。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/718,044 US7178229B2 (en) | 2003-11-20 | 2003-11-20 | Method of making interlayer panels |
Publications (3)
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JP2005159345A JP2005159345A (ja) | 2005-06-16 |
JP2005159345A5 JP2005159345A5 (ja) | 2007-11-15 |
JP4551191B2 true JP4551191B2 (ja) | 2010-09-22 |
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JP2004331013A Expired - Fee Related JP4551191B2 (ja) | 2003-11-20 | 2004-11-15 | 基準のx線識別を用いて内層パネルおよび印刷回路板を製造する方法 |
Country Status (6)
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US (2) | US7178229B2 (ja) |
EP (1) | EP1534051B1 (ja) |
JP (1) | JP4551191B2 (ja) |
KR (1) | KR100687689B1 (ja) |
CN (1) | CN100536636C (ja) |
TW (1) | TWI347808B (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI233323B (en) * | 2004-04-22 | 2005-05-21 | Phoenix Prec Technology Corp | Circuit board with identifiable information and method for fabricating the same |
US7441329B2 (en) * | 2004-06-07 | 2008-10-28 | Subtron Technology Co. Ltd. | Fabrication process circuit board with embedded passive component |
JP2008016758A (ja) * | 2006-07-10 | 2008-01-24 | Adtec Engineeng Co Ltd | 多層回路基板製造におけるマーキング装置 |
KR100882261B1 (ko) * | 2007-07-25 | 2009-02-06 | 삼성전기주식회사 | 인쇄회로기판의 제조 방법 및 장치 |
CN101472404B (zh) * | 2007-12-25 | 2011-12-07 | 富葵精密组件(深圳)有限公司 | 多层电路板及其制作方法 |
JP5525618B2 (ja) * | 2010-10-01 | 2014-06-18 | 株式会社メイコー | 部品内蔵基板の製造方法及びこれを用いた部品内蔵基板 |
KR101713642B1 (ko) * | 2010-10-01 | 2017-03-08 | 메이코 일렉트로닉스 컴파니 리미티드 | 부품 내장 기판 및 부품 내장 기판의 제조 방법 |
TWI404472B (zh) * | 2011-01-05 | 2013-08-01 | Zhen Ding Technology Co Ltd | 電路板之製作方法 |
KR20140089385A (ko) | 2011-10-31 | 2014-07-14 | 메이코 일렉트로닉스 컴파니 리미티드 | 부품내장기판의 제조방법 및 이 방법을 이용하여 제조한 부품내장기판 |
WO2014041601A1 (ja) * | 2012-09-11 | 2014-03-20 | 株式会社メイコー | 部品内蔵基板の製造方法及びこの方法を用いて製造した部品内蔵基板 |
EP2903399A4 (en) * | 2012-09-26 | 2016-07-27 | Meiko Electronics Co Ltd | METHOD FOR MANUFACTURING INTEGRATED COMPONENT SUBSTRATE AND INTEGRATED COMPONENT SUBSTRATE MADE USING THE SAME |
US8847078B2 (en) * | 2012-09-27 | 2014-09-30 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
US11029267B2 (en) * | 2016-04-04 | 2021-06-08 | Security Matters Ltd. | Method and a system for XRF marking and reading XRF marks of electronic systems |
EP3472599B1 (en) * | 2016-04-04 | 2022-06-01 | Soreq Nuclear Research Center | A method and a system for xrf marking and reading xrf marks of electronic systems |
US20170323708A1 (en) * | 2016-05-03 | 2017-11-09 | Texas Instruments Incorporated | Component sheet and method of singulating |
JP2019165072A (ja) * | 2018-03-19 | 2019-09-26 | 富士通株式会社 | 配線基板、半導体モジュール及び配線基板の製造方法 |
CN108770240A (zh) * | 2018-05-03 | 2018-11-06 | 江门崇达电路技术有限公司 | 一种pcb压合后快速识别出料号的工具及方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08155796A (ja) * | 1994-11-30 | 1996-06-18 | Seikosha Co Ltd | X線を用いた穴明け方法及びx線穴明け装置 |
JP2000013023A (ja) * | 1998-06-19 | 2000-01-14 | Matsushita Electric Ind Co Ltd | 多層プリント配線板の製造方法 |
JP2001035946A (ja) * | 1999-07-23 | 2001-02-09 | Matsushita Electric Ind Co Ltd | 電子部品、この電子部品の認識方法およびこの電子部品を用いた電子機器 |
JP2001244638A (ja) * | 1999-12-20 | 2001-09-07 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュール及びその製造方法 |
JP2003092460A (ja) * | 2001-06-05 | 2003-03-28 | Dainippon Printing Co Ltd | 受動素子を備えた配線板の製造方法、受動素子を備えた配線板 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US179329A (en) * | 1876-06-27 | Improvement in combined portmanteaus and shawl-straps | ||
US154592A (en) * | 1874-09-01 | Improvement in wooden shoes | ||
US4190854A (en) * | 1978-02-15 | 1980-02-26 | National Semiconductor Corporation | Trim structure for integrated capacitors |
JPH02153589A (ja) | 1988-12-05 | 1990-06-13 | Ibiden Co Ltd | 厚膜素子付プリント配線板 |
DE69218344T2 (de) * | 1991-11-29 | 1997-10-23 | Hitachi Chemical Co., Ltd., Tokio/Tokyo | Herstellungsverfahren für eine gedruckte Schaltung |
JPH1051143A (ja) | 1996-07-29 | 1998-02-20 | Oki Purintetsudo Circuit Kk | 多層プリント配線板の製造方法 |
KR100198460B1 (ko) * | 1996-10-29 | 1999-06-15 | 이계철 | 브이홈에 정렬된 렌즈를 가진 광모듈 및 그 제작방법 |
WO1998033366A1 (fr) * | 1997-01-29 | 1998-07-30 | Kabushiki Kaisha Toshiba | Procede et dispositif permettant de fabriquer un tableau de connexions multicouches et un tableau de connexions approprie |
US5956564A (en) * | 1997-06-03 | 1999-09-21 | Ultratech Stepper, Inc. | Method of making a side alignment mark |
US5952241A (en) * | 1997-09-03 | 1999-09-14 | Vlsi Technology, Inc. | Method and apparatus for improving alignment for metal masking in conjuction with oxide and tungsten CMP |
CN101094565A (zh) * | 1997-12-11 | 2007-12-26 | 伊比登株式会社 | 多层印刷电路板的制造方法 |
JPH11330316A (ja) | 1998-05-19 | 1999-11-30 | Nec Tohoku Ltd | 電子部品 |
US6317026B1 (en) * | 1998-06-12 | 2001-11-13 | Michael L Brodine | Vehicle part identification system and method |
US6631551B1 (en) * | 1998-06-26 | 2003-10-14 | Delphi Technologies, Inc. | Method of forming integral passive electrical components on organic circuit board substrates |
JP2001022099A (ja) | 1999-07-08 | 2001-01-26 | Adtec Engineeng Co Ltd | 露光装置 |
JP2001135941A (ja) | 1999-08-26 | 2001-05-18 | Matsushita Electric Works Ltd | プリント配線板の製造方法 |
US6317023B1 (en) * | 1999-10-15 | 2001-11-13 | E. I. Du Pont De Nemours And Company | Method to embed passive components |
JP3964085B2 (ja) | 1999-12-09 | 2007-08-22 | 大日本印刷株式会社 | プリント配線基板、及びプリント配線基板の製造方法 |
EP2315510A3 (en) | 2001-06-05 | 2012-05-02 | Dai Nippon Printing Co., Ltd. | Wiring board provided with passive element |
JP2003131401A (ja) | 2001-10-26 | 2003-05-09 | Adtec Engineeng Co Ltd | 多層回路基板製造におけるマーキング装置 |
US6860000B2 (en) | 2002-02-15 | 2005-03-01 | E.I. Du Pont De Nemours And Company | Method to embed thick film components |
-
2003
- 2003-11-20 US US10/718,044 patent/US7178229B2/en not_active Expired - Fee Related
-
2004
- 2004-11-15 JP JP2004331013A patent/JP4551191B2/ja not_active Expired - Fee Related
- 2004-11-18 KR KR1020040094522A patent/KR100687689B1/ko not_active IP Right Cessation
- 2004-11-19 EP EP04027548A patent/EP1534051B1/en not_active Expired - Fee Related
- 2004-11-19 TW TW093135517A patent/TWI347808B/zh not_active IP Right Cessation
- 2004-11-19 CN CNB2004100997308A patent/CN100536636C/zh not_active Expired - Fee Related
-
2005
- 2005-12-29 US US11/321,934 patent/US7586198B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08155796A (ja) * | 1994-11-30 | 1996-06-18 | Seikosha Co Ltd | X線を用いた穴明け方法及びx線穴明け装置 |
JP2000013023A (ja) * | 1998-06-19 | 2000-01-14 | Matsushita Electric Ind Co Ltd | 多層プリント配線板の製造方法 |
JP2001035946A (ja) * | 1999-07-23 | 2001-02-09 | Matsushita Electric Ind Co Ltd | 電子部品、この電子部品の認識方法およびこの電子部品を用いた電子機器 |
JP2001244638A (ja) * | 1999-12-20 | 2001-09-07 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュール及びその製造方法 |
JP2003092460A (ja) * | 2001-06-05 | 2003-03-28 | Dainippon Printing Co Ltd | 受動素子を備えた配線板の製造方法、受動素子を備えた配線板 |
Also Published As
Publication number | Publication date |
---|---|
US7586198B2 (en) | 2009-09-08 |
EP1534051B1 (en) | 2012-12-26 |
KR100687689B1 (ko) | 2007-03-02 |
CN100536636C (zh) | 2009-09-02 |
US7178229B2 (en) | 2007-02-20 |
KR20050049366A (ko) | 2005-05-25 |
TWI347808B (en) | 2011-08-21 |
JP2005159345A (ja) | 2005-06-16 |
EP1534051A1 (en) | 2005-05-25 |
US20050111206A1 (en) | 2005-05-26 |
TW200527993A (en) | 2005-08-16 |
US20060101639A1 (en) | 2006-05-18 |
CN1652665A (zh) | 2005-08-10 |
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