JP4527746B2 - 同期形半導体メモリ装置のためのカラム選択ライン制御回路 - Google Patents
同期形半導体メモリ装置のためのカラム選択ライン制御回路 Download PDFInfo
- Publication number
- JP4527746B2 JP4527746B2 JP2007098645A JP2007098645A JP4527746B2 JP 4527746 B2 JP4527746 B2 JP 4527746B2 JP 2007098645 A JP2007098645 A JP 2007098645A JP 2007098645 A JP2007098645 A JP 2007098645A JP 4527746 B2 JP4527746 B2 JP 4527746B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- column
- csl
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Description
120 ローディコーダ
140 I/Oゲート回路
160 アドレスバッファ
180A カラムプレーディコーダ
200A カラムメーンディコーダ
230 クロックバッファー
280 データI/Oバッファ
300 CSLタイミング制御器
Claims (3)
- 列アドレス信号をプレーディコーディングし、制御信号に応答して活性化または非活性化される列プレーディコーダと、
前記プレーディコーディングされた列アドレス信号に応答して、列選択ラインを選択的に駆動させるための列選択ラインと連結された列メーンディコーダと、
基準クロック信号に同期して前記列プレーディコーダを活性化または非活性化させるための前記制御信号を発生する制御回路とを含み、
前記制御回路は、
前記制御信号をラッチするためのラッチ回路と、
前記基準クロック信号を所定の時間遅延させた初期化信号を発生して、前記ラッチ回路にラッチされた前記制御信号を非活性化させる初期化回路と、
前記基準クロック信号を所定の時間遅延させた設定信号を発生して、前記ラッチ回路にラッチされた前記制御信号を活性化させる設定回路とを含み、
前記初期化回路は、
直列で連結された奇数個のインバータで構成された第1遅延回路と、
前記遅延回路に接続された第1入力端子、電源電圧が印加される第2入力端子、及び前記初期化信号を出力する出力端子を有する第1ロジック回路とを含み、
前記設定回路は、
直列で連結された偶数個のインバータで構成された第2遅延回路と、
前記遅延回路に接続された第1入力端子、アドレスコーディング時点を示す信号が印加される第2入力端子、及び前記設定信号を出力する出力端子を有する第2ロジック回路とを含み、
前記設定回路の遅延時間は、前記初期化回路の遅延時間より長い
ことを特徴とする半導体メモリ装置。 - 前記制御回路は、前記初期化信号、前記設定信号を受け入れる入力端子、及び前記制御信号を出力する出力端子を有するフリップフロップを含む
ことを特徴とする請求項1に記載の半導体メモリ装置。 - 前記フリップフロップは、NORゲートを有するラッチロジックを含む
ことを特徴とする請求項2に記載の半導体メモリ装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970074207A KR100266899B1 (ko) | 1997-12-26 | 1997-12-26 | 동기형 메모리 장치 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10371517A Division JPH11250664A (ja) | 1997-12-26 | 1998-12-25 | 同期形半導体メモリ装置のためのカラム選択ライン制御回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007184106A JP2007184106A (ja) | 2007-07-19 |
JP4527746B2 true JP4527746B2 (ja) | 2010-08-18 |
Family
ID=19528709
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10371517A Pending JPH11250664A (ja) | 1997-12-26 | 1998-12-25 | 同期形半導体メモリ装置のためのカラム選択ライン制御回路 |
JP2007098645A Expired - Fee Related JP4527746B2 (ja) | 1997-12-26 | 2007-04-04 | 同期形半導体メモリ装置のためのカラム選択ライン制御回路 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10371517A Pending JPH11250664A (ja) | 1997-12-26 | 1998-12-25 | 同期形半導体メモリ装置のためのカラム選択ライン制御回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6064622A (ja) |
JP (2) | JPH11250664A (ja) |
KR (1) | KR100266899B1 (ja) |
TW (1) | TW418396B (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5835441A (en) * | 1997-08-21 | 1998-11-10 | Micron Technology, Inc. | Column select latch for SDRAM |
JP3259701B2 (ja) * | 1998-12-24 | 2002-02-25 | 日本電気株式会社 | 半導体記憶装置 |
DE19900802C1 (de) * | 1999-01-12 | 2000-03-23 | Siemens Ag | Integrierter Speicher |
KR100287189B1 (ko) * | 1999-04-07 | 2001-04-16 | 윤종용 | 활성화된 다수개의 워드라인들이 순차적으로 디세이블되는 반도체 메모리장치 |
KR100351048B1 (ko) * | 1999-04-27 | 2002-09-09 | 삼성전자 주식회사 | 데이터 입출력 라인의 부하를 최소화하는 칼럼 선택 회로, 이를 구비하는 반도체 메모리 장치 |
KR100322181B1 (ko) * | 1999-12-30 | 2004-09-07 | 주식회사 하이닉스반도체 | 칼럼 경로 액세스 제어회로를 구비한 반도체 메모리 장치 |
JP4345204B2 (ja) * | 2000-07-04 | 2009-10-14 | エルピーダメモリ株式会社 | 半導体記憶装置 |
KR100396882B1 (ko) * | 2000-10-24 | 2003-09-02 | 삼성전자주식회사 | 칼럼 선택 라인 인에이블 시점을 조절하기 위한 칼럼어드레스디코더와 디코딩 방법 및 칼럼 어드레스 디코더를구비하는 반도체 메모리 장치 |
JP4049297B2 (ja) * | 2001-06-11 | 2008-02-20 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
KR100416622B1 (ko) * | 2002-04-27 | 2004-02-05 | 삼성전자주식회사 | 동기식 반도체 메모리장치의 컬럼 디코더 인에이블 타이밍제어방법 및 장치 |
KR100568253B1 (ko) * | 2003-12-01 | 2006-04-07 | 삼성전자주식회사 | 반도체 메모리 장치 및 그의 기입 제어 방법 |
US7009911B2 (en) * | 2004-07-09 | 2006-03-07 | Micron Technology, Inc. | Memory array decoder |
KR100674981B1 (ko) * | 2005-07-02 | 2007-01-29 | 삼성전자주식회사 | 칼럼선택 라인을 개선한 반도체 메모리 장치 및 그구동방법 |
KR20080029573A (ko) * | 2006-09-29 | 2008-04-03 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR100878313B1 (ko) * | 2007-06-11 | 2009-01-14 | 주식회사 하이닉스반도체 | 데이터 입출력 라인 제어 회로 및 이를 포함하는 반도체집적 회로 |
KR20130132044A (ko) * | 2012-05-25 | 2013-12-04 | 에스케이하이닉스 주식회사 | 컬럼 선택 신호 생성 회로 |
TW201621670A (zh) | 2014-09-06 | 2016-06-16 | Neo半導體股份有限公司 | 非揮發性記憶體之多頁編程寫入方法與裝置 |
US10720215B2 (en) | 2014-09-06 | 2020-07-21 | Fu-Chang Hsu | Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming |
US9761310B2 (en) | 2014-09-06 | 2017-09-12 | NEO Semiconductor, Inc. | Method and apparatus for storing information using a memory able to perform both NVM and DRAM functions |
KR20190070158A (ko) * | 2017-12-12 | 2019-06-20 | 에스케이하이닉스 주식회사 | 어드레스 디코더 및 이를 포함하는 반도체 메모리 장치 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08139573A (ja) * | 1994-11-08 | 1996-05-31 | Hitachi Ltd | ワンショットパルス発生回路 |
JP3380828B2 (ja) * | 1995-04-18 | 2003-02-24 | 松下電器産業株式会社 | 半導体メモリ装置 |
JPH10106263A (ja) * | 1996-09-27 | 1998-04-24 | Oki Electric Ind Co Ltd | デコーダ回路 |
US5898637A (en) * | 1997-01-06 | 1999-04-27 | Micron Technology, Inc. | System and method for selecting shorted wordlines of an array having dual wordline drivers |
US5933376A (en) * | 1997-02-28 | 1999-08-03 | Lucent Technologies Inc. | Semiconductor memory device with electrically programmable redundancy |
-
1997
- 1997-12-26 KR KR1019970074207A patent/KR100266899B1/ko not_active IP Right Cessation
-
1998
- 1998-12-16 TW TW087120927A patent/TW418396B/zh not_active IP Right Cessation
- 1998-12-25 JP JP10371517A patent/JPH11250664A/ja active Pending
- 1998-12-28 US US09/221,827 patent/US6064622A/en not_active Expired - Lifetime
-
2007
- 2007-04-04 JP JP2007098645A patent/JP4527746B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6064622A (en) | 2000-05-16 |
TW418396B (en) | 2001-01-11 |
JPH11250664A (ja) | 1999-09-17 |
KR100266899B1 (ko) | 2000-10-02 |
KR19990054395A (ko) | 1999-07-15 |
JP2007184106A (ja) | 2007-07-19 |
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