JP4500558B2 - 絶縁ゲート型半導体装置の製造方法 - Google Patents
絶縁ゲート型半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 92
- 238000004519 manufacturing process Methods 0.000 title claims description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 38
- 229920005591 polysilicon Polymers 0.000 claims description 38
- 239000012212 insulator Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 22
- 230000008021 deposition Effects 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000010408 film Substances 0.000 description 173
- 238000001039 wet etching Methods 0.000 description 25
- 210000000746 body region Anatomy 0.000 description 23
- 238000001312 dry etching Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
Description
第1の形態に係る絶縁ゲート型半導体装置100(以下,「半導体装置100」とする)は,図1の断面図に示す構造を有している。なお,本明細書においては,出発基板と,出発基板上にエピタキシャル成長により形成した単結晶シリコンの部分とを合わせた全体を半導体基板と呼ぶこととする。
以下,第2の形態の製造方法について,図5を基に説明する。第2の形態では,くさび状の溝233に蓋をするために被覆性が良い膜を使用する。この点,被覆性が悪い膜でカバー絶縁膜241を形成した第1の形態と異なる。なお,N+ ドレイン領域11上にエピタキシャル層を有する半導体基板(図2参照)を作製する手順は,第1の形態と同様である。また,本形態の製造方法では,その半導体基板に対し,第1の形態の製造方法で示した図3(A)から(E)までの工程を行う。すなわち,図5(E)に示すようにゲートトレンチ21内に絶縁物23が堆積しているとともにその堆積絶縁層23にはくさび状の溝233が形成されている。また,ゲートトレンチ21の側壁には酸化膜24が形成されている。
以下,第3の形態の製造方法について,図6および図7を基に説明する。第3の形態では,くさび状の溝233を絶縁物で充填した後にゲート酸化膜24を形成する。この点,ゲート酸化膜24を形成した後にくさび状の溝233を充填する第2の形態と異なる。なお,N+ ドレイン領域11上にエピタキシャル層を有する半導体基板(図2参照)を作製するまでの手順は,第1の形態と同様である。本形態の製造方法では,その半導体基板に対し,第1の形態の製造方法で示した図3(A)ないし(B)の工程を行う。すなわち,図6(B)に示すようにゲートトレンチ21内が絶縁物23で充填されており,幅方向の中央部分にシーム234が生じている。
以下,第4の形態の製造方法について,図8および図9を基に説明する。第4の形態では,シームを形成することなくゲートトレンチ21を絶縁物で充填する。この点,絶縁体積層23に必ずシームが発生する他の形態と異なる。なお,N+ ドレイン領域11上にエピタキシャル層を有する半導体基板(図2参照)を作製するまでの手順は,第1の形態と同様である。
第5の形態に係る絶縁ゲート型半導体装置200(以下,「半導体装置200」とする)は,図10の断面図に示す構造を有している。本形態の半導体装置200の特徴は,N- ドリフト領域12中にPフローティング領域51を設けている点である。なお,図10中,図1で示した半導体装置100と同一記号の構成要素は,その構成要素と同一機能を有するものである。
以下,ゲートトレンチ21内に絶縁膜23を確実に埋め込む方法について説明する。絶縁膜23を確実に埋め込む方法としては,大別してハードマスクを除去する方法と除去しない方法とがある。
12 N- ドリフト領域(ドリフト領域)
21 トレンチ(トレンチ部)
22 ゲート電極(導体層)
23 堆積絶縁層(堆積絶縁層)
233 くさび状の溝
234 シーム
24 ゲート絶縁膜
241 被覆性が悪いカバー絶縁膜(カバー絶縁層)
242 空洞
243 被覆性が良いカバー絶縁膜(カバー絶縁層)
31 N+ ソース領域
41 P- ボディ領域(ボディ領域)
51 Pフローティング領域(フローティング領域)
90 ハードマスク
100 絶縁ゲート型半導体装置
Claims (2)
- トレンチ部と,前記トレンチ部内に位置し絶縁物を堆積してなる堆積絶縁層と,前記トレンチ部内であって前記堆積絶縁層の上方に位置する導体層とを有する絶縁ゲート型半導体装置の製造方法において,
半導体基板の上面からトレンチ部を形成するトレンチ部形成工程と,
前記トレンチ部形成工程にてトレンチ部を形成した後に,そのトレンチ部の表面上に,そのトレンチ部の幅の半分の長さよりも薄い膜厚となるように絶縁物を堆積する絶縁物堆積工程と,
前記絶縁物堆積工程にて絶縁層を形成した後に,その絶縁層上にポリシリコンを堆積し,その後にそのポリシリコンを酸化することでトレンチ部内に堆積絶縁層を形成する堆積絶縁層形成工程と,
前記堆積絶縁層形成工程にて堆積絶縁層を形成した後に,トレンチ部内の堆積絶縁層の一部を除去するエッチバック工程と,
前記エッチバック工程にて堆積絶縁層の一部を除去した後に,その残った堆積絶縁層上に導体層を形成する導体層形成工程とを含むことを特徴とする絶縁ゲート型半導体装置の製造方法。 - 請求項1に記載する絶縁ゲート型半導体装置の製造方法において,
前記トレンチ部形成工程の後であって前記絶縁物堆積工程の前に,前記トレンチ部形成工程にて形成されたトレンチ部の底部から不純物を注入することでフローティング領域を形成するフローティング領域形成工程とを含むことを特徴とする絶縁ゲート型半導体装置の製造方法。
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Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006066611A (ja) * | 2004-08-26 | 2006-03-09 | Toshiba Corp | 半導体装置 |
KR100683089B1 (ko) | 2005-08-24 | 2007-02-15 | 삼성전자주식회사 | 리세스된 게이트 구조물, 리세스된 게이트 구조물의 형성방법, 리세스된 게이트 구조물을 포함하는 반도체 장치 및그 제조 방법 |
EP1883116B1 (en) * | 2006-07-26 | 2020-03-11 | Semiconductor Components Industries, LLC | Semiconductor device with high breakdown voltage and manufacturing method thereof |
US7381618B2 (en) * | 2006-10-03 | 2008-06-03 | Power Integrations, Inc. | Gate etch process for a high-voltage FET |
US8981384B2 (en) * | 2010-08-03 | 2015-03-17 | Sumitomo Electric Industries, Ltd. | Semiconductor device and method for manufacturing same |
WO2013001677A1 (ja) | 2011-06-28 | 2013-01-03 | パナソニック株式会社 | 半導体装置とその製造方法 |
JP5699878B2 (ja) | 2011-09-14 | 2015-04-15 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
JP2013069964A (ja) | 2011-09-26 | 2013-04-18 | Sumitomo Electric Ind Ltd | 炭化珪素半導体装置 |
JP5764046B2 (ja) | 2011-11-21 | 2015-08-12 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
JP2013122953A (ja) | 2011-12-09 | 2013-06-20 | Toyota Motor Corp | 半導体装置 |
JP5602256B2 (ja) * | 2013-01-11 | 2014-10-08 | 株式会社東芝 | 半導体装置の製造方法 |
JP6426642B2 (ja) * | 2016-03-08 | 2018-11-21 | 株式会社東芝 | 半導体装置 |
CN109379915B (zh) * | 2018-11-20 | 2021-08-17 | 合肥智慧龙机械设计有限公司 | 一种智能化离合拖拽装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05506335A (ja) * | 1991-01-31 | 1993-09-16 | シリコニックス・インコーポレイテッド | 電力用mos電界効果トランジスタ |
JPH077149A (ja) * | 1993-01-04 | 1995-01-10 | Texas Instr Inc <Ti> | 高特性高電圧の垂直形トランジスタとその製造法 |
US6194741B1 (en) * | 1998-11-03 | 2001-02-27 | International Rectifier Corp. | MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance |
JP2004014696A (ja) * | 2002-06-05 | 2004-01-15 | Denso Corp | 半導体装置の製造方法 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05506335A (ja) * | 1991-01-31 | 1993-09-16 | シリコニックス・インコーポレイテッド | 電力用mos電界効果トランジスタ |
JPH077149A (ja) * | 1993-01-04 | 1995-01-10 | Texas Instr Inc <Ti> | 高特性高電圧の垂直形トランジスタとその製造法 |
US6194741B1 (en) * | 1998-11-03 | 2001-02-27 | International Rectifier Corp. | MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance |
JP2004014696A (ja) * | 2002-06-05 | 2004-01-15 | Denso Corp | 半導体装置の製造方法 |
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