JP4496529B2 - 多層セラミック基板の製造方法及び多層セラミック基板 - Google Patents

多層セラミック基板の製造方法及び多層セラミック基板 Download PDF

Info

Publication number
JP4496529B2
JP4496529B2 JP2004168219A JP2004168219A JP4496529B2 JP 4496529 B2 JP4496529 B2 JP 4496529B2 JP 2004168219 A JP2004168219 A JP 2004168219A JP 2004168219 A JP2004168219 A JP 2004168219A JP 4496529 B2 JP4496529 B2 JP 4496529B2
Authority
JP
Japan
Prior art keywords
multilayer ceramic
glass
ceramic substrate
substrate
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2004168219A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005347674A (ja
JP2005347674A5 (enExample
Inventor
平吉 種井
耕司 市川
到 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Proterial Ltd
Original Assignee
Hitachi Metals Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Metals Ltd filed Critical Hitachi Metals Ltd
Priority to JP2004168219A priority Critical patent/JP4496529B2/ja
Publication of JP2005347674A publication Critical patent/JP2005347674A/ja
Publication of JP2005347674A5 publication Critical patent/JP2005347674A5/ja
Application granted granted Critical
Publication of JP4496529B2 publication Critical patent/JP4496529B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2004168219A 2004-06-07 2004-06-07 多層セラミック基板の製造方法及び多層セラミック基板 Expired - Lifetime JP4496529B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004168219A JP4496529B2 (ja) 2004-06-07 2004-06-07 多層セラミック基板の製造方法及び多層セラミック基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004168219A JP4496529B2 (ja) 2004-06-07 2004-06-07 多層セラミック基板の製造方法及び多層セラミック基板

Publications (3)

Publication Number Publication Date
JP2005347674A JP2005347674A (ja) 2005-12-15
JP2005347674A5 JP2005347674A5 (enExample) 2007-07-05
JP4496529B2 true JP4496529B2 (ja) 2010-07-07

Family

ID=35499730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004168219A Expired - Lifetime JP4496529B2 (ja) 2004-06-07 2004-06-07 多層セラミック基板の製造方法及び多層セラミック基板

Country Status (1)

Country Link
JP (1) JP4496529B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI388533B (zh) * 2007-12-11 2013-03-11 Murata Manufacturing Co Manufacturing method of ceramic molded body
CN101909837B (zh) * 2008-01-11 2012-11-14 株式会社村田制作所 陶瓷成形体的制造方法
JP2009252929A (ja) * 2008-04-04 2009-10-29 Panasonic Corp セラミック多層デバイスとその製造方法
JP5377885B2 (ja) * 2008-05-16 2013-12-25 日本特殊陶業株式会社 セラミック基板の製造方法
JP2011210828A (ja) * 2010-03-29 2011-10-20 Tdk Corp 薄膜回路形成用基板、薄膜回路部品及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01252548A (ja) * 1987-12-28 1989-10-09 Asahi Glass Co Ltd ガラスセラミックス組成物
EP0511301B1 (en) * 1990-01-18 1994-12-28 E.I. Du Pont De Nemours And Company Method for reducing shrinkage during firing of green ceramic bodies
US5254191A (en) * 1990-10-04 1993-10-19 E. I. Du Pont De Nemours And Company Method for reducing shrinkage during firing of ceramic bodies
JP2002084065A (ja) * 2000-09-07 2002-03-22 Murata Mfg Co Ltd 多層セラミック基板およびその製造方法ならびに電子装置
JP2003332741A (ja) * 2002-05-14 2003-11-21 Murata Mfg Co Ltd セラミック多層基板の製造方法

Also Published As

Publication number Publication date
JP2005347674A (ja) 2005-12-15

Similar Documents

Publication Publication Date Title
JP5263226B2 (ja) 多層セラミック基板およびその製造方法
JP4557417B2 (ja) 低温焼成セラミック配線基板の製造方法
JPWO2005039263A1 (ja) 多層セラミック基板及びその製造方法並びにこれを用いた電子機器
CN100556244C (zh) 多层陶瓷基板以及使用了它的电子机器
US8231961B2 (en) Low temperature co-fired ceramic material, low temperature co-fired ceramic body, and multilayer ceramic substrate
JP6728859B2 (ja) セラミック基板およびその製造方法
JP4496529B2 (ja) 多層セラミック基板の製造方法及び多層セラミック基板
CN102753502B (zh) 陶瓷烧结体及其制造方法
JP4029408B2 (ja) 難焼結性拘束用グリーンシート及び多層セラミック基板の製造方法
JP4688460B2 (ja) コンデンサ内蔵ガラスセラミック多層配線基板
JP2005285968A (ja) コンデンサ内蔵ガラスセラミック多層配線基板
JP4110536B2 (ja) 多層セラミック集合基板および多層セラミック集合基板の製造方法
JP4645962B2 (ja) 多層セラミック基板
JP4658465B2 (ja) コンデンサ内蔵ガラスセラミック多層配線基板
JP3850245B2 (ja) ガラスセラミック基板の製造方法
JP5110419B2 (ja) Ａｇ粉末、導体ペースト及び多層セラミック基板とその製造方法
JP2009181987A (ja) セラミック多層基板の製造方法
JP2002368421A (ja) 多層セラミック基板の製造方法および多層セラミック基板
JP4530864B2 (ja) コンデンサ内蔵配線基板
JP3850243B2 (ja) ガラスセラミック基板の製造方法
JP3872325B2 (ja) ガラスセラミック基板の製造方法
JP5533120B2 (ja) 多層セラミック基板の製造方法
JP3990535B2 (ja) ガラスセラミック基板の製造方法
JP2005277162A (ja) 電子部品の製造方法
JP2005123460A (ja) 多層セラミック基板の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070517

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070517

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091009

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091208

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100319

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100401

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130423

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4496529

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140423

Year of fee payment: 4

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term