JP4494525B1 - 誘電体膜の製造方法、半導体装置の製造方法、誘電体膜、およびコンピュータ読み取り可能な記録媒体 - Google Patents
誘電体膜の製造方法、半導体装置の製造方法、誘電体膜、およびコンピュータ読み取り可能な記録媒体 Download PDFInfo
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- JP4494525B1 JP4494525B1 JP2009549325A JP2009549325A JP4494525B1 JP 4494525 B1 JP4494525 B1 JP 4494525B1 JP 2009549325 A JP2009549325 A JP 2009549325A JP 2009549325 A JP2009549325 A JP 2009549325A JP 4494525 B1 JP4494525 B1 JP 4494525B1
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Abstract
【選択図】図7
Description
特許文献1に記載のZrO2にAlを5〜30%の範囲で含有させる技術では、非晶質構造で比誘電率が25〜28と高い値が得られるが、結晶構造を有するZrO2の比誘電率値30よりも低下してしまうという課題が生じる。
を有する半導体装置の製造方法であって、前記絶縁膜を、上記第1の態様に記載の方法により形成することを特徴とする。
de=dh×(εo/εh)・・・(1)
<実施例1(コスパッタによる実施例)>
本発明の第1の実施例を、図面を参照しながら詳細に説明する。
図18は、本発明の方法により形成された誘電体膜を有するMISキャパシタを示した図である。図2に示すような本実施例に係る基板処理装置は、表面に膜厚3nm〜5nmのシリコン酸化膜302を有するシリコン基板301に、スパッタリング法により非晶質構造を有するHfAlON膜303を堆積した。ターゲット106、126としては、HfおよびAlの金属ターゲットを用い、スパッタガスとしてアルゴンおよび酸素および窒素を用いた。
ここでは、物理蒸着機構を制御し、基板温度30℃、Tiのターゲットパワー750W、スパッタガス圧0.03Pa、Arガス流量30sccm、窒素ガス流量10sccmとして成膜を行った。
本発明の第2の実施例を、図面を参照しながら詳細に説明する。
図19は、本発明の第2の実施例である半導体装置の製造方法の工程を示した図である。
まず、本実施例に係る基板処理装置は、図19の工程1に示すようにシリコン基板401の表面にSTI(Shallow Trench Isolation)技術を用いて素子分離領域402を形成した。続いて、本実施例に係る基板処理装置は、素子分離されたシリコン基板401表面に熱酸化法により膜厚1.8nmのシリコン酸化膜403を形成する。その後、本実施例に係る基板処理装置は、実施例1と同じ方法によりHfAlON膜を膜厚1nm〜10nmの範囲で形成する。続いて、本実施例に係る基板処理装置は、窒素雰囲気中で1000℃、10secのアニール処理を行い、HfAlON膜を結晶化させ、誘電体膜404とした。
図20は本発明の第3の実施例に関わる半導体素子の作製工程を示した断面図である。
まず本実施例に係る基板処理装置は、図20の工程1に示すようにシリコン基板501の表面にSTI(Shallow Trench Isolation)技術を用いて素子分離領域502を形成した。続いて、本実施例に係る基板処理装置は、素子分離されたシリコン基板501表面に、第1の絶縁膜503としてシリコン酸化膜を熱酸化膜法により30Å〜100Å形成する。続いて、本実施例に係る基板処理装置は、第2の絶縁膜504としてシリコン窒化膜をLPCVD(Low Pressure Chemical Vapor Deposition)法により30Å〜100Å形成する。続いて、本実施例に係る基板処理装置は、第3の絶縁膜505として、酸化アルミニウム膜を5Å〜50Å形成する。酸化アルミニウム膜は、MOCVD法、ALD(Atomic Layer Deposition)法、PVD(Physical Vapor Deposition)法を用いてもよい。続いて、本実施例に係る基板処理装置は、第4の絶縁膜506として、実施例1と同じ方法によりHfAlON膜を膜厚5nm〜20nmの範囲で形成する。続いて、本実施例に係る基板処理装置は、第5の絶縁膜507として、酸化アルミニウム膜を5Å〜50Å形成する。形成方法は、MOCVD法、ALD法、PVD法を用いて形成する。
本発明の第4の実施例を、図面を参照しながら詳細に説明する。
図21は、本発明の第4の実施例である半導体装置の断面図を示した図である。本実施例は、実施例3における半導体素子の第2の絶縁膜504をpoly−Si601からなる層で形成する点で、実施例3と異なる。第2の絶縁膜504以降の形成工程は、実施例3と同一である。
図22において、基板処理装置301は、上述した実施例1〜4に係る基板処理装置とすることができる。従って、制御機構300は、プロセッサ300dが、記憶部300cに格納された制御プログラムを実行することで、基板処理装置301の動作を制御することができる。すなわち、制御機構301の制御により、基板処理装置301は、上述した実施例1〜6に記載した動作を行うことができる。
なお、制御機構300は、基板処理装置301と別個に設けても良いし、基板処理装置301に内蔵しても良い。
かかる記憶媒体としてはたとえばフロッピー(登録商標)ディスク、ハードディスク、光ディスク、光磁気ディスク、CD−ROM、磁気テープ、不揮発性メモリカード、ROMを用いることができる。
Claims (13)
- 基板上に、HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む誘電体膜の形成方法であって、
A元素とB元素とNのモル比率B/(A+B+N)が0.015≦(B/(A+B+N))≦0.095であり、かつN/(A+B+N)が0.045≦(N/(A+B+N))であり、かつA元素とOのモル比率O/Aが1.0<(O/A)<2.0の間で表され、非晶質構造を有する金属酸窒化物を形成する工程と、
該非晶質構造を有する金属酸窒化物に700℃以上のアニール処理を施し、立方晶の混入割合が80%以上の結晶相を含む金属酸窒化物を形成する工程と、
を備えたことを特徴とする誘電体膜の製造方法。 - 前記非晶質構造を有する金属酸窒化物を形成する工程が、
真空容器内で、酸素と窒素の混合ガスからなる反応性ガスと不活性ガスとの混合雰囲気下において前記金属酸窒化物層を構成する金属ターゲットをマグネトロンスパッタする工程であり、
前記反応性ガスの供給量を、前記金属酸窒化物のA元素とOのモル比率O/Aが1.0<(O/A)<2.0の範囲となるように設定することを特徴とする請求項1に記載の誘電体膜の製造方法。 - 前記反応性ガスの供給量を、前記金属ターゲットの表面が酸化することにより生じるスパッタ率の低下率が最大となる供給量以下に設定することを特徴とする請求項2に記載の誘電体膜の製造方法。
- 前記真空容器内の圧力を1×10-1Pa以下に設定することを特徴とする請求項2に記載の誘電体膜の製造方法。
- 前記誘電体膜の比誘電率が40以上であることを特徴とする請求項1に記載の誘電体膜の製造方法。
- 絶縁体膜として誘電体膜を有する半導体装置の製造方法であって、
前記誘電体膜を、請求項1に記載の方法により形成することを特徴とする半導体装置の製造方法。 - 少なくとも表面が半導体層を含む基板と、
前記基板上に形成されたゲート電極と、
前記基板と前記ゲート電極の間に順次積層された積層型ゲート絶縁膜を有する不揮発性半導体装置の製造方法であって、
前記積層型ゲート絶縁膜を構成する絶縁膜の少なくとも一層を、請求項1に記載の方法により形成することを特徴とする半導体装置の製造方法。 - 少なくとも表面が半導体層を含む基板と、
前記基板上に形成されたゲート電極と、
前記基板と前記ゲート電極の間に絶縁膜と浮遊電極と絶縁膜とが順次積層された構造を有する不揮発性半導体装置の製造方法であって、
前記ゲート電極と前記浮遊電極との間に形成される絶縁膜の少なくとも一部を、請求項1に記載の方法により形成することを特徴とする半導体装置の製造方法。 - 少なくとも表面が半導体層を含む基板上に、
ソース領域と、
ドレイン領域と、
絶縁膜を介して形成されてゲート電極と、
を有する半導体装置の製造方法であって、
前記絶縁膜を、請求項1に記載の方法により形成することを特徴とする半導体装置の製造方法。 - HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む誘電体膜であって、
A元素とB元素とNのモル比率B/(A+B+N)が0.015≦(B/(A+B+N))≦0.095であり、かつN/(A+B+N)が0.045≦(N/(A+B+N))であり、かつA元素とOのモル比率O/Aが1.0<(O/A)<2.0であることを特徴とする誘電体膜。 - コンピュータに、高誘電体膜を含むMISキャパシタの、該高誘電体膜の形成方法を実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体であって、
前記形成方法は、
HfもしくはHfとZrを含有する金属ターゲット及びAlの金属ターゲットを用いた物理蒸着により、シリコン酸化膜を有するシリコン基板上に、HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む誘電体膜を堆積する工程であって、A元素とOのモル比率O/Aが1.0<(O/A)<2.0の範囲になるように酸素供給量を設定し、前記誘電体膜を堆積する第1の工程と、
前記誘電体膜上に、金属ターゲットを用いた物理蒸着により、TiN膜、Ti、TaN、W、Pt、Ru、Al、Si、のうちから選択される膜を堆積する第2の工程と、
前記第1の工程又は前記2の工程の後、アニール処理を行い前記誘電体膜を結晶化させる第3の工程と
を有することを特徴とするコンピュータ読み取り可能な記録媒体。 - コンピュータに、高誘電体膜を含むMOSFETの形成方法を実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体であって、
前記形成方法は、
STIにより、シリコン基板上に、素子分離領域を形成する第1の工程と、
前記素子分離されたシリコン基板上に熱酸化法により、シリコン酸化膜を形成する第2の工程と、
前記シリコン酸化膜上に、Hf及びAlの金属ターゲットを用いた物理蒸着により、HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む誘電体膜を堆積する工程であって、A元素とOのモル比率O/Aが1.0<(O/A)<2.0の範囲になるように酸素供給量を設定し、前記誘電体膜を堆積する第3の工程と、
前記誘電体膜上にゲート電極膜を形成する第4の工程と、
リソグラフィーとRIEを用いて、前記ゲート電極膜を加工する第5の工程と、
イオン注入を行い、前記加工されたゲート電極膜をマスクとして、エクステンション領域を形成する第6の工程と、
前記エクステンション領域が形成されたシリコン基板上に、シリコン窒化膜とシリコン酸化膜とを堆積する第7の工程と、
前記堆積されたシリコン窒化膜とシリコン酸化膜とをエッチバックすることにより、ゲート側壁を形成する第8の工程と、
イオン注入を行い、前記エクステンション領域の下にソース・ドレイン領域を形成する第9の工程と
を有することを特徴とするコンピュータ読み取り可能な記録媒体。 - コンピュータに、高誘電体膜を含む不揮発メモリ素子又はFG型不揮発性半導体素子の形成方法を実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体であって、
前記形成方法は、
STIにより、シリコン基板上に、素子分離領域を形成する第1の工程と、
前記素子分離されたシリコン基板上に熱酸化法により、第1の絶縁膜を形成する第2の工程と、
前記第1の絶縁膜上に、LPCVDにより、第2の絶縁膜を形成する第3の工程と、
前記第2の絶縁膜上に、MOCVD、ALD、PVDのいずれかを使用して、第3の絶縁膜を形成する第4の工程と、
前記第3の絶縁膜上に、Hf及びAlの金属ターゲットを用いた物理蒸着により、HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む、第4の絶縁膜である高誘電体膜を堆積する工程であって、A元素とOのモル比率O/Aが1.0<(O/A)<2.0の範囲になるように酸素供給量を設定し、前記第4の絶縁膜である高誘電体膜を形成する第5の工程と、
前記第4の絶縁膜上に、MOCVD、ALD、PVDのいずれかを用いて、第5の絶縁膜を形成する第6の工程と、
前記第5の絶縁膜上に、ゲート電極膜を形成する第7の工程と、
リソグラフィー技術及びRIE技術を用いて、前記ゲート電極膜を加工する第8の工程と、
イオン注入を行い、前記加工されたゲート電極膜をマスクとして、エクステンション領域を形成する第9の工程と、
前記エクステンション領域が形成されたシリコン基板上に、シリコン窒化膜とシリコン酸化膜とを堆積する第10の工程と、
前記堆積されたシリコン窒化膜とシリコン酸化膜とをエッチバックすることにより、ゲート側壁を形成する第11の工程と、
イオン注入を行い、前記エクステンション領域の下にソース・ドレイン領域を形成する第12の工程と
を有することを特徴とするコンピュータ読み取り可能な記録媒体。
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US20110064642A1 (en) | 2011-03-17 |
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US7867847B2 (en) | 2011-01-11 |
KR20100085989A (ko) | 2010-07-29 |
US8178934B2 (en) | 2012-05-15 |
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