WO2010050292A1 - 誘電体膜ならびに半導体装置の製造方法、誘電体膜、および、記録媒体 - Google Patents
誘電体膜ならびに半導体装置の製造方法、誘電体膜、および、記録媒体 Download PDFInfo
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- WO2010050292A1 WO2010050292A1 PCT/JP2009/065306 JP2009065306W WO2010050292A1 WO 2010050292 A1 WO2010050292 A1 WO 2010050292A1 JP 2009065306 W JP2009065306 W JP 2009065306W WO 2010050292 A1 WO2010050292 A1 WO 2010050292A1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
- H01L21/02148—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
Definitions
- the present invention relates to a dielectric film and a method for manufacturing a semiconductor device using the dielectric film.
- the high dielectric constant film is required to have heat resistance against the annealing process at 1000 ° C. in the above-described semiconductor device manufacturing process. Further, the high dielectric constant film is required to have excellent film surface flatness in order to suppress variations in the operating voltage of the semiconductor device.
- HfO 2 , ZrO 2 , Al having a dielectric constant higher than that of a conventional SiO 2 film, SiN film, or a combination of both as a dielectric film.
- the use of 2 O 3 is being considered.
- Recently, in order to suppress the leakage current associated with the thinning of the dielectric film research on a laminated structure of HfO 2 , ZrO 2 , Al 2 O 3 and a dielectric film doped with a metal element in HfO 2 , ZrO 2 Has been done.
- Examples of the method for forming the high dielectric film include a CVD (Chemical Vapor Deposition) method, an atomic layer adsorption deposition method, and a sputtering method.
- CVD Chemical Vapor Deposition
- atomic layer adsorption deposition method atomic layer adsorption deposition
- sputtering method has a problem of forming an interface layer by plasma damage or oxidation of the substrate to be processed.
- Patent Document 1 discloses that amorphous aluminum oxide is contained in a crystalline dielectric and Al x M (1-x) O y (however, , M is a metal that can form a crystalline dielectric such as Hf and Zr), and an amorphous film having a composition of 0.05 ⁇ x ⁇ 0.3 is disclosed.
- This technique is characterized in that a high relative dielectric constant of 25 to 28 can be obtained in amorphous zircon aluminate.
- the dielectric constant of ZrO 2 is 30.
- Patent Document 2 discloses that the surface of a target is oxidized within a range in which ZrO 2 has a stoichiometric composition by sputtering using electron cyclotron resonance. A technique is disclosed in which formation is performed in an oxygen supply range in which the reduction rate of the sputtering rate generated by the above is maximized.
- Patent Document 3 discloses a dielectric film obtained by doping HfO 2 with yttrium (Y) and nitrogen as metal elements using a ceramic target of HfO 2 and Y 2 O 3 as a sputtering target. According to Patent Document 3, the addition of an element having a large atomic radius such as Y described above to monoclinic HfO 2 reduces and stabilizes the cubic agglomeration energy, so that the HfO 2 crystal system is monoclinic. It is described that the crystal changes to tetragonal or cubic. As a result, it is described that a high dielectric constant film having a relative dielectric constant of 70 can be obtained with a dielectric film made of HfYO. Furthermore, it is shown that when the oxygen in monoclinic HfO 2 is replaced with nitrogen, the crystal system changes from monoclinic to tetragonal, rhombohedral, and cubic as the amount of nitrogen increases. Yes.
- Patent Document 4 regarding a dielectric film made of Zr x Si (1-x) O (2-y) (0.81 ⁇ x ⁇ 0.99, 0.04 ⁇ y ⁇ 0.25), Zr and Si A dielectric film having a tetragonal crystal is formed by forming an amorphous film by sputtering in a mixed atmosphere of argon and oxygen using an oxygen target, and then subjecting the amorphous film to an annealing treatment at 750 ° C. or higher in an atmosphere containing oxygen. Is formed.
- Non-Patent Document 1 discloses a dielectric film in which TiN is laminated on the surface of HfO 2 formed by RF sputtering. According to the literature 3 HfO 2 having a cubic crystal phase by crystallization in a state of stacking a TiN to HfO 2 is formed, a dielectric film having a relative dielectric constant value 50 is described to be obtained.
- each of the above-described techniques has the following problems.
- the technique of including the range of 5-30% Al is ZrO 2 described in Patent Document 1, although the dielectric constant in an amorphous structure can be obtained as high as 25-28, the ZrO 2 having a crystal structure There arises a problem that the dielectric constant is lower than 30.
- the technique for forming the HfYO film described in Patent Document 3 is effective in that a relative dielectric constant value of 70 and a high dielectric constant film can be obtained.
- the sputtering method using a ceramic target made of a metal oxide of HfO 2 and Y 2 O 3 as a sputtering target has a problem that the deposition rate of the dielectric film becomes extremely slow because the sputtering rate is lowered.
- Patent Document 4 a dielectric having a tetragonal crystal structure consisting of Zr x Si (1-x) O (2-y) (0.81 ⁇ x ⁇ 0.99,0.04 ⁇ y ⁇ 0.25)
- the technique for forming a body film has a problem that the relative dielectric constant value of the obtained dielectric film is 20 to 26, which is lower than ZrO 2 described in Patent Document 1.
- Non-Patent Document 1 for forming HfO 2 having a cubic structure by crystallization in a state where TiN is laminated on the surface of HfO 2 formed by an RF sputtering method has a relative dielectric constant value of 50 and a high dielectric constant film. It is effective in that it is obtained.
- the sputtering method using a ceramic target made of HfO 2 metal oxide as the sputtering target has a problem that the deposition rate of the dielectric film becomes extremely slow because the sputtering rate is lowered.
- the present invention has been made with respect to the above-described conventional problems, and improves the above-described problems, reduces a decrease in deposition rate due to a decrease in the sputtering rate, has a high relative dielectric constant, and is annealed at 1000 ° C. It is an object of the present invention to provide a manufacturing method for forming a dielectric film excellent in heat resistance against heat and flatness of the film surface.
- the present inventors have formed a metal oxynitride having a specific composition and an amorphous structure, and further subjected to annealing treatment, whereby the relative dielectric constant is reduced.
- the inventors have found that a dielectric film having a high temperature resistance of 1000 ° C. and excellent flatness can be obtained, and the present invention has been completed.
- a first aspect of the present invention is a method for forming a dielectric film comprising a metal oxynitride containing an A element made of Hf or a mixture of Hf and Zr, a B element made of Al, and N and O on a substrate.
- the molar ratio B / (A + B + N) of A element, B element and N is 0.015 ⁇ (B / (A + B + N)) ⁇ 0.095, and N / (A + B + N) is 0.045 ⁇ ( N / (A + B + N)), and the molar ratio O / A between the element A and O is expressed as 1.0 ⁇ (O / A) ⁇ 2.0, and the metal oxynitride having an amorphous structure And a step of annealing the metal nitride having an amorphous structure at 700 ° C. or higher to form a metal oxynitride containing a crystal phase with a cubic crystal mixing ratio of 80% or more. It is characterized by having.
- a second aspect of the present invention includes a substrate having at least a surface including a semiconductor layer, a gate electrode formed on the substrate, and a stacked gate insulating film sequentially stacked between the substrate and the gate electrode.
- a substrate having at least a surface including a semiconductor layer, a gate electrode formed on the substrate, and an insulating film, a floating electrode, and an insulating film are sequentially formed between the substrate and the gate electrode.
- a method for manufacturing a nonvolatile semiconductor device having a stacked structure, wherein at least a part of an insulating film formed between the gate electrode and the floating electrode is formed by the method according to the first aspect. It is characterized by doing.
- a method of manufacturing a semiconductor device comprising: forming the insulating film by the method described in the first aspect.
- a dielectric film comprising a metal oxynitride containing an A element composed of Hf or a mixture of Hf and Zr, a B element composed of Al, and N and O,
- the molar ratio B / (A + B + N) between element B and N is 0.015 ⁇ (B / (A + B + N)) ⁇ 0.095
- N / (A + B + N) is 0.045 ⁇ (N / (A + B + N))
- the molar ratio O / A between the element A and O is 1.0 ⁇ (O / A) ⁇ 2.0.
- a computer-readable recording medium recording a program for causing a computer to execute a method for forming a high dielectric film of a MIS capacitor including the high dielectric film,
- the formation method is performed by physical vapor deposition using a metal target containing Hf or Hf and Zr and an Al metal target on a silicon substrate having a silicon oxide film, and from an A element and Al made of a mixture of Hf or Hf and Zr.
- the oxygen supply amount is set so as to be in the range of 0.0, and the TiN film, Ti, T are deposited by physical vapor deposition using a metal target on the dielectric film and the first step of depositing the dielectric film.
- a third step of crystallizing is set so as to be in the range of 0.0, and the TiN film, Ti, T are deposited by physical vapor deposition using a metal target on the dielectric film and the first step of depositing the dielectric film.
- a computer-readable recording medium having recorded thereon a program for causing a computer to execute a method for forming a MOSFET including a high dielectric film.
- depositing a dielectric film containing a metal oxynitride containing an A element made of Hf or a mixture of Hf and Zr, a B element made of Al, and N and O by physical vapor deposition using an Al metal target
- the oxygen supply amount is set so that the molar ratio O / A between the element A and O is 1.0 ⁇ (O / A) ⁇ 2.0, and the dielectric film is deposited.
- An eighth aspect of the present invention is a computer-readable recording medium recording a program for causing a computer to execute a method for forming a nonvolatile memory element or an FG type nonvolatile semiconductor element including a high dielectric film
- the forming method includes a first step of forming an element isolation region on a silicon substrate by STI, and a second step of forming a first insulating film by thermal oxidation on the element-isolated silicon substrate.
- a high dielectric film which is a fourth insulating film containing a metal oxynitride containing B element and N and O, wherein the molar ratio O / A of A element and O is 1 0.0 ⁇ (O / A) ⁇ 2.0
- a fifth step of setting the oxygen supply amount so as to form a high dielectric film as the fourth insulating film A sixth step of forming a fifth insulating film on the insulating film using any one of MOCVD, ALD, and PVD, and a seventh step of forming a gate electrode film on the fifth insulating film
- an eighth step of processing the gate electrode film using a lithography technique and an RIE technique and a ninth step of forming an extension region by performing ion implantation and using the processed gate electrode film as
- a silicon nitride film and a silicon acid are formed on the silicon substrate on which the extension region is formed.
- the dielectric film manufacturing method of the present invention is applied to a method of manufacturing a gate insulating film of a CMOS transistor element having a high temperature annealing process, a method of manufacturing a blocking insulating film of a MONOS type nonvolatile semiconductor element, and an FG type nonvolatile semiconductor element. Even when applied to a method for manufacturing an insulating film between a floating electrode and a gate electrode, it is possible to reduce the equivalent oxide thickness (EOT: Equivalent Oxide Thickness) by increasing the dielectric constant.
- EOT Equivalent Oxide Thickness
- FIG. 2 is a diagram showing a relationship between EOT and physical film thickness of the MIS capacitor of FIG. 1. It is the figure which showed the relationship between the dielectric constant of the MIS capacitor of FIG. 1, and a dielectric film composition.
- FIG. 2 is a diagram showing the annealing temperature dependence of the EOT and physical film thickness of the MIS capacitor of FIG. 1.
- FIG. 3 is a cross-sectional view of a MIS capacitor of Example 1.
- 6 is a diagram illustrating a process of a manufacturing method of a semiconductor device of Example 2.
- FIG. It is a figure which shows the process of the manufacturing method of the semiconductor device of Example 3.
- 6 is a cross-sectional view of a semiconductor device according to Example 4.
- FIG. It is a schematic diagram which shows the control mechanism for implementing Example 1 to Example 4.
- MIS Metal Insulator Semiconductor in which a dielectric film formed according to the present invention is formed on a silicon substrate having a silicon oxide film on the surface thereof, as a dielectric film, an HfAlON film in which the A element is Hf and the B element is Al.
- a capacitor As an example.
- an HfAlON film 3 having an amorphous structure was deposited on a silicon substrate 1 having a silicon oxide film 2 having a thickness of 3 nm to 5 nm on the surface.
- FIG. 2 shows an outline of an example of a processing apparatus used in the process of forming the HfAlON film having an amorphous structure.
- the film forming chamber 100 can be heated to a predetermined temperature by the heater 101.
- the substrate 102 to be processed can be heated to a predetermined temperature by a heater 105 via a susceptor 104 incorporated in a substrate support base 103. It is preferable that the substrate support 103 can be rotated at a predetermined rotational speed from the viewpoint of film thickness uniformity.
- targets 106 and 126 are installed at positions where the target substrate 102 is desired.
- the targets 106 and 126 are installed on the target holders 108 and 128 via back plates 107 and 127 made of a metal such as Cu. It should be noted that the outer shape of the target assembly in which the targets 106 and 126 and the back plates 107 and 127 are combined may be made of a target material as a single part and attached as a target. That is, the target may be installed on the target holder.
- Direct current power sources 110 and 130 for applying sputtering discharge power are connected to the target holders 108 and 128 made of metal such as Cu, and insulated from the wall of the film formation processing chamber 100 at the ground potential by the insulators 109 and 129. Has been.
- Magnets 111 and 131 for realizing magnetron sputtering are disposed behind the targets 106 and 126 as viewed from the sputtering surface. Magnets 111 and 131 are held by magnet holders 112 and 132, and can be rotated by a magnet holder rotating mechanism (not shown). In order to make the erosion of the target uniform, the magnets 111 and 131 rotate during discharge.
- the targets 106 and 126 are installed at offset positions obliquely above the substrate 102. That is, the center point of the sputtering surface of the targets 106 and 126 is at a position displaced by a predetermined dimension with respect to the normal line of the center point of the substrate 102.
- a shielding plate 116 is installed between the targets 106 and 126 and the processing substrate 102 to control film formation on the processing substrate 102 by sputtered particles emitted from the targets 106 and 126 to which power is supplied.
- the Hf metal target 106 and the Al metal target 126 are used as targets.
- Deposition of the dielectric film 3 is performed by supplying electric power to the metal targets 106 and 126 from the DC power sources 110 and 130 via the target holders 108 and 128 and the back plates 107 and 127, respectively.
- an inert gas is introduced into the processing chamber 100 from the vicinity of the target from the inert gas source 201 through the valves 202 and 222, the mass flow controllers 203 and 223, and the valves 204 and 224.
- a reactive gas composed of oxygen is introduced from the oxygen gas source 205 to the vicinity of the substrate in the processing chamber 100 through the valve 206, the mass flow controller 207, and the valve 208.
- a reactive gas composed of nitrogen is introduced from the nitrogen gas source 209 to the vicinity of the substrate in the processing chamber 100 through the valve 210, the mass flow controller 211, and the valve 212.
- the introduced inert gas and reactive gas are exhausted by the exhaust pump 118 via the conductance valve 117.
- the molar ratio Al / (Hf + Al + N) of the HfAlON film was adjusted by the power supplied to the Al target.
- FIG. 3 shows the Al target power dependence of the molar ratio Al / (Hf + Al + N) of the HfAlON film.
- the composition was evaluated by analysis by XPS (X-ray Photoelectron Spectroscopy).
- XPS X-ray Photoelectron Spectroscopy
- the molar ratio Al / (Hf + Al + N) can be controlled in the range of 0 to 0.20 by adjusting the target power of Al.
- the molar ratio O / A was adjusted by the oxygen supply amount.
- the molar ratio N / (Hf + Al + N) was adjusted by the nitrogen supply amount.
- an HfAlON film, an HfON film not containing Al, an HfAlO film not containing N, and an HfO 2 film not containing N and Al were formed in a thickness range of 5 nm to 25 nm.
- the deposited HfAlON film, HfON film, HfAlO film, and HfO 2 film were crystallized by performing annealing treatment in a nitrogen atmosphere in the range of 600 ° C. to 1000 ° C. to obtain a dielectric film 3.
- a TiN film 4 having a thickness of 10 nm was deposited on the dielectric film 3 by sputtering.
- it may be crystallized by annealing.
- the TiN film 4 was processed into a desired size using a lithography technique and an RIE (Reactive Ion Etching) technique to form a MIS capacitor structure.
- the electrical characteristics were evaluated using the silicon substrate 1 as the lower electrode and the TiN film 4 as the upper electrode.
- FIG. 4 shows an oxide film for a sample in which the molar ratio Al / (Hf + Al + N) of the HfAlON film is changed, a sample in which the molar ratio Al / (Hf + Al) of the HfAlO film is changed, and a sample in which the HfON film is formed.
- the relationship between a conversion film thickness (EOT: Equivalent Oxide Thickness) and a physical film thickness is shown.
- EOT Equivalent Oxide Thickness
- the equivalent oxide thickness (EOT) will be described.
- the formula (1) is an insulating film, when a material having a large dielectric constant epsilon h as compared to the dielectric constant epsilon o of silicon oxide film, the equivalent oxide thickness d e, the insulating It shows that the silicon oxide film is thinner than the film thickness d h .
- the relative dielectric constant ⁇ o of the silicon oxide film is about 3.9.
- films made of a high dielectric constant material epsilon h 39, even the physical thickness d h as 15 nm, equivalent oxide thickness (electric film thickness) d e becomes 1.5 nm, the insulating film The leakage current can be remarkably reduced while maintaining the same capacitance value as that of a silicon oxide film having a thickness of 1.5 nm.
- FIG. 5 shows the value of the relative dielectric constant derived from the EOT obtained from FIG. 4 and the slope of the physical film thickness.
- X in the figure represents the molar ratio Al / (Hf + Al + N) and the molar ratio Al / (Hf + Al).
- FIG. 5 shows that the relative dielectric constant of the HfAlON film is 48, which is significantly larger than the relative dielectric constant values of 15 to 35 of the HfAlO film and the HfON film.
- FIG. 6 shows the annealing temperature dependence of the EOT and physical film thickness of the HfAlO film whose molar ratio Al / (Hf + Al) is 0.03. From FIG. 6, it can be confirmed that the HfAlO film subjected to the annealing process at 1000 ° C. has an increase in EOT due to the decrease in the relative dielectric constant value as compared with the HfAlO film subjected to the annealing process at 850 ° C. This result shows that the HfAlO film not containing N has no heat resistance against annealing at 1000 ° C., and it becomes clear that the heat resistance against high temperature annealing at 1000 ° C. can be obtained by containing N. It was.
- FIG. 7 shows the relationship between the relative dielectric constant of the HfAlON film crystallized by annealing at 1000 ° C. and the molar ratio Al / (Hf + Al + N). From FIG. 7, it can be confirmed that a relative dielectric constant of 40 or more is obtained when the molar ratio Al / (Hf + Al + N) is in the range of 0.015 to 0.095. Therefore, the molar ratio Al / (Hf + Al + N) of the HfAlON film needs to have a range of 0.015 to 0.095, and a range of 0.02 to 0.07 where a remarkable EOT thin film effect can be obtained. It is preferable to have.
- FIG. 9 shows the annealing temperature dependence of the X-ray diffraction spectrum of the HfAlON film having a molar ratio Al / (Hf + Al + N) of 0.03 and a molar ratio N / (Hf + Al + N) of 0.08. From FIG. 9, it can be confirmed that the HfAlO film has an amorphous structure in the range of the annealing temperature of 600 ° C. from the as-deposited state and is crystallized by the annealing temperature of 700 ° C. or more.
- the dielectric film of the present invention has a crystal phase mainly composed of cubic crystals, and if the cubic crystals are contained in 80% or more, the effect can be sufficiently exerted.
- FIG. 10 shows each X-ray diffraction spectrum.
- FIG. 10 shows that both the HfAlON film and the HfAlO film have a crystal structure mainly composed of cubic crystals.
- FIG. 11 shows the result of comparing the ratio of the peak intensity of [220] and the peak intensity of [111] in the X-ray diffraction spectra of the HfAlON film and the HfAlO film of FIG.
- FIG. 11 shows that the [220] / [111] peak intensity ratio of the HfAlON film is larger than the peak intensity ratio of the HfAlO film. Accordingly, it is considered that the increase in dielectric constant and the improvement in heat resistance in the HfAlON film containing Al and N are related to the orientation in the crystal phase.
- FIG. 14 shows the relationship between the molar ratio O / Hf of the deposited HfO 2 film and the oxygen flow rate during deposition.
- the molar ratio of oxygen was measured by XPS. From FIG. 14, it was confirmed that oxygen has a molar ratio of 2.0 which is a stoichiometric ratio in a region where the oxygen flow rate is 20 sccm or more.
- FIG. 15 shows a cross-sectional TEM image of a metal oxide film made of HfO 2 formed at an oxygen flow rate of 18 sccm (point A) and an oxygen flow rate of 60 sccm (point B) in FIG.
- FIG. 15 shows that HfO 2 obtained under the condition A is amorphous and has excellent surface flatness.
- HfO 2 obtained under the condition of B is crystallized and the flatness is greatly deteriorated.
- FIG. 16 shows an X-ray diffraction spectrum of HfO 2 formed under the conditions of A and B.
- the X-ray diffraction spectrum when HfO 2 formed under condition A is annealed at 600 ° C. is shown in the figure.
- M represents a peak unique to monoclinic crystals (monoclinic).
- FIG. 16 shows that HfO 2 obtained under the condition A is amorphous in the as-deposited state, and crystallizes into a crystal phase mainly composed of cubic crystals by annealing at 600 ° C. On the other hand, it can be confirmed that the crystal phase of HfO 2 obtained under the condition B is monoclinic.
- the molar ratio O / Hf in the film is set in the range of 1.0 ⁇ O / Hf ⁇ 2.0, It is shown that it is important to form it in an amorphous state and then crystallize it into cubic crystals by annealing.
- the relationship between the deposition conditions of the HfO 2 film not containing Al and N, the molar ratio O / Hf, and the deposition rate was described.
- the amorphous state can be obtained by setting the oxygen flow rate so that the molar ratio O / Hf is in the range of 1.0 ⁇ O / Hf ⁇ 2.0 even under the deposition conditions of the HfAlON film containing Al and N. It was confirmed that a high dielectric constant film can be obtained by forming a HfAlON film and then crystallizing it into a crystal structure mainly composed of cubic crystals by annealing.
- FIG. 17 shows the oxygen flow rate dependency of the deposition rate of the HfAlON film. From FIG. 17, it can be confirmed that the deposition rate is 2 nm / min or less in the region where the oxygen flow rate is 20 sccm or more, whereas the deposition rate is significantly increased to 10 nm / min or more in the region lower than 20 sccm. This is because when the oxygen supply amount is 20 sccm, the surface of the metal target is oxidized and the sputtering rate is lowered.
- the formation of the dielectric film in the present invention does not cause a decrease in the deposition rate. It shows that it can be realized.
- the metal oxynitride containing the A element, the B element consisting of Al, and N and O the molar ratio B / (A + B + N) of the A element, the B element and N is 0.015 ⁇ (B / (A + B + N) ) ⁇ 0.095 and N / (A + B + N) is 0.045 ⁇ (N / (A + B + N)) and O / A is between 1.0 ⁇ (O / A) ⁇ 2.0
- a crystalline phase mainly composed of cubic crystals by forming the amorphous oxynitride within the range shown and having an amorphous structure, and further subjecting the metal oxynitride having the amorphous structure to an annealing treatment at 700 ° C. or higher. It is necessary to form a dielectric film containing
- the step of forming the metal oxynitride having an amorphous structure is performed in a vacuum vessel in a mixed atmosphere of a reactive gas and an inert gas composed of a mixed gas of oxygen and nitrogen.
- a step of magnetron sputtering a metal target constituting the layer, and the supply amount of the reactive gas is such that the molar ratio O / A of the metal oxynitride is 1.0 ⁇ (O / A) ⁇ 2.0. It is preferable to set so that.
- the supply amount of the reactive gas in order to suppress a decrease in the deposition rate, it is preferable to set the supply amount of the reactive gas to be equal to or less than the supply amount at which the reduction rate of the sputtering rate caused by the oxidation of the surface of the metal target is maximized. Furthermore, in order to make the film thickness uniformity of the formed dielectric film ⁇ 1% or less, it is preferable to set the pressure in the vacuum vessel during film formation to 1 ⁇ 10 ⁇ 1 Pa or less.
- the present invention is not limited to these.
- the blocking film in the MONOS nonvolatile memory, the floating electrode in the FG nonvolatile memory element, and the like By applying the method of the present invention to the insulating film between the gate electrodes and part of the MOS transistor, the effect can be sufficiently obtained.
- the method of the present invention can be applied to a method of manufacturing a semiconductor device having a dielectric film as an insulator film, and examples thereof include, but are not limited to, the following manufacturing methods.
- a manufacturing method of a semiconductor device includes a substrate having at least a surface including a semiconductor layer, a gate electrode formed on the substrate, and a stacked layer sequentially stacked between the substrate and the gate electrode.
- a method for manufacturing a semiconductor device includes a substrate having at least a surface including a semiconductor layer, a gate electrode formed on the substrate, and an insulating film between the substrate and the gate electrode.
- a nonvolatile semiconductor device having a structure in which a floating electrode and an insulating film are sequentially stacked, and at least a part of the insulating film formed between the gate electrode and the floating electrode is formed by the method of the present invention. To do.
- a method of manufacturing a semiconductor device includes a source region, a drain region, and a gate electrode formed on an insulating film on a substrate having at least a surface including a semiconductor layer.
- a method of manufacturing a semiconductor device having the insulating film is formed by the method of the present invention.
- metal oxynitride containing A element composed of Hf (hafnium) or a mixture of Hf and Zr (zirconium), B element composed of Al, N and O The dielectric film containing the material is formed so that the molar ratio of the A element, the B element and N, and the molar ratio of the A element and O are within the specific ranges described above, respectively, and an amorphous structure is formed. It is important to anneal the metal oxynitride having a crystalline structure at 700 ° C. or higher. Therefore, in any device having a high dielectric film such as a MIS capacitor or a semiconductor device, the method of the present invention can be applied when forming the high dielectric film.
- FIG. 18 shows a MIS capacitor having a dielectric film formed by the method of the present invention.
- a HfAlON film 303 having an amorphous structure is deposited on a silicon substrate 301 having a silicon oxide film 302 with a film thickness of 3 nm to 5 nm on the surface by a sputtering method.
- the targets 106 and 126 metal targets of Hf and Al were used, and argon, oxygen and nitrogen were used as sputtering gases.
- the substrate temperature is 27 ° C. to 600 ° C.
- the target power is 50 W to 1000 W
- the sputtering gas pressure is 0.02 Pa to 0.1 Pa
- the Ar gas flow rate is 1 sccm to 200 sccm
- the oxygen gas flow rate is 1 sccm to 100 sccm
- the nitrogen gas flow rate is 1 sccm to It can be appropriately determined within the range of 50 sccm.
- the substrate processing apparatus controls the heater 105 to set the substrate temperature to 30 ° C., controls the DC power supply 110 to set the target power of Hf to 600 W, and controls the DC power supply 130. Then, the target power of Al is set to 50 W to 500 W, the exhaust pump 118 or the like is controlled to set the sputtering gas pressure to 0.03 Pa, the mass flow controller 230 is controlled to set the Ar gas flow rate to 25 sccm, and the mass flow The controller 207211 was controlled to form a film with the nitrogen gas flow rate set to 0 to 20 sccm.
- the substrate processing apparatus controls the mass flow controller 207 so that the molar ratio O / A shown in FIG. 14 is 1.0 ⁇ (O / A)
- the oxygen supply amount was set to be in the range of ⁇ 2.0.
- the substrate processing apparatus includes a second film forming chamber that is separate from the film forming chamber 100, and a Ti target and a sputtering gas are supplied into the second film forming chamber.
- a supply mechanism for supplying the second film formation chamber is provided.
- the substrate processing apparatus according to this embodiment includes a physical vapor deposition mechanism for performing physical vapor deposition using a Ti target, such as sputtering.
- the substrate temperature is 27 ° C. to 600 ° C.
- the target power is 50 W to 1000 W
- the sputtering gas pressure is 0.02 Pa to 0.1 Pa
- the Ar gas flow rate is 1 sccm to 200 sccm
- the nitrogen gas is appropriately determined within the range of 1 sccm to 50 sccm. be able to.
- the physical vapor deposition mechanism was controlled to form a film at a substrate temperature of 30 ° C., a Ti target power of 750 W, a sputtering gas pressure of 0.03 Pa, an Ar gas flow rate of 30 sccm, and a nitrogen gas flow rate of 10 sccm.
- TiN film 304 is deposited here, but Ti, TaN, W, Pt, Ru, Al, and Si can also be used as appropriate. Further, a film selected from the group consisting of these may be deposited.
- the substrate processing apparatus performs annealing for 10 sec at a temperature of 700 ° C. for 2 min or 1000 ° C. in a nitrogen atmosphere to crystallize the HfAlON film to obtain a dielectric film 303.
- the annealing process is performed after the TiN film 304 is deposited here, the annealing process may be performed before the TiN film 304 is deposited.
- the annealing treatment is performed in a nitrogen atmosphere, but an inert gas such as oxygen or Ar can be used as appropriate.
- the substrate processing apparatus according to the present embodiment can further include a chamber for the annealing process.
- the TiN film 304 was processed into a desired size using a lithography technique and an RIE technique to form a MIS capacitor structure.
- the relative dielectric constant of the dielectric film 303 produced as described above was evaluated.
- the Al molar ratio Al / (Hf + Al + N) of the HfAlON film is in the range of 0.015 to 0.095
- the N molar ratio N / (Hf + Al + N) is 0.045 or higher
- the relative dielectric constant is 40 or higher. It was confirmed that Further, as a result of measuring X-ray diffraction of the dielectric film 303 subjected to annealing treatment at 700 ° C. or higher, it was confirmed that the dielectric film 303 had a crystal structure mainly composed of cubic crystals. Furthermore, as a result of evaluating the surface flatness by AFM, it was confirmed that the surface flatness was superior as compared with HfO 2 film and HfON film not containing Al or N.
- HfAlON Al molar ratio 0.015 ⁇ (Al / (Hf + Al + N)) ⁇ 0.095
- N molar ratio 0.045 ⁇ (N / (Hf + Al + N) Forming a metal oxynitride having an amorphous structure, and subjecting the metal oxynitride having an amorphous structure to an annealing treatment at 700 ° C. or more to include a metal oxynitride containing a crystal phase mainly composed of cubic crystals
- FIG. 19 is a diagram showing the steps of a semiconductor device manufacturing method according to the second embodiment of the present invention.
- an element isolation region 402 was formed on the surface of a silicon substrate 401 by using STI (Shallow Trench Isolation) technique as shown in Step 1 of FIG.
- a silicon oxide film 403 having a film thickness of 1.8 nm is formed on the surface of the silicon substrate 401 from which the elements have been separated by thermal oxidation.
- the substrate processing apparatus forms the HfAlON film in the thickness range of 1 nm to 10 nm by the same method as in the first embodiment. Subsequently, the substrate processing apparatus according to this example annealed at 1000 ° C. for 10 seconds in a nitrogen atmosphere to crystallize the HfAlON film to obtain a dielectric film 404.
- the gate electrode is formed by using the lithography technique and the RIE technique as shown in Step 2 of FIG. Then, ion implantation was performed, and the extension region 406 was formed in a self-aligned manner using the gate electrode as a mask.
- a silicon nitride film and a silicon oxide film were sequentially deposited, and then etched back to form a gate sidewall 407.
- the substrate processing apparatus according to this example performed ion implantation again, and formed source / drain regions 408 through activation annealing.
- crystallization of the HfAlON film may be performed in an activation annealing step. In that case, the crystallization annealing step after depositing the HfAlON film can be omitted.
- the Al molar ratio of the HfAlON film as the dielectric film 404 is 0.015 ⁇ (Al / (Hf + Al + N) ⁇ 0.095, and the N molar ratio is 0.045 ⁇ (N In the range of / (Hf + Al + N), it was confirmed that the relative dielectric constant increased and the leakage current could be reduced as compared with HfO 2 not containing Al and N.
- X-ray diffraction of the dielectric film 404 subjected to annealing treatment As a result, it was confirmed that the crystal structure was mainly composed of cubic crystals.
- the gate leakage current is obtained by performing the method for manufacturing a dielectric film of the present invention. It is possible to obtain a semiconductor device that can reduce the above. Further, in this example, it was confirmed that the same effect can be obtained even in a HfZrAlON film containing Zr as a dielectric film.
- FIG. 20 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the third embodiment of the present invention.
- an element isolation region 502 was formed on the surface of a silicon substrate 501 using an STI (Shallow Trench Isolation) technique as shown in Step 1 of FIG.
- a silicon oxide film as a first insulating film 503 is formed on the surface of the element-isolated silicon substrate 501 by 30 to 100 by a thermal oxide film method.
- a silicon nitride film is formed as a second insulating film 504 by 30 to 100 by LPCVD (Low Pressure Chemical Vapor Deposition).
- the substrate processing apparatus according to this embodiment forms an aluminum oxide film of 5 to 50 mm as the third insulating film 505.
- the aluminum oxide film may be formed by MOCVD, ALD (Atomic Layer Deposition), or PVD (Physical Vapor Deposition).
- the substrate processing apparatus according to the present embodiment forms an HfAlON film with a thickness of 5 nm to 20 nm as the fourth insulating film 506 by the same method as in the first embodiment.
- the substrate processing apparatus according to the present embodiment forms 5 to 50 mm of aluminum oxide film as the fifth insulating film 507.
- an MOCVD method, an ALD method, and a PVD method are used.
- lithography technology and RIE reactive Ion Etching
- a gate side wall 510 was formed by sequentially depositing a silicon nitride film and a silicon oxide film and then performing etch back.
- the substrate processing apparatus according to this example performed ion implantation again, and formed source / drain regions 511 through activation annealing.
- the Al molar ratio of the HfAlON film as the fourth insulating film 506 is 0.015 ⁇ (Al / (Hf + Al + N) ⁇ 0.095, and the N molar ratio is 0.045 ⁇ .
- the relative dielectric constant increased and the leakage current could be reduced as compared with HfO 2 not containing Al and N.
- the fourth insulating film 506 subjected to the annealing treatment was confirmed.
- As a result of measuring the X-ray diffraction it was confirmed that it had a crystal structure mainly composed of cubic crystals.
- the dielectric film manufacturing method of the present invention is carried out in the manufacturing method of the semiconductor device having the HfAlON film on a part of the blocking insulating film of the MONOS type nonvolatile memory element.
- a semiconductor device that can reduce the gate leakage current can be obtained.
- the poly-Si film is used as the gate electrode.
- the same effect can be obtained by using TiN, TaN, W, WN, Pt, Ir, Pt, Ta, Ti as the gate electrode. did it.
- the annealing treatment of the first insulating film 503, the second insulating film 504, the third insulating film 505, the fourth insulating film 506, and the fifth insulating film 507 is performed after ion implantation. Although it is performed by activation annealing, annealing may be performed after each insulating film is formed.
- a stacked film of the third insulating film 505, the fourth insulating film 506, and the fifth insulating film 507 is used as the blocking layer of the nonvolatile semiconductor memory element.
- a similar effect can be obtained with a laminated film of the insulating film 505 and the fourth insulating film 506.
- FIG. 21 is a sectional view of a semiconductor device according to the fourth embodiment of the present invention.
- This example is different from Example 3 in that the second insulating film 504 of the semiconductor element in Example 3 is formed of a layer made of poly-Si 601. The formation process after the second insulating film 504 is the same as that of the third embodiment.
- the Al molar ratio of the HfAlON film as the fourth insulating film is 0.015 ⁇ (Al / (Hf + Al + N) ⁇ 0.095, and the N molar ratio is 0.045 ⁇ ( In the range of N / (Hf + Al + N), it was confirmed that the relative dielectric constant increased and the leakage current could be reduced as compared with HfO 2 not containing Al and N. Further, X of the fourth insulating film subjected to the annealing treatment was confirmed. As a result of measuring line diffraction, it was confirmed that it had a crystal structure mainly composed of cubic crystals.
- the present invention provides a method for manufacturing a semiconductor device having an HfAlON film on a part of a blocking insulating film (interpoly insulating film) of an FG type nonvolatile memory element having a floating electrode.
- a semiconductor device capable of reducing the gate leakage current can be obtained. Further, in this example, it was confirmed that the same effect can be obtained even in a HfZrAlON film containing Zr as a dielectric film.
- the poly-Si film is used as the gate electrode.
- the same effect can be obtained by using TiN, TaN, W, WN, Pt, Ir, Pt, Ta, Ti as the gate electrode. did it.
- the first insulating film, the second poly-Si layer, the third insulating film, the fourth insulating film, and the fifth insulating film are annealed after the ion implantation.
- annealing may be performed after each insulating film is formed.
- a laminated film of the third insulating film, the fourth insulating film, and the fifth insulating film is used as the blocking layer of the nonvolatile semiconductor memory element.
- the same effect could be obtained with a laminated film with the fourth insulating film.
- FIG. 22 is a schematic diagram illustrating a control mechanism for carrying out the first to fourth embodiments.
- the control mechanism 300 is connected to a substrate processing apparatus 301 that can implement the first to fourth embodiments.
- the control mechanism 300 includes an input unit 300b, a storage unit 300c having a program and data, a processor 300d, and an output unit 300e.
- the control mechanism 300 basically has a computer configuration and controls the substrate processing apparatus 301.
- the substrate processing apparatus 301 can be the substrate processing apparatus according to the first to fourth embodiments described above. Therefore, the control mechanism 300 can control the operation of the substrate processing apparatus 301 by causing the processor 300d to execute the control program stored in the storage unit 300c. That is, under the control of the control mechanism 301, the substrate processing apparatus 301 can perform the operations described in the first to sixth embodiments.
- the control mechanism 300 may be provided separately from the substrate processing apparatus 301 or may be built in the substrate processing apparatus 301.
- the processing method for storing the program for operating the configuration of the above-described embodiment so as to realize the function of the above-described embodiment in a storage medium, reading the program stored in the storage medium as a code, and executing the program on the computer is also described above. It is included in the category of the embodiment. That is, a computer-readable storage medium is also included in the scope of the embodiments. In addition to the storage medium storing the computer program, the computer program itself is included in the above-described embodiment. As such a storage medium, for example, a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, CD-ROM, magnetic tape, nonvolatile memory card, and ROM can be used.
- processing is not limited to the single program stored in the above-described storage medium, but operates on the OS in cooperation with other software and expansion board functions to execute the operations of the above-described embodiments. This is also included in the category of the embodiment described above.
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Abstract
Description
特許文献1に記載のZrO2にAlを5~30%の範囲で含有させる技術では、非晶質構造で比誘電率が25~28と高い値が得られるが、結晶構造を有するZrO2の比誘電率値30よりも低下してしまうという課題が生じる。
を有する半導体装置の製造方法であって、前記絶縁膜を、上記第1の態様に記載の方法により形成することを特徴とする。
de=dh×(εo/εh)・・・(1)
<実施例1(コスパッタによる実施例)>
本発明の第1の実施例を、図面を参照しながら詳細に説明する。
図18は、本発明の方法により形成された誘電体膜を有するMISキャパシタを示した図である。図2に示すような本実施例に係る基板処理装置は、表面に膜厚3nm~5nmのシリコン酸化膜302を有するシリコン基板301に、スパッタリング法により非晶質構造を有するHfAlON膜303を堆積した。ターゲット106、126としては、HfおよびAlの金属ターゲットを用い、スパッタガスとしてアルゴンおよび酸素および窒素を用いた。
ここでは、物理蒸着機構を制御し、基板温度30℃、Tiのターゲットパワー750W、スパッタガス圧0.03Pa、Arガス流量30sccm、窒素ガス流量10sccmとして成膜を行った。
本発明の第2の実施例を、図面を参照しながら詳細に説明する。
図19は、本発明の第2の実施例である半導体装置の製造方法の工程を示した図である。
まず、本実施例に係る基板処理装置は、図19の工程1に示すようにシリコン基板401の表面にSTI(Shallow Trench Isolation)技術を用いて素子分離領域402を形成した。続いて、本実施例に係る基板処理装置は、素子分離されたシリコン基板401表面に熱酸化法により膜厚1.8nmのシリコン酸化膜403を形成する。その後、本実施例に係る基板処理装置は、実施例1と同じ方法によりHfAlON膜を膜厚1nm~10nmの範囲で形成する。続いて、本実施例に係る基板処理装置は、窒素雰囲気中で1000℃、10secのアニール処理を行い、HfAlON膜を結晶化させ、誘電体膜404とした。
図20は本発明の第3の実施例に関わる半導体素子の作製工程を示した断面図である。
まず本実施例に係る基板処理装置は、図20の工程1に示すようにシリコン基板501の表面にSTI(Shallow Trench Isolation)技術を用いて素子分離領域502を形成した。続いて、本実施例に係る基板処理装置は、素子分離されたシリコン基板501表面に、第1の絶縁膜503としてシリコン酸化膜を熱酸化膜法により30Å~100Å形成する。続いて、本実施例に係る基板処理装置は、第2の絶縁膜504としてシリコン窒化膜をLPCVD(Low Pressure Chemical Vapor Deposition)法により30Å~100Å形成する。続いて、本実施例に係る基板処理装置は、第3の絶縁膜505として、酸化アルミニウム膜を5Å~50Å形成する。酸化アルミニウム膜は、MOCVD法、ALD(Atomic Layer Deposition)法、PVD(Physical Vapor Deposition)法を用いてもよい。続いて、本実施例に係る基板処理装置は、第4の絶縁膜506として、実施例1と同じ方法によりHfAlON膜を膜厚5nm~20nmの範囲で形成する。続いて、本実施例に係る基板処理装置は、第5の絶縁膜507として、酸化アルミニウム膜を5Å~50Å形成する。形成方法は、MOCVD法、ALD法、PVD法を用いて形成する。
本発明の第4の実施例を、図面を参照しながら詳細に説明する。
図21は、本発明の第4の実施例である半導体装置の断面図を示した図である。本実施例は、実施例3における半導体素子の第2の絶縁膜504をpoly-Si601からなる層で形成する点で、実施例3と異なる。第2の絶縁膜504以降の形成工程は、実施例3と同一である。
図22において、基板処理装置301は、上述した実施例1~4に係る基板処理装置とすることができる。従って、制御機構300は、プロセッサ300dが、記憶部300cに格納された制御プログラムを実行することで、基板処理装置301の動作を制御することができる。すなわち、制御機構301の制御により、基板処理装置301は、上述した実施例1~6に記載した動作を行うことができる。
なお、制御機構300は、基板処理装置301と別個に設けても良いし、基板処理装置301に内蔵しても良い。
かかる記憶媒体としてはたとえばフロッピー(登録商標)ディスク、ハードディスク、光ディスク、光磁気ディスク、CD-ROM、磁気テープ、不揮発性メモリカード、ROMを用いることができる。
Claims (13)
- 基板上に、HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む誘電体膜の形成方法であって、
A元素とB元素とNのモル比率B/(A+B+N)が0.015≦(B/(A+B+N))≦0.095であり、かつN/(A+B+N)が0.045≦(N/(A+B+N))であり、かつA元素とOのモル比率O/Aが1.0<(O/A)<2.0の間で表され、非晶質構造を有する金属酸窒化物を形成する工程と、
該非晶質構造を有する金属窒化物に700℃以上のアニール処理を施し、立方晶の混入割合が80%以上の結晶相を含む金属酸窒化物を形成する工程と、
を備えたことを特徴とする誘電体膜の製造方法。 - 前記非晶質構造を有する金属酸窒化物を形成する工程が、
真空容器内で、酸素と窒素の混合ガスからなる反応性ガスと不活性ガスとの混合雰囲気下において前記金属酸窒化物層を構成する金属ターゲットをマグネトロンスパッタする工程であり、
前記反応性ガスの供給量を、前記金属酸窒化物のA元素とOのモル比率O/Aが1.0<(O/A)<2.0の範囲となるように設定することを特徴とする請求項1に記載の誘電体膜の製造方法。 - 前記反応性ガスの供給量を、前記金属ターゲットの表面が酸化することにより生じるスパッタ率の低下率が最大となる供給量以下に設定することを特徴とする請求項2に記載の誘電体膜の製造方法。
- 前記真空容器内の圧力を1×10-1Pa以下に設定することを特徴とする請求項2に記載の誘電体膜の製造方法。
- 前記誘電体膜の比誘電率が40以上であることを特徴とする請求項1に記載の誘電体膜の製造方法。
- 絶縁体膜として誘電体膜を有する半導体装置の製造方法であって、
前記誘電体膜を、請求項1に記載の方法により形成することを特徴とする半導体装置の製造方法。 - 少なくとも表面が半導体層を含む基板と、
前記基板上に形成されたゲート電極と、
前記基板と前記ゲート電極の間に順次積層された積層型ゲート絶縁膜を有する不揮発性半導体装置の製造方法であって、
前記積層型ゲート絶縁膜を構成する絶縁膜の少なくとも一層を、請求項1に記載の方法により形成することを特徴とする半導体装置の製造方法。 - 少なくとも表面が半導体層を含む基板と、
前記基板上に形成されたゲート電極と、
前記基板と前記ゲート電極の間に絶縁膜と浮遊電極と絶縁膜とが順次積層された構造を有する不揮発性半導体装置の製造方法であって、
前記ゲート電極と前記浮遊電極との間に形成される絶縁膜の少なくとも一部を、請求項1に記載の方法により形成することを特徴とする半導体装置の製造方法。 - 少なくとも表面が半導体層を含む基板上に、
ソース領域と、
ドレイン領域と、
絶縁膜を介して形成されてゲート電極と、
を有する半導体装置の製造方法であって、
前記絶縁膜を、請求項1に記載の方法により形成することを特徴とする半導体装置の製造方法。 - HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む誘電体膜であって、
A元素とB元素とNのモル比率B/(A+B+N)が0.015≦(B/(A+B+N))≦0.095であり、かつN/(A+B+N)が0.045≦(N/(A+B+N))であり、かつA元素とOのモル比率O/Aが1.0<(O/A)<2.0であることを特徴とする誘電体膜。 - コンピュータに、高誘電体膜を含むMISキャパシタの、該高誘電体膜の形成方法を実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体であって、
前記形成方法は、
HfもしくはHfとZrを含有する金属ターゲット及びAlの金属ターゲットを用いた物理蒸着により、シリコン酸化膜を有するシリコン基板上に、HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む誘電体膜を堆積する工程であって、A元素とOのモル比率O/Aが1.0<(O/A)<2.0の範囲になるように酸素供給量を設定し、前記誘電体膜を堆積する第1の工程と、
前記誘電体膜上に、金属ターゲットを用いた物理蒸着により、TiN膜、Ti、TaN、W、Pt、Ru、Al、Si、のうちから選択される膜を堆積する第2の工程と、
前記第1の工程又は前記2の工程の後、アニール処理を行い前記誘電体膜を結晶化させる第3の工程と
を有することを特徴とするコンピュータ読み取り可能な記録媒体。 - コンピュータに、高誘電体膜を含むMOSFETの形成方法を実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体であって、
前記形成方法は、
STIにより、シリコン基板上に、素子分離領域を形成する第1の工程と、
前記素子分離されたシリコン基板上に熱酸化法により、シリコン酸化膜を形成する第2の工程と、
前記シリコン酸化膜上に、Hf及びAlの金属ターゲットを用いた物理蒸着により、HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む誘電体膜を堆積する工程であって、A元素とOのモル比率O/Aが1.0<(O/A)<2.0の範囲になるように酸素供給量を設定し、前記誘電体膜を堆積する第3の工程と、
前記誘電体膜上にゲート電極膜を形成する第4の工程と、
リソグラフィーとRIEを用いて、前記ゲート電極膜を加工する第5の工程と、
イオン注入を行い、前記加工されたゲート電極膜をマスクとして、エクステンション領域を形成する第6の工程と、
前記エクステンション領域が形成されたシリコン基板上に、シリコン窒化膜とシリコン酸化膜とを堆積する第7の工程と、
前記堆積されたシリコン窒化膜とシリコン酸化膜とをエッチバックすることにより、ゲート側壁を形成する第8の工程と、
イオン注入を行い、前記エクステンション領域の下にソース・ドレイン領域を形成する第9の工程と
を有することを特徴とするコンピュータ読み取り可能な記録媒体。 - コンピュータに、高誘電体膜を含む不揮発メモリ素子又はFG型不揮発性半導体素子の形成方法を実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体であって、
前記形成方法は、
STIにより、シリコン基板上に、素子分離領域を形成する第1の工程と、
前記素子分離されたシリコン基板上に熱酸化法により、第1の絶縁膜を形成する第2の工程と、
前記第1の絶縁膜上に、LPCVDにより、第2の絶縁膜を形成する第3の工程と、
前記第2の絶縁膜上に、MOCVD、ALD、PVDのいずれかを使用して、第3の絶縁膜を形成する第4の工程と、
前記第3の絶縁膜上に、Hf及びAlの金属ターゲットを用いた物理蒸着により、HfもしくはHfとZrの混合物からなるA元素とAlからなるB元素とNとOとを含有する金属酸窒化物を含む、第4の絶縁膜である高誘電体膜を堆積する工程であって、A元素とOのモル比率O/Aが1.0<(O/A)<2.0の範囲になるように酸素供給量を設定し、前記第4の絶縁膜である高誘電体膜を形成する第5の工程と、
前記第4の絶縁膜上に、MOCVD、ALD、PVDのいずれかを用いて、第5の絶縁膜を形成する第6の工程と、
前記第5の絶縁膜上に、ゲート電極膜を形成する第7の工程と、
リソグラフィー技術及びRIE技術を用いて、前記ゲート電極膜を加工する第8の工程と、
イオン注入を行い、前記加工されたゲート電極膜をマスクとして、エクステンション領域を形成する第9の工程と、
前記エクステンション領域が形成されたシリコン基板上に、シリコン窒化膜とシリコン酸化膜とを堆積する第10の工程と、
前記堆積されたシリコン窒化膜とシリコン酸化膜とをエッチバックすることにより、ゲート側壁を形成する第11の工程と、
イオン注入を行い、前記エクステンション領域の下にソース・ドレイン領域を形成する第12の工程と
を有することを特徴とするコンピュータ読み取り可能な記録媒体。
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