WO2007142010A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- WO2007142010A1 WO2007142010A1 PCT/JP2007/060255 JP2007060255W WO2007142010A1 WO 2007142010 A1 WO2007142010 A1 WO 2007142010A1 JP 2007060255 W JP2007060255 W JP 2007060255W WO 2007142010 A1 WO2007142010 A1 WO 2007142010A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 82
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 81
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 64
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 62
- 239000010703 silicon Substances 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000013078 crystal Substances 0.000 claims abstract description 33
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 19
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 19
- 230000005669 field effect Effects 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 146
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 56
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 50
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 42
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 claims description 38
- 239000012535 impurity Substances 0.000 claims description 34
- 238000010438 heat treatment Methods 0.000 claims description 27
- 229910052759 nickel Inorganic materials 0.000 claims description 22
- 239000000203 mixture Substances 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 14
- 229910052735 hafnium Inorganic materials 0.000 claims description 10
- 230000000873 masking effect Effects 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 239000002253 acid Substances 0.000 claims description 4
- 229910052746 lanthanum Inorganic materials 0.000 claims description 4
- 239000002052 molecular layer Substances 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- 229910052726 zirconium Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- 229910005883 NiSi Inorganic materials 0.000 claims 6
- 229910003217 Ni3Si Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 172
- 229910052751 metal Inorganic materials 0.000 description 19
- 239000002184 metal Substances 0.000 description 19
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- 238000004544 sputter deposition Methods 0.000 description 11
- 239000007789 gas Substances 0.000 description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 229910021334 nickel silicide Inorganic materials 0.000 description 7
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical group [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 7
- 238000000151 deposition Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000011259 mixed solution Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 241001663154 Electron Species 0.000 description 1
- 206010030924 Optic ischaemic neuropathy Diseases 0.000 description 1
- 240000004760 Pimpinella anisum Species 0.000 description 1
- 206010037660 Pyrexia Diseases 0.000 description 1
- 229910006501 ZrSiO Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910002065 alloy metal Inorganic materials 0.000 description 1
- -1 and among these Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000002484 cyclic voltammetry Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a technique related to a MOS field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) having a gate electrode formed of metal silicide. .
- MOSFET Metal Oxide Semiconductor Field Effect Transistor
- Non-Patent Document 1 International 'Electron' Device 'Meeting' International Electron Devices Meeting Technical Digest 2002, p. 359 is a Ta electrode formed on SiO and Ru
- the work function of the electrode is that They are 4.15 eV and 4.95 eV, respectively, and it is stated that a 0.8 eV work function modulation is possible between the two electrodes.
- Non-Patent Document 2 International 'electron' device meeting & tech-calguinest (International electron devices meeting technical digest) 2004, p. 91
- Patent Document 1 International Publication No. 2006Z001271 pamphlet
- gate electrodes made of silicide having different work functions can be separately formed without performing a process of etching and removing a film deposited on a gate insulating film as in the dual metal gate technology. Therefore, damage to the gate insulating film can be prevented.
- the composition of nickel silicide is utilized by utilizing the formation of a crystal phase. It is described that control of a wide range of effective work functions is possible by controlling. In particular, utilizing the formation of NiSi phase, NiSi phase and NiSi phase
- Patent Document 2 (US Patent Application Publication No. 2005Z0070062) includes P-type MOSFE.
- a metal silicide to which a p-type impurity is added is used for the gate electrode of T, N-type MO
- Half of the metal silicide doped with n-type impurities is used for the gate electrode of SFET A conductor arrangement is disclosed.
- Patent Document 3 JP 2005- 129551 discloses
- Ni composition Ni composition (NIZ (Ni + Si)) is 40 to 70 atomic 0/0
- a gate insulating film made of silicon oxide and a gate electrode containing an 11-type impurity with a Ni composition of 30 to 60 atomic% are used in the N-type MOSFET. It is described that the desired work function can be obtained, respectively.
- NiSi nickel monosilicide
- the silicide progresses nonuniformly, and there arises a problem that crystal phases of different compositions are formed depending on the gate size.
- the nickel film formed on the polycrystalline silicon layer constituting the gate pattern also has the diffusion amount of nickel to the polycrystalline silicon layer, in particular, the diffusion amount from the lateral direction (in the plane of the substrate), the gate size.
- the silicide speed is affected by the difference in the impurity species added to the polycrystalline silicon layer, and sufficient silicidation is not performed and the polycrystalline silicon remains. is there.
- Such a phenomenon is caused by the fact that NiSi is not the most stable phase in nickel silicide.
- the composition of the gate electrode varies, the amount of impurities near the interface between the gate electrode and the gate insulating film changes, resulting in the variation of the threshold voltage. If polycrystalline silicon remains without being silicided, the original metal gate effect can not be obtained.
- Non-Patent Document 3 International 'electron's' anis 'meeting' Technical electron devices meeting technical digest 2004, p. 87
- Non-patent document 4 international. Electron. Device ⁇ Meeting ⁇ Technical-cal-digest (International elec tron devices meeting technical digest) 2005, p. 06 ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇
- the first heat treatment is performed to make polycrystalline silicon halfway (polycrystalline silicon part Will remain )
- nickel rich silicide such as Ni Si and remove excess Ni.
- an object of the present invention is to provide a high-performance and highly reliable semiconductor device in which variations in element performance are suppressed, and a method of manufacturing the same.
- a field effect transistor having a silicon substrate, a gate insulating film on the silicon substrate, a gate electrode on the gate insulating film, and source / drain regions formed on the substrate on both sides of the gate electrode.
- a semiconductor device comprising
- the gate electrode includes a NiSi crystal phase at least in a portion including the lower surface of the gate electrode.
- the said transistor is a semiconductor device which has an adhesion layer containing a metal oxide component between the said gate insulating film and the said gate electrode.
- the gate insulating film has a silicon oxide film or a silicon oxynitride film at least in a portion including the upper surface of the gate insulating film,
- the silicide layer containing the above-mentioned NiSi crystal phase contains the impurity element.
- P-channel type having a first gate insulating film on the silicon substrate, a first gate electrode on the first gate insulating film, and a source / drain region formed on the substrate on both sides of the first gate electrode
- a field effect transistor
- An N-channel field effect transistor having a second gate insulating film on the silicon substrate, a second gate electrode on the second gate insulating film, and source / drain regions formed on the substrate on both sides of the second gate electrode;
- the first gate insulating film has a silicon oxide film or a silicon oxynitride film in a portion including at least the upper surface of the gate insulating film,
- the first gate electrode has a silicide layer containing a first conductivity type impurity element and containing a NiSi crystalline phase in a portion including at least the lower surface of the gate electrode,
- the N-channel field effect transistor has an adhesion layer containing a metal oxide component between the first gate insulating film and the first gate electrode.
- the second gate insulating film has a silicon oxide film or a silicon oxynitride film in a portion including at least the upper surface of the gate insulating film,
- the second gate electrode has a silicide layer containing a second conductivity type impurity element and containing a NiSi crystalline phase at least in a portion including the lower surface of the gate electrode,
- a semiconductor device having an adhesion layer containing a metal oxide component between a second gate insulating film and a second gate electrode.
- the oxide component of the adhesion layer is an oxide of a metal selected from Hf, Ta, Zr, La, Ti, Y, and Al, and also a metal oxide selected from any of the items 1 to 3.
- the semiconductor device of description is an oxide of a metal selected from Hf, Ta, Zr, La, Ti, Y, and Al, and also a metal oxide selected from any of the items 1 to 3.
- the semiconductor device according to any one of the items 1 to 5, having a resistive layer.
- the silicide layer containing the above-mentioned NiSi crystal phase is formed of the silicide represented by the composition formula NiSi (0. 6 ⁇ x ⁇ 0. 9).
- the semiconductor device according to claim 1. (9) A method of manufacturing a semiconductor device according to item 1 above,
- the polycrystalline silicon under the nickel film is silicided by heat treatment to form Ni Si
- the manufacturing method of the semiconductor device which has the process of forming the silicide layer containing 3 crystal phases.
- a method of manufacturing a semiconductor device further comprising the step of: diffusing nickel from the silicide layer into the silicon film by heat treatment to form a low resistance silicide layer including a nickel monosilicide crystal phase.
- the polycrystalline silicon under the nickel film is silicided by heat treatment to form Ni Si
- the manufacturing method of the semiconductor device which has the process of forming the silicide layer containing 3 crystal phases.
- the method of manufacturing a semiconductor device further comprising: a step of diffusing nickel from the silicide layer into the silicon film by heat treatment to form a low resistance silicide layer including a nickel monosilicide crystal phase.
- the “effective work function” of the gate electrode is generally obtained from flat band voltage by CV measurement, and in addition to the work function inherent to the gate electrode, the insulating film can be used. It is affected by the fixed charge inside, the dipole formed at the interface, Fermi level pin Jung, etc. It is distinguished from the original "work function" of the material that constitutes the gate electrode.
- the present invention it is possible to provide a high-performance, highly reliable semiconductor device with suppressed variations in element performance, and a method of manufacturing the same.
- the formation of the silicide layer enables the formation of a uniform silicide, which suppresses the device performance. Thus, it is possible to provide the obtained semiconductor device. Further, according to the present invention, since the adhesion layer is provided between the gate electrode and the gate insulating film, sufficient adhesion of the gate electrode to the gate insulating film can be obtained, and a semiconductor device with high reliability is provided. can do.
- the upper layer portion of the gate electrode is a silicon layer containing the NiSi phase in the lower layer portion.
- the wiring resistance and contact resistance of the gate electrode can be reduced.
- FIG. 1 is a schematic cross-sectional view showing a first embodiment of the semiconductor device of the present invention.
- FIG. 2 is a schematic cross-sectional view showing a second embodiment of the semiconductor device of the present invention.
- FIG. 3 A cross-sectional photograph showing the state of the silicide layer (without the adhesion layer) on the silicon oxide film.
- FIG. 4 A cross-sectional photograph showing the state of the silicide layer (with the adhesion layer) on the silicon oxide film.
- FIG. 5 A sectional view of a process for illustrating a method of manufacturing a semiconductor device (first embodiment) according to the present invention.
- FIG. 6 is a cross-sectional view of a process for illustrating a method of manufacturing a semiconductor device (first embodiment) according to the present invention.
- FIG. 7 is a cross-sectional view of a process for illustrating a method of manufacturing a semiconductor device (first embodiment) according to the present invention.
- FIG. 8 is a cross-sectional view of a process for illustrating a method of manufacturing a semiconductor device (first embodiment) according to the present invention.
- FIG. 9 is a cross-sectional view of a process for illustrating a method of manufacturing a semiconductor device (first embodiment) according to the present invention.
- FIG. 10 is a process sectional view for illustrating a method of manufacturing a semiconductor device (second embodiment) according to the present invention.
- FIG. 11 is a cross-sectional process view for explaining a manufacturing method of the semiconductor device (second embodiment) according to the present invention.
- the present invention is suitable for a MOS type field effect transistor (hereinafter referred to as “MOSFET”) having a gate electrode formed of metal silicide, and in particular a P channel type field effect transistor
- MOSFET MOS type field effect transistor
- P-type MOSFET MOS type field effect transistor
- N-type MOSFET TJ N-channel field effect transistor
- CMOS complementary MOS
- FIG. 1 and FIG. 2 show schematic cross-sectional views for describing first and second embodiments of the semiconductor device of the present invention, respectively.
- reference numeral 1 is a silicon substrate
- 2 is an element isolation region
- 3a is a gate insulating film
- 3b is an adhesion layer
- 4 is an extension diffusion region
- 5 is a source / drain diffusion region
- 6 is a silicide layer
- 7 is a gate sidewall
- 8 and 9 are impurity-containing Ni Si electrodes
- the semiconductor devices of the first and second embodiments have a P-type MOSFET and an N-type MOSFET, and a silicon oxide film or a silicon oxynitride film is used as a gate insulating film, and an impurity is contained as a gate electrode.
- a NiSi electrode is used.
- the gate electrode of P-type MOSFET is
- the gate electrode of an N-type MOSFET contains an n-type impurity such as phosphorus (P), and each transistor has a predetermined threshold value depending on the type and concentration of the impurity. It is set.
- One of the features of the present invention is that it has a silicide layer (hereinafter referred to as “Ni Si layer” as needed) in a region (at least the lowermost layer) including at least the lower surface of the gate electrode. , Or
- the entire gate electrode includes a silicide layer containing a NiSi crystal phase (NiSi electrode 8,
- a low resistance layer (low resistance) having a resistance lower than that of the lower silicide layer (Ni Si electrodes 8 and 9) in the upper layer portion of the gate electrode Silicide
- a layer 11 can be provided.
- the threshold voltage By having the Ni Si layer in at least the lowermost portion of the gate electrode, the threshold
- Ni Si crystalline phase is
- nickel silicide it is the crystal phase that can be formed most stably, and for example, by performing silicide heat treatment at a temperature of 350 ° C. or more, a nickel supply amount exceeding the necessary amount, and a heat treatment time longer than the necessary time. It is possible to form a silicide having a constant composition which does not depend on the gate pattern size and the amount of impurities in polycrystalline silicon. Therefore, since the impurity concentration in the vicinity of the interface between the gate electrode and the gate insulating film is stabilized at a predetermined value, You can reduce the fluctuation of the value.
- the threshold in the first and second embodiments is controlled by the type and concentration of impurities added to the gate electrode.
- a Ni Si layer is used for the gate electrode (at least the lowermost part) of both P-type MOSFET and N-type MOSFET, and silicon oxide is used for the gate insulating film.
- a film or silicon oxynitride film is used.
- the gate insulating film has a multilayer structure, it is preferable to have a silicon oxide film or a silicon oxynitride film in the uppermost layer portion.
- the effective work function of the nickel silicide on the silicon oxide film or silicon oxynitride film shows a nearly constant value where the influence of the composition of the silicide crystal phase is small, so it is easy to add impurities to the silicide. It is possible to carry out value control.
- the adhesion layer between the gate electrode and the gate insulating film by providing the adhesion layer between the gate electrode and the gate insulating film, the adhesion between the gate electrode and the gate insulating film can be improved, and a highly reliable semiconductor device can be provided. . Moreover, the yield at the time of manufacture can also be improved.
- Figs. 3 and 4 show cross-sectional photographs of the nickel silicide layer formed on the silicon oxide film.
- Fig. 3 shows an example without an adhesion layer between the silicon oxide film and the silicide layer
- Fig. 4 shows an example with an adhesion layer between the silicon oxide film and the silicide layer.
- a silicon oxide film (3 nm in thickness) is formed on a silicon substrate by thermal oxidation, and a Ni Si layer (120 nm in thickness) is formed on this oxide film as follows. Formed. Silicon oxide film type
- a polycrystalline silicon film 60 nm thick was deposited by chemical vapor deposition (CVD) and subjected to an annealing treatment under the same conditions as the active barrier of the source / drain diffusion layer used in the usual CMOS process.
- a nickel film (thickness 100 nm) for forming a polycrystalline silicon film was formed on the entire surface.
- heat treatment is carried out to
- the heat treatment conditions were set to a temperature of 400 ° C. and a heat treatment time of 5 minutes.
- excess Ni was removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide water. Through the above process, the structure shown in FIG. 3 was formed.
- a silicon oxide film (3 nm in thickness) is formed on a silicon substrate by thermal oxidation, and an adhesion layer (0.06 ML) and an oxide layer are formed on this oxide film as follows.
- Ni Si layer 120 nm in thickness
- hafnium silicon oxide was deposited on the silicon oxide film using atomic layer deposition (ALD).
- ALD atomic layer deposition
- Deposition conditions are substrate temperature 3 At 00 ° C, tetragetylaminohafnium (Hf [(CH 3) N]) and tri-trile as film-forming materials.
- Hf raw material gas was supplied for 10 seconds by publishing nitrogen carrier gas at a flow rate of 20 sccm.
- H20 was again supplied to acidify the Hf and elemental silicon surfaces. At this time, the amount of the acid hafnium component (Hf-O component) contained in the silicon nitride silicon oxide film deposited on the silicon oxide film was 0.33 ML in molecular layer conversion.
- a polycrystalline silicon film having a thickness of 60 nm was deposited by CVD (Chemical Vapor Deposition) and subjected to an annealing treatment under the same conditions as the active energy of the source / drain diffusion layer used in a normal CMOS process.
- a nickel film (10 O nm in thickness) for silicidation of the polycrystalline silicon film was formed on the entire surface.
- heat treatment was performed to form NiSi. Heat treatment conditions are warm
- the heat treatment time was set to 5 minutes.
- excess Ni was removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide water. Through the above process, the structure shown in Fig. 4 was formed.
- FIG. 3 and FIG. 4 were taken of the cross section of the substrate on which the silicide layer was formed, using a scanning electron microscope (SEM) (trade name: S5000, manufactured by Hitachi High-Technologies).
- SEM scanning electron microscope
- the silicide layer Ni Si
- the adhesion between the silicon oxide film and the silicide layer is improved in the example shown in FIG. I understand that.
- the adhesion between the silicon oxide film and the silicide layer was low even if the adhesion layer was not provided, and no peeling was observed when the NiSi layer was formed. It was confirmed that the phenomenon was remarkable when the NiSi layer was formed.
- the adhesive layer in the present invention is a region including a metal oxide component provided at the interface between the gate oxide film and the gate electrode.
- the metal oxide component is preferably provided in a range of 0.1 ML (monolayer) or more and 0.1 ML or less as the coverage of the interface in molecular layer conversion. More than 03ML and less than 0. 07ML are more preferable.
- this metal oxide component as the amount of metal atoms at the interface, is lE 13 cm Above, lE14cm_ 2 following ranges preferably instrument 3E13cm_ 2 or more, 7E13cm_ 2 following range is preferable.
- the formation region of the metal oxide component of the adhesion layer is too wide or the amount is too large, the Fermi leveling phenomenon occurs, and it becomes difficult to control the threshold value by the impurity.
- the physical film thickness increases, the equivalent oxide thickness (EOT) of the gate insulating film increases, and the driving capability of the transistor decreases.
- EOT equivalent oxide thickness
- metal oxide of the adhesion layer examples include Hf, Ta, Zr, La, Ti, Y and Al, and among these, metals selected from Hf, Zr, La and Ta are preferable.
- the metal oxide of the adhesion layer is Hf02, HfSiO, HfSiON, TaO, TaSiO, TaSiON, ZrO, ZrSiO, ZrSiON
- the genus acid is preferred.
- the thickness of the Ni Si layer constituting the gate electrode is the same as that of the impurity-containing Ni Si layer.
- a thickness that can ensure the effective work function that can be originally obtained, and can be set to, for example, 10 nm or more, preferably 20 nm or more. On the other hand, it can be set to 120 nm or less, preferably 100 nm or less from the viewpoint of miniaturization.
- the thickness of the low resistance layer of the second embodiment is sufficiently thick within a range that does not affect the value of the effective work function determined by the silicide that constitutes the lower layer portion of the gate electrode. I like it.
- the thickness of the low resistance layer can be set to, for example, 10 nm or more, preferably 20 nm or more, for obtaining sufficiently low resistance, and 120 nm from the viewpoint of the effect on the effective work function and easiness of formation. In the following, preferably, it can be set to 100 nm or less.
- the thickness of the gate electrode lower layer portion (NiSi electrode) of the second embodiment is the same as that of the NiSi electrode 8, 9 of the first embodiment.
- the size of the gate electrode (including the low resistance layer) in the present invention can be set to a height (length in a direction perpendicular to the substrate) of 200 nm or less, further 100 nm or less, from the viewpoint of miniaturization. 20 nm or more is preferable in terms of securing the operation performance and manufacturing accuracy. 40 nm or more is more preferable.
- the gate length can be set, for example, in the range of 10 to: LOO nm.
- the Ni Si layer constituting the gate electrode that is, the first and second embodiments
- the NiSi electrode is a silicide layer containing a NiSi phase as a main crystal component. This silicide
- the layer should have a thread structure represented by Ni Si _ (0. 6 ⁇ x ⁇ 0. 9), 0.70 ⁇ x ⁇ 0.
- the low resistance layer in the present invention ie, the low resistance layer 11 of the second embodiment, is preferably a silicide layer containing a Ni monosilicide (NiSi) phase as a main crystal component, in terms of resistance value.
- This silicide layer preferably has a composition represented by Ni Si _ (0.4 ⁇ x ⁇ 0.6).
- the crystal phase of nickel silicide is mainly composed of NiSi, NiSi, Ni Si, Ni Si, Ni Si, Ni Si,
- the gate electrode is Ni 2 Si etc., and mixtures of these can also be formed. Therefore, the gate electrode is
- the average composition of the resulting silicide may deviate from the stoichiometric composition, but it is desirable to be within the above composition range.
- the Ni Si layer and the low resistance layer constituting the gate electrode consist of a single crystal as much as possible from the point of suppressing the variation of the device performance, and a constant reflecting this
- the gate insulating film in the present invention is not particularly limited as long as threshold control can be performed by the impurities contained in the gate electrode, but at least a portion including the upper surface of the insulating film on the gate electrode side It is preferable to have a silicon oxide film or a silicon oxynitride film in part).
- the gate insulating film may be a silicon oxide film, a silicon oxynitride film, a laminated film of a silicon oxide film and a silicon oxynitride film, a silicon oxide film or a silicon oxynitride film provided on the uppermost layer portion, and the like. A stacked film with another insulating film can be used.
- the thickness of the gate insulating film is preferably set as thin as possible within the range where its function can be exhibited, but can be set, for example, to a thickness of 1 to 2 nm.
- An element isolation region 2 formed by STI (Shallow Trench Isolation) technology, and a silicon substrate 1 having a P-type active region and an n-type active region are prepared, and the process shown in FIG. 5 Form the laminated structure shown in (a).
- STI Shallow Trench Isolation
- a gate insulating film 3 a (thickness 1.1 to 1.2 nm) is formed by thermal oxidation on a silicon substrate on which elements have been separated.
- the adhesion layer 3 b is formed on the gate insulating film 3 a as follows.
- atomic layer deposition is used to form an adhesion layer made of hafnium silicon oxide (HfSiO).
- ALD atomic layer deposition
- HfSiO hafnium silicon oxide
- a substrate temperature 200 to 500 ° C.
- tetragetilaminohafnium Hf [(CH 2) N]
- trisdimethylaminosilicon as raw materials for film formation.
- H 2 O is supplied as an oxidant gas onto the silicon dioxide film (first step).
- a silicon source gas is supplied by a mass flow controller at a flow rate of 2 to 20 sccm (second step).
- the silicon source gas partial pressure during film formation can be set to 1 ⁇ 10 " 4 Torr (0.03 Pa) force as well as 0.3 Torr (40. OPa), the supply time is 0 to 300 seconds, and the temperature of the silicon source can be set to 45 ° C.
- supply the Hf source gas from the container at 87 ° C.
- Hf is supplied under the same conditions as the first step for the purpose of oxidizing the Hf and silicon element surface (fourth step).
- First Step Force After performing the fourth step, the second step force repeats the fourth step.
- the second process force can also carry out one cycle of the fourth process in the range of 1 to 10 cycles. In addition, you may provide the process to substitute between each process.
- An adhesion layer was formed on the silicon oxide film by such a process. At this time, the deposition amount in Hf atomic equivalent was 6 ⁇ 10 13 cm ′ ′ 2 (0.06 ML).
- the adhesive layer in the present invention can also be formed by the following method.
- PVD physical vapor deposition
- hafnium and silicon are simultaneously deposited on the silicon oxide film by the sputtering method (co-sputtering method), and oxidation treatment is performed.
- the sputtering apparatus one provided with two sputtering targets of hafnium and silicon can be used. Sputtering damage to the silicon oxide film can be minimized by setting the sputtering power to 15 to 100 W and setting the distance between the target and the silicon wafer 240 to 330 mm. . 20: Generate a plasma using LOO sccm Ar gas. By flowing lOOsccm Ar gas, the background pressure of the chamber can be maintained at 1.6 x 10 13 Torr (2.1 3 x 10 15 Pa).
- Hf and Si are co-sputtered on a silicon oxide film by depositing for 5 seconds with a sputtering power of 15 W, an Ar flow rate of 100 sccm, a substrate rotational speed of 60 rpm, and a distance between the target and the silicon wafer of 300 mm. Deposited. Adhesion amount of Hf in this case was of 4 X 10 13 c m_ 2 ( 0. 04ML). After that, Hf and Si were sputtered by oxidizing the silicon wafer in an oxygen atmosphere at a normal pressure of 800 ° C. for 30 seconds to acidify the Hf and Si, and the HfO and HfSiO become dense.
- a layer of fouling was formed.
- a polycrystalline silicon film 13 having a thickness of 60 nm is deposited by CVD (Chemical Vapor Deposition) on the gate insulating film 3b on which the adhesion layer 3b is formed, and then a silicon oxide film having a thickness of 15 nm is formed.
- the SiO mask 19 is formed.
- the P-type MOSFET region is covered with a resist mask 20, and phosphorus (P) is ion-implanted into the polycrystalline silicon film of the N-type MOSFET region with lO keV.
- phosphorus P
- Injection amount of phosphorus can be set to 4 X 10 15 cm_ 2.
- the N-type MOSFET region is covered with a resist mask 20 to implant boron (B) into the polycrystalline silicon film of the P-type MOSFET region at 3 keV.
- boron B
- Injection of boron can be set to 4 X 10 15 cm_ 2.
- the laminated film (the gate insulating film 3a, the adhesion layer 3b, the impurity-implanted polycrystalline silicon film 14a, 14b, the SiO mask 19) is subjected to the lithography technique and the RIE (React)
- silicon nitride is applied to cover the gate pattern by the CVD method.
- a gate sidewall 7 is formed by depositing a film (not shown) and a silicon oxide film and then etching back.
- ion implantation is performed again, and then active ion is performed to form the source / drain diffusion region 5.
- FIG. 6 (e) silicon nitride is applied to cover the gate pattern by the CVD method.
- the extension diffusion region and the source / drain region described above are formed by ion-implanting an impurity of the opposite conductivity type to each active region while masking one of the p-type active region and the n-type active region. Can.
- a nickel film 15 is deposited on the entire surface by sputtering, and then, as shown in FIG. 7 (h), the gate pattern, gate sidewall and device isolation are formed by salicide technology.
- the silicide layer 6 is formed only on the source / drain diffusion region using the region as a mask.
- a Ni monosilicide (NiSi) layer capable of minimizing the contact resistance is formed as the silicide layer 6.
- a Co silicide layer or a Ti silicide layer may be formed.
- excess Ni is removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide water.
- an interlayer insulating film 10 made of a silicon dioxide film is formed by the CVD method so as to embed the gate pattern.
- the surface of the interlayer insulating film 10 is planarized by CMP (Chemical Mechanic Polishing) technology.
- the interlayer insulating film 10 is etched back, and the SiO mask 19 in the upper layer of the gate pattern is removed to form the impurity-implanted polycrystalline silicon films 14a and 14b.
- a nickel film 15 (thickness 100 nm) for forming the impurity-implanted polycrystalline silicon films 14 a and 14 b is formed over the entire surface.
- a temperature of 400 ° C. and a heat treatment time of 5 minutes can be set.
- excess Ni is removed by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide water.
- the structure of the first embodiment shown in FIG. 1 can be formed. Can. Thereafter, an interlayer insulating film is formed on the entire surface according to a conventional method. Thereafter, a desired semiconductor device can be formed in accordance with a normal process.
- FIG. 10 (a) corresponding to FIG. 9 (n) is formed.
- a silicon (Si) film 21 with a thickness of about 60 nm is formed on the entire surface by sputtering.
- the impurity-containing Ni in the N-type MOSFET region is formed by heat treatment.
- the upper layer portion of the 3 3 pole 17 and the Si film 21 are reacted to form a resistance layer region 18 respectively.
- the conditions of the heat treatment may be set, for example, in an inert gas atmosphere at 350 to 500 ° C. for 1 to 20 minutes, for example, in a nitrogen atmosphere for 2 to 5 minutes at 400 ° C. it can
- the excess Si film is removed by wet etching or dry etching.
- the structure of the second embodiment shown in FIG. 2 can be formed. Thereafter, an interlayer insulating film is formed on the entire surface according to a conventional method. Thereafter, a desired semiconductor device can be formed in accordance with a normal process.
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US7235501B2 (en) | 2004-12-13 | 2007-06-26 | Micron Technology, Inc. | Lanthanum hafnium oxide dielectrics |
US7776765B2 (en) * | 2006-08-31 | 2010-08-17 | Micron Technology, Inc. | Tantalum silicon oxynitride high-k dielectrics and metal gates |
US7563730B2 (en) * | 2006-08-31 | 2009-07-21 | Micron Technology, Inc. | Hafnium lanthanide oxynitride films |
US7544604B2 (en) | 2006-08-31 | 2009-06-09 | Micron Technology, Inc. | Tantalum lanthanide oxynitride films |
DE102010063778B4 (de) * | 2010-12-21 | 2018-05-09 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung einer Gateelektrodenstruktur mit erhöhter Strukturierungsgleichmäßigkeit |
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US6605513B2 (en) * | 2000-12-06 | 2003-08-12 | Advanced Micro Devices, Inc. | Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing |
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US7148546B2 (en) | 2003-09-30 | 2006-12-12 | Texas Instruments Incorporated | MOS transistor gates with doped silicide and methods for making the same |
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