JP4449190B2 - Voltage-driven semiconductor device gate drive device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
INDUSTRIAL APPLICABILITY The present invention is used in a voltage-driven semiconductor element gate driving device constituting a power conversion device, in particular, a power conversion device configured by connecting voltage-driven semiconductor elements in series in order to increase the voltage of the power conversion device. And a suitable gate driving device.
[0002]
[Prior art]
FIG. 9 shows an example of a chopper circuit using an IGBT (insulated gate bipolar transistor) as a voltage-driven semiconductor element. The DC power supply Ed is provided with an IGBT 1 on the upper arm and a freewheeling diode FWD 1 connected in antiparallel with the DC power supply Ed, and an IGBT 2 and FWD 2 connected in antiparallel with the lower arm on the lower arm. A load is connected to the IGBT 1. GDU1 and GDU2 are gate drive devices. Specifically, for example, as shown in FIG. 10, transistors TR1 and TR2, IGBTs Rg (on) and Rg (off) for turning on and off the IGBT, an interface circuit IF, and the like. Composed.
[0003]
Now, when the IGBT 2 in FIG. 9 is turned on, a current flows through the load. Next, when the IGBT 2 is turned off, the current flowing through the IGBT 2 from the load is commutated to the FWD 1 (free wheeling mode). When the IGBT 2 is turned on in this state, the FWD 1 is reversely recovered, and the current is switched again from the load to the route passing through the IGBT 2. At this time, it is pointed out that a large surge voltage is generated when the FWD1 reversely recovers when the freewheeling current commutated to the FWD1 is a low current of 1/10 or less of the element rating. FIGS. 11 and 12 show the state at that time, and an example in which a surge voltage higher than the rating is applied to the FWD 1 is shown. FIG. 12 is an enlarged view of the part (main part) of FIG.
[0004]
FIG. 9 shows an example in which one voltage-driven semiconductor element is used for one arm. However, the problem described above is that a plurality of (two in the figure) elements are provided for one arm as shown in FIG. The same applies to the power conversion device to be achieved, and the state at that time is indicated by a dotted line in FIG. This shows a voltage waveform applied to the IGBTs 1 and 2 during reverse recovery of the FWDs 1 and 2 of the upper arms when the lower arm elements IGBTs 3 and 4 are operated by the gate driving devices GDU3 and 4, respectively. It can be seen that a surge voltage exceeding the rating as indicated by the dotted line is applied to both IGBTs 1 and 2.
[0005]
[Problems to be solved by the invention]
Such a surge voltage sometimes greatly exceeds the rated breakdown voltage of the element, and in the worst case, the element may be destroyed. Therefore, conventionally, for example, by increasing the value of the gate-on resistance Rg (on) shown in FIG. 10, the turn-on time of the IGBT 2 is delayed, the time for holding the voltage on the IGBT 2 side is lengthened, and the voltage applied to the FWD 1 is increased. A method of suppressing the surge voltage by lowering the voltage is used. However, if the gate resistance is large, the voltage holding time increases and the turn-on loss increases. This increase in turn-on loss increases the total loss of the entire device, causing a problem that the operating frequency must be lowered or the output current must be lowered.
[0006]
Further, when a plurality of elements are provided on one arm to increase the voltage, a problem due to variations in element characteristics occurs in addition to the above problems. This problem is illustrated in FIG. 15, which shows a case where a difference occurs in the turn-on timing of the IGBT due to variations in element characteristics among a plurality of elements, resulting in an imbalance in voltage sharing. Here, for example, the IGBT 2 of the upper arm in FIG. 13 is turned on earlier, and the IGBT 1 is turned off at this time, so that an unbalance that voltage is applied only to the IGBT 1 occurs. At this time, there is a period in which the voltage obtained by adding the collector-emitter voltage VCE (1) of the IGBT 1 and the collector-emitter voltage VCE (2) of the IGBT 2 is not equal to the DC voltage Ed. This is due to resonance operation with the floating inductance Lm.
[0007]
In this way, voltage imbalance occurs. As a countermeasure, for example, as shown in FIG. 13, an IGBT 1 that turns on late by adding an RC snubber circuit including a snubber capacitor C and a snubber resistor R to each IGBT. The voltage increase rate (dv / dt) is reduced, and the voltage applied to the IGBT 1 is suppressed during the period (Δt) until the ON signal is input to the IGBT 1.
[0008]
When using IGBTs connected in series, as described above, by adding an RC snubber circuit to each IGBT, it is possible to prevent overvoltage application due to voltage imbalance when the turn-on timing is deviated and element destruction due to this. If an attempt is made to increase the time difference between allowable turn-on timings, the capacitor capacity of the added snubber must be increased, and as a result, the generated loss increases, so that the shape of the resistor R increases and the overall device also increases. Problem arises.
Therefore, an object of the present invention is to protect the IGBT without increasing the turn-on loss or increasing the snubber capacitor capacity.
[0009]
[Means for Solving the Problems]
In order to solve such a problem, the invention of claim 1 is a gate driving device for driving on and off a plurality of voltage-driven semiconductor elements connected in series to each arm of the power converter,
An overvoltage discrimination circuit that detects a voltage applied to the voltage-driven semiconductor element and determines whether or not the voltage-driven semiconductor element is overvoltage, and the voltage-driven semiconductor element is set to a voltage higher than a normal forward bias voltage when the voltage-driven semiconductor element is turned on. An overdrive circuit for turning on, and due to a difference in turn-on timing of each of the voltage-driven semiconductor elements connected in series, an imbalance occurs in the applied voltage of each voltage-driven semiconductor element, and an overvoltage is detected in the overvoltage determination circuit. Is detected, by turning on the voltage-driven semiconductor element to which the overvoltage is applied by the overdrive circuit at a voltage higher than a normal forward bias voltage, and applying the overvoltage to the voltage-driven semiconductor element. It is characterized by preventing the destruction of the original element.
[0010]
In the invention described in claim 1, wherein Once off overvoltage when the voltage-driven semiconductor element is detected, an overvoltage is added to re-on circuit for again on the detected voltage drive type semiconductor device, which is connected each of the series Further, it is possible to prevent overvoltage application to the voltage-driven semiconductor element due to voltage imbalance when the voltage-driven semiconductor element is turned off, and element destruction based on this. In the first or second aspect of the invention, the overdrive circuit may include a voltage application circuit that applies a voltage higher than a normal forward bias voltage to the voltage-driven semiconductor element for a predetermined time. Invention).
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a first embodiment of the present invention. Like FIG. 13, FIG. 1 shows a one-phase inverter composed of IGBTs Q1 to Q4 connected in series as voltage-driven semiconductor elements. Q1 and Q2 and the lower arm are constituted by series connection circuits of Q3 and Q4, and each element Q1 to Q4 is configured by providing an RC snubber circuit. That is, although the detection resistors R1 to R4 are added to the one shown in FIG. 13, the gate driving device GDU has an overvoltage compared to the conventional gate driving device shown in FIG. 10 as shown in FIG. The difference is that it includes a determination circuit OV and an overdrive circuit OD. The overvoltage discrimination circuit OV discriminates whether or not the voltage detected by the detection resistor is an overvoltage, and the overdrive circuit OD superimposes a forward bias voltage on the IGBT when the IGBT is turned on. Dd1 is a backflow prevention diode. When it is not necessary to separate the FWD from the IGBT, these are collectively referred to as a voltage-driven semiconductor element Q or IGBT.
[0012]
With reference to FIG. 2B, the operation of the gate driving device will be described.
Assuming that Q2 is turned on first, the collector-emitter voltage VCE (Q1) of Q1 starts to rise, and when the voltage detected by the detection resistor reaches the overvoltage detection level, the overvoltage determination circuit OV is in an overvoltage state. Judge. As a result, the overdrive circuit OD operates to turn on Q1 at a voltage higher than the normal forward bias voltage (overdrive operation). By operating Q1 through the overdrive circuit OD, it is turned on faster than the normal turn-on operation.
[0013]
This is shown in FIG. 3, and when the overdrive circuit OD is used, as shown by the solid line in FIG. 3, the turn-on can be turned on faster by ΔT than when the overdrive circuit OD indicated by the dotted line is not used.
By doing so, the collector-emitter voltage VCE rapidly decreases when an overvoltage is applied to Q1, so that the destruction of Q1 due to the overvoltage application can be prevented at high speed, and the generated loss is reduced.
[0014]
FIG. 4 shows a specific example of the overdrive circuit OD. The broken line portion is the overdrive circuit OD, and the other portions are the same as in FIG. That is, the overdrive circuit OD includes a field effect transistor TR3 such as a MOSFET, logic IC1 and IC2 such as an inverter and a NOR gate, a DC power source V, and a timer circuit TM.
When an overvoltage detection signal is input to the circuit OD from the overvoltage determination circuit OV to the timer circuit TM, the output of the logic IC1 changes from H (high) to L (low), and TR1 is turned off. At the same time, TR3 is turned on, and the gate-emitter voltage of the IGBT is biased to the DC power supply voltage V. This voltage V is higher than the normal forward bias voltage (here, forward bias voltage 15V, overdrive voltage 20V). After the timer time, TR3 is turned off and the overdrive circuit OD is disconnected, so that the normal forward bias voltage is restored.
[0015]
FIGS. 5A and 5B are explanatory views for explaining a second embodiment of the present invention. FIG. 5A shows a gate drive device, and FIG. 5B shows a detailed example of the overdrive circuit.
This is an overdrive circuit configured as shown in FIG. 2B. The difference from FIG. 2A is that the overdrive circuit OD is directly connected to the gate terminal (G) of the IGBT. The interface circuit IF has a function of disconnecting the normally-on circuit (turning TR1 off) during circuit operation. In this example, the gate resistance (R) can be arbitrarily set during overdrive, and the IGBT can be protected at a high speed when voltage imbalance occurs. The circuit operation is the same as in FIG.
[0016]
FIGS. 6A and 6B are explanatory views for explaining a third embodiment of the present invention. FIG. 6A is a gate drive device, and FIG.
As apparent from FIG. 6 (a), an on / off discrimination circuit OF and a re-on circuit RO are added to that shown in FIG. 2 (a). The on / off discrimination circuit OF discriminates the turn-on and turn-off of the IGBT element, and the re-on circuit RO turns it on again when the IGBT is turned off.
As apparent from FIG. 6 (b), the operation at turn-on is exactly the same as that of FIG. 2 (b) and FIG. 3, and will be described below only when voltage imbalance occurs at turn-off.
[0017]
If the IGBT collector-emitter voltage detected via the detection resistor reaches the overvoltage detection level when the IGBT (Q1) is turned off, the overvoltage determination circuit OV determines that the overvoltage state is present. The on / off determination circuit OF receives the output of the circuit OV and activates the re-on circuit RO, so that the turn-on operation (re-on) is started by the re-on circuit RO. When Q1 is turned on again, the collector-emitter voltage decreases, so that it is possible to prevent an overvoltage from being applied to Q1 until Q2 is turned off.
Thus, the voltage imbalance at turn-on can be suppressed by the overdrive circuit, and the voltage imbalance at turn-off can be suppressed by the re-on circuit.
[0018]
FIG. 7 is a block diagram showing an application example of the present invention.
This is to cope with a surge voltage at the time of FWD reverse recovery, and a delay circuit composed of a resistor R and a capacitor C, a resistor Rg (on) 1 and a transistor TR10 are added to the conventional gate driving device shown in FIG. Configured.
Therefore, when TR1 is turned on via the interface circuit IF, the gate of the IGBT is first driven via the resistor Rg (on). Thereafter, when a certain time determined by the CR time constant of the delay circuit elapses, TR10 is turned on, whereby the gate of the IGBT is driven by the parallel resistance of the resistor Rg (on) and the resistor Rg (on) 1. At this time, since the parallel resistance value is smaller than the resistance Rg (on), if this gate driving device is used, the gate of the IGBT is driven with a high resistance at the beginning and with a low resistance after a certain time. The delay circuit on the transistor TR2 side is for adjusting the turn-off timing by the amount delayed on the TR1 side.
[0019]
FIG. 8 is a waveform diagram for explaining the operation of FIG.
When the gate drive device of FIG. 7 corresponds to the GDU2 shown in FIG. 9 and when the TR1 is turned on and the IGBT 2 is operated via the interface circuit IF, as shown in the GDU2 waveform of FIG. It drives by high resistance until the period t1 at the time of reverse recovery, and suppresses the surge voltage on the FWD1 side by holding the voltage on the IGBT2 side. In the period t2, which is the time of reverse recovery of a large current, the turn-on time is shortened by driving with a low resistance, and the turn-on loss is reduced. As a result, the collector-emitter voltage, the FWD1 voltage, and the current waveform of the IGBT 2 are as shown in the figure, and it can be seen that the surge voltage is suppressed as compared with the cases of FIGS. Note that the collector-emitter voltage, the FWD1 voltage, and the current waveform of the IGBT 2 indicate the operation at a large current with a solid line and the operation at a low current with a dotted line.
[0020]
The above is the case where there is a single element of the arm as shown in FIG. 9. However, in the case where there are a plurality of elements of the arm as shown in FIG. 13, the gate driving device shown in FIG. In addition, by driving with a low resistance after a certain time, the surge voltage can be suppressed and the turn-on loss can be reduced. FIG. 14 shows the state at this time, and shows voltage waveforms applied to the IGBTs 1 and 2 during reverse recovery of the FWD of the upper arm when the lower arm elements IGBT 3 and 4 are operated by the gate drive units GDU 3 and 4. Yes. That is, the voltage on the IGBT 2 side that reversely recovers as early as Δt overlaps with the voltage shared on the IGBT 1 side, and a surge voltage is generated as indicated by the dotted line, which may lead to element destruction. However, in the reverse recovery operation when the gate driving device shown in FIG. 7 is used, it is possible to suppress the generation of surge voltage as shown by the solid line and to minimize the voltage sharing on the IGBT 2 side that reversely recovers faster by Δt. This makes it possible to prevent element destruction.
[0021]
【The invention's effect】
According to the first aspect of the present invention, when each arm of the power conversion device including the inverter is configured by connecting voltage-driven switching elements such as IGBTs in series, the elements are detected from the overvoltage generated by the voltage imbalance between the elements. Can be protected at a higher speed than the conventional case, and the capacitor capacity of the charge / discharge snubber can be reduced, so that the apparatus can be miniaturized. In addition, since the overdrive circuit is operated at a voltage higher than a normal forward bias voltage, the loss generated is small and the turn-on loss is hardly increased.
Further, by adding a re-ON circuit as in claims 2 and 3, it is possible to prevent element destruction due to an overvoltage at the time of turn-off as well as at the time of turn-on.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.
FIG. 2 is a specific example of a gate driving device and an operation explanatory diagram thereof.
FIG. 3 is an explanatory diagram of an overdrive operation.
FIG. 4 is a circuit diagram showing a specific example of an overdrive circuit.
FIG. 5 is an explanatory diagram for explaining a second embodiment of the present invention.
FIG. 6 is an explanatory diagram for explaining a third embodiment of the present invention.
FIG. 7 is a block diagram showing an application example of the present invention.
8 is a waveform diagram for explaining the operation of FIG.
FIG. 9 is a configuration diagram illustrating a conventional example of a chopper circuit.
FIG. 10 is a circuit diagram showing a conventional example of a gate driving device.
11 is an operation explanatory diagram of FIG. 10; FIG.
12 is an enlarged view of a main part of FIG.
FIG. 13 is a circuit diagram showing one phase of an element serial connection type power converter.
FIG. 14 is a diagram illustrating an operation during reverse recovery in FIG. 13;
FIG. 15 is an explanatory diagram of a voltage unbalance operation in FIG. 13;
[Explanation of symbols]
Q: Insulated gate bipolar transistor switch (IGBT), GDU: Gate drive device, Ed: DC power supply, R: Resistance, C: Capacitor, D, Dd1 ... Diode, TR ... Transistor, IF ... Interface circuit, OV ... Overvoltage discrimination circuit OD: Overdrive circuit, TM: Timer circuit, OF: On / off discrimination circuit, RO: Re-on circuit.

Claims (3)

A gate driving device for driving on and off a plurality of voltage-driven semiconductor elements connected in series to each arm of a power converter,
An overvoltage discrimination circuit that detects a voltage applied to the voltage-driven semiconductor element and determines whether or not the voltage-driven semiconductor element is overvoltage, and the voltage-driven semiconductor element is set to a voltage higher than a normal forward bias voltage when the voltage-driven semiconductor element is turned on. An overdrive circuit for turning on, and due to a difference in turn-on timing of each of the voltage-driven semiconductor elements connected in series, an imbalance occurs in the applied voltage of each voltage-driven semiconductor element, and an overvoltage is detected in the overvoltage determination circuit. Is detected, by turning on the voltage-driven semiconductor element to which the overvoltage is applied by the overdrive circuit at a voltage higher than a normal forward bias voltage, and applying the overvoltage to the voltage-driven semiconductor element. A gate drive device for a voltage-driven semiconductor element, characterized by preventing element destruction. When an overvoltage is detected at the time of turn-off of the voltage driven type semiconductor element, overvoltage adds re-on circuit which again turns on the detected voltage driven type semiconductor element, upon turn-off of each of the series-connected voltage-driven semiconductor element 2. The gate drive device for a voltage-driven semiconductor element according to claim 1, wherein an overvoltage is applied to the voltage-driven semiconductor element due to a voltage imbalance and an element breakdown based thereon is prevented.   3. The voltage drive according to claim 1, wherein the overdrive circuit includes a voltage application circuit that applies a voltage higher than a normal forward bias voltage to the voltage-driven semiconductor element for a predetermined time. Type semiconductor device gate drive device.

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