JP2005328668A - Drive circuit of self arc-extinguishing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve an effect for suppressing a surge voltage generated in the reverse recovery of a reflux diode by reducing a switching loss and shortening a switching time. <P>SOLUTION: This drive circuit comprises: a means for applying forward and reverse biases to a control terminal of a semiconductor device; a preliminary charging means for performing preliminary charging by applying a prescribed voltage to the control terminal when turning-off; and a timing control means for controlling operation timings of these means. A Zenner diode 3 is connected between a collector and an emitter of an IGBT 1 of each upper and lower arm, and after turning off the IGBT 1 of one arm, voltages having values that act as polarities for turning on the IGBTs 1 and are lower than a threshold are applied to the control terminal of the IGBT 1 of one arm over a certain period until the completion of the turning-on of the IGBT 1 of the other arm by switches 7c, 7d and dividing resistors 9c, 9d. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a drive circuit for a self-extinguishing semiconductor element that suppresses a surge voltage during switching in a power conversion device that performs power conversion by switching a self-extinguishing semiconductor element such as an IGBT or a MOSFET. is there.

An AC motor driving device (so-called inverter), an uninterruptible power supply (UPS), and the like perform power conversion by switching a self-extinguishing power semiconductor element (power semiconductor element).
FIG. 7 is a block diagram showing a circuit configuration of this type of power conversion device. In the main circuit of the power converter, two IGBTs 1 as self-extinguishing semiconductor elements each having a free-wheeling diode 2 connected in reverse parallel are connected in series at both ends of the DC power supply 12 to form upper and lower arms for one phase. These upper and lower arms are connected in parallel for three phases. And the internal connection point of the upper and lower arms of each phase becomes an AC output terminal, and is connected to the three-phase AC motor 10 as a load. Reference numeral 11A denotes a drive circuit for the IGBT 1. In the illustrated example, only the drive circuit for the IGBT of the upper and lower arms for one phase is shown for convenience.

  In the above configuration, the drive circuit 11A alternately switches the IGBTs 1 of the upper and lower arms of each phase to convert DC power into AC power, and this AC power is supplied to the electric motor 10. It is also known that when the IGBT 1 is turned off, an operation of circulating the load current through the reflux diode 2 is performed.

  Here, as a switching method of the IGBT 1, the control unit 14 generally performs PWM control in which the comparison operation unit 14 c compares the magnitude relationship between the output voltage command 14 a and the reference triangular wave 14 b to determine a switching pattern. The switching pattern is distributed to the upper and lower arms of the three phases in the pulse distribution unit 13, and the IGBTs 1 of the upper and lower arms are alternately switched via the drive circuit 11A.

  FIG. 8 shows an example of the switching pattern (gate voltage) of the upper arm side IGBT and the lower arm side IGBT in FIG. As shown in the figure, the IGBTs of the upper and lower arms are alternately turned on and off alternately. However, since the IGBT has a switching delay time (turn-off time), the IGBTs of the upper and lower arms connected in series are simultaneously turned on. In order to prevent the DC power supply 12 from being short-circuited, a dead time for turning off the IGBTs of the upper and lower arms is usually provided as a short-circuit prevention period.

  In the above-described conventional power converter, the surge voltage generated when power semiconductor elements such as IGBTs and freewheeling diodes are switched becomes excessive, and the switched voltage or the element is connected in antiparallel with the surge voltage. There is a case where the existing element is deteriorated or destroyed.

9A and 9B show a state in which a surge voltage is generated when the IGBT is turned off. FIG. 9A is a circuit diagram of one phase of the power conversion device, and FIG. 9B is a waveform diagram of voltages and currents of each part of FIG. 9A. It is.
When the IGBT is turned off or the freewheeling diode is reversely recovered, a very high di / dt (current change rate) is generated. As shown in FIG. 9A, this current change rate appears as a surge voltage (L × di / dt) in FIG. 9B due to the floating inductance 15 (the inductance value is L) in the wiring between the DC power supply 12 and the IGBT 1. .

  For this reason, the higher the switching speed, that is, the greater the di / dt, and the longer the wiring length (the larger the wiring inductance value L), the higher the surge voltage. Then, this surge voltage countermeasure is particularly important.

Here, FIG. 10 shows a configuration of a general drive circuit 11A of the IGBT 1. This drive circuit 11A connects switches 7a and 7b made of semiconductor switches and resistors 9a and 9b in series with a forward bias drive power supply 5 and a reverse bias drive power supply 6 to turn on the IGBT 1 as shown in FIG. The switch 7a is turned on and the switch 7b is turned on to apply a forward bias or reverse bias to the gate of the IGBT 1 to turn the IGBT 1 on and off.
The on / off timing of the switches 7a and 7b is determined by the timing control circuit 8 in accordance with the on / off command signal sent from the control unit 14 of FIG.

Further, the gate charge / discharge speed of the IGBT 1 and thus the switching speed of the IGBT 1 can be adjusted by appropriately selecting the resistance values of the resistors 9 a and 9 b connected between the switches 7 a and 7 b and the gate of the IGBT 1.
That is, as the values of the resistors 9a and 9b are increased, the gate charge / discharge speed of the IGBT 1 is decreased and the switching speed of the IGBT 1 can be decreased, and di / dt at the time of switching is decreased, thereby suppressing the surge voltage. Can do.
However, when the surge voltage is suppressed by the above method, there is a problem that the loss in the switching operation and the switching time delay increase as a whole.

On the other hand, in order to suppress this type of surge voltage, for example, in Patent Document 1 to be described later, a Zener diode 3 as a voltage clamp element is connected between the collector and gate of the IGBT 1 in the direction shown in FIG. advance, by setting the breakdown voltage V _z below the breakdown voltage between the collector and emitter of IGBT 1, suppressing a surge voltage during switching below the breakdown voltage of the IGBT 1, the so-called dynamic clamp circuit is disclosed .

In operation of FIG. 12, when the surge voltage reaches the breakdown voltage V _z of the Zener diode 3, the gate input capacitance 16 flows into the gate of IGBT1 breakdown current as shown by the dotted line via the Zener diode 3 is charged Therefore, during the period when the gate voltage of the IGBT 1 rises and the surge voltage is generated, that is, during the period when the Zener diode 3 is broken down, the gate voltage is maintained at or above the threshold voltage _{Vth of the} IGBT.
As a result, the discharge rate of the gate of IGBT1 is suppressed, di / dt will be limited to a value such that the surge voltage is the breakdown voltage V _z of approximately Zener diode, it can be made gentle turn it can.

However, even in such a dynamic clamp circuit, there is no effect on the surge voltage generated when the freewheeling diode connected in reverse parallel to the off-side IGBT of the arm facing the arm performing the switching operation is reversely recovered. .
That is, as shown in FIG. 8, the gate voltage of the off-side IGBT is normally applied with a negative bias in order to maintain the off state, so that the surge voltage generated during reverse recovery of the freewheeling diode 2 is the zener diode. This is because, when the breakdown voltage _Vz is reached, the Zener breakdown current does not flow in the direction of charging the gate input capacitor 16 of the off-side IGBT but bypasses the reverse bias drive power supply 6 and flows.

13A and 13B show the above switching operation waveforms. FIG. 13A is an operation waveform diagram when the IGBT 1 is turned off, and FIG. 13B is an operation waveform diagram when the freewheeling diode 2 is reversely recovered.
In the turn-off operation of the IGBT 1 shown in FIG. 13A, the gate voltage V _GE of the IGBT 1 when the current is interrupted is approximately near the threshold voltage V _th , and the charging current from the Zener diode 3 to the gate input capacitor 16 is accompanied by the generation of the surge voltage Therefore, the gate voltage V _{GE of the} IGBT 1 rises, and the cutoff operation is performed in a balanced manner in that the collector-emitter voltage V _CE becomes equal to the Zener breakdown voltage V _z .

In contrast, the reverse recovery time of the freewheeling diode 2 shown in FIG. 13B, even if a surge voltage is generated, the gate voltage _{V GE} of IGBT1 is not rise to the threshold voltage _{V th.} This is because almost all of the Zener breakdown current flows to the reverse bias drive power source 6 side as described above. Therefore, an excessive surge voltage (V _CE ) is applied to the IGBT 1 as shown in FIG. 13B.
Therefore, in the prior art shown in FIG. 12, since the surge voltage cannot be suppressed during reverse recovery of the freewheeling diode 2, the surge voltage may cause destruction or deterioration of the element.

On the other hand, the surge voltage, which is the reverse recovery characteristic of the freewheeling diode, depends on the turn-on speed (turn-on current change rate di / dt) of the IGBT on the opposite arm side. That is, if the turn-on speed of the IGBT on the opposite arm side is fast, the reverse recovery speed of the freewheeling diode also becomes fast, and a surge voltage at the time of reverse recovery is likely to occur. In other words, if the turn-on of the IGBT on the opposite arm side is slow, the surge voltage during reverse recovery can be suppressed.
By utilizing this characteristic, Patent Document 2 below discloses a technique for adjusting the turn-on speed by gradually increasing the gate voltage of the IGBT. However, even in this case, since the rise of the gate voltage is slow, there are problems such as an increase in switching loss at turn-on and a delay in switching time.

Patent Document 3 below also discloses a drive circuit for a self-extinguishing semiconductor element for the purpose of preventing a delay in switching time of an IGBT and reducing a surge voltage and switching noise by suppressing di / dt and dv / dt. It is disclosed.
However, in this prior art, the switching time of the IGBT is shortened by operating the one-shot circuit by the voltage drop of the current change rate detecting inductance or the current detecting resistor connected between the main emitter terminal and the auxiliary emitter terminal of the IGBT. In order to obtain a desired switching time, there is a problem that the values of the inductance and the resistance are required to be strictly accurate, and the number of components is large and the circuit configuration is complicated.

JP 2001-231247 A (paragraphs [0004], [0005], FIG. 5 and the like) JP-A-2-179262 (page 3, lower right column to page 4, upper right column (action), page 4, lower right column, line 9 to page 5, lower left column, line 12, FIG. 2 etc.) Japanese Patent Laid-Open No. 10-32976 (paragraphs [0023] to [0028], FIG. 1, FIG. 2, etc.)

As described above in detail, the conventional techniques described in FIGS. 10 and 12, Patent Documents 1 to 3 and the like are insufficient in reducing switching loss and switching time, and at the time of reverse recovery of the freewheeling diode. There is room for improvement in the surge voltage suppression effect. In addition, further simplification is required for the circuit configuration.
Therefore, the present invention has been made to solve the various problems described above.

In order to solve the above-mentioned problem, the invention described in claim 1 is configured such that self-extinguishing semiconductor elements having diodes connected in reverse parallel are connected in series to form upper and lower arms, and the semiconductor elements of these upper and lower arms are A drive circuit for the semiconductor element in a power conversion device that performs power conversion by alternately turning on and off, means for applying a forward bias voltage and a reverse bias voltage to a control terminal of the semiconductor element, and turning off the semiconductor element In a drive circuit provided with preliminary charging means for performing preliminary charging by applying a predetermined voltage to the control terminal sometimes, and timing control means for controlling the operation timing of each of these means,
Between the input terminal and the control terminal of the semiconductor element of the upper and lower arms, a voltage clamp element for suppressing the surge voltage at the time of switching of the semiconductor element below the breakdown voltage of the semiconductor element, respectively,
The timing control means includes
After turning off the semiconductor element of one arm, at least for the period when the semiconductor element of the other arm is turned on, the polarity is set so that the semiconductor element is turned on with respect to the control terminal of the semiconductor element of one arm. A voltage having a value lower than the threshold value is output by the preliminary charging means.

  The timing control means may operate the pre-charging means continuously after turn-off of the semiconductor element of one arm as described in claim 2, or one of the timing control means as described in claim 3. It is desirable to operate the precharging means after a certain period of time has elapsed since the semiconductor element of the arm of the arm is turned off.

  According to the present invention, after the semiconductor element is turned off, the forward bias state is maintained for a certain period of time, so that the surge generated not only when the semiconductor element is turned off but also when the return diode on the opposite arm side is reversely recovered. Voltage can also be suppressed, and destruction and deterioration of the element can be prevented and reliability can be improved. In addition, the circuit configuration is relatively simple compared to the prior art disclosed in Patent Document 3, and can be realized at low cost.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and the same components as those in FIGS. 10 and 12 are given the same reference numerals.

In FIG. 1, reference numeral 11 denotes a drive circuit according to the present embodiment. The drive circuit 11 includes a series circuit of a forward bias drive power source 5 and a reverse bias drive power source 6 of the IGBT 1 having a Zener diode 3 connected between a collector and a base, and a series of a switch 7a, resistors 9a and 9b, and a switch 7b. A circuit and a series circuit of a switch 7c, resistors 9c and 9d and a switch 7d are provided, and these series circuits are connected in parallel. Here, the switches 7a to 7d are constituted by semiconductor switches. The interconnection points of the resistors 9a and 9b and the interconnection points of the resistors 9c and 9d are collectively connected to the gate of the IGBT 1, and the emitter of the IGBT 1 is connected to the interconnection point of the drive power sources 5 and 6.
Although not shown, an on / off command signal via the control unit 14 and the pulse distribution unit 13 of FIG. 7 is input to the timing control circuit 8, and the switches 7 a to 7 d are output by the output signal of the timing control circuit 8. Is on / off controlled.

In the above configuration, the gates of the IGBT 1 are controlled to turn on and off the IGBT 1 by alternately turning on and off the switches 7 a and 7 b by the output of the timing control circuit 8. Here, the resistors 9a and 9b are gate resistors. When the IGBT 1 is turned on, the driving power sources 5 and 6 are applied through the switch 7a and the resistor 9a and when the IGBT 1 is turned off through the switch 7b and the resistor 9b.
The resistance 9c, 9d are dividing resistors of the driving power source 5 and 6, a period of time the switch 7c which is after the turn-off of the IGBT 1, by turning on the 7d, gate voltage _{V GE} resistors 9c, is divided by 9d It operates to maintain a predetermined voltage value.
Here, the drive power supplies 5 and 6, the switches 7c and 7d, and the resistors 9c and 9d constitute pre-charging means in the present invention.

FIG. 2 is a timing chart showing the on / off command signal and the operation of the switches 7a to 7d. When switching the IGBT 1, as shown in the drawing, the switches 7 a and 7 b are alternately turned on and off in accordance with the on / off command signal to apply a forward bias or a reverse bias to the gate of the IGBT 1.
Here, in this embodiment, at the timing when one IGBT 1 is switched from on to off, the control operation of the timing control circuit 8 causes the switches 7a and 7b to turn on the opposing arm side IGBT, specifically, for a certain period Δt. Is turned off only for a period until completion of the operation, and the switches 7c and 7d are held in the on state. As a result, a voltage value obtained by dividing the voltage sum of the drive power supplies 5 and 6 by the voltage dividing resistors 9c and 9d is applied to the gate of the IGBT 1 shown in FIG.

The divided voltage value is higher than 0 [V] and lower than the threshold voltage (turn-on gate voltage value) _{Vth of the} IGBT 1, and preferably about 1 [V] from the threshold value _Vth . The resistance values of the voltage dividing resistors 9c and 9d are set so as to be low within the range of. For example, when the threshold voltage _{Vth of the} IGBT 1 is 6 [V], the voltage by the voltage dividing resistors 9c and 9d is set to 5 [V].
During this time, the Zener diode 3 connected between the gate and the collector of the IGBT 1 performs an operation of clamping the surge voltage generated when the IGBT 1 is turned off to the breakdown voltage _Vz .

On the other hand, the reflux diode 2 for a surge voltage generated at the time of reverse recovery, the zener breakdown current in a direction for charging the gate input capacitance 16 from the collector of the IGBT1 When the surge voltage reaches the breakdown voltage V _z of the Zener diode 3 Flows in. Here, since it is charged to the vicinity of approximately the threshold voltage V _th gate voltage as described above, IGBT 1 is easily migrate to the on state, to clamp a surge voltage by the breakdown voltage V _z of the Zener diode 3 be able to.
The reverse recovery operation of the return diode 2 on the opposite arm side is completed, that is, after the IGBT 1 is turned on, the switch 7c and 7d are turned off and the switch 7b for applying a reverse bias is turned on in the drive circuit of the IGBT 1 on the arm side already turned off. The reverse bias is applied continuously. Thereby, the OFF state of IGBT1 can be hold | maintained stably.

FIG. 3 is a timing chart of the gate voltage of the IGBT 1 showing the above-described operation. 4A is an operation waveform diagram of the IGBT 1 when the IGBT 1 is turned off, and FIG. Note that the dotted waveform in FIG. 3 and FIG. 6 described later indicates an increase in the gate voltage V _GE during the surge voltage clamping.
From these figures, the clamping operation of the surge voltage by the breakdown voltage IGBT1 by breakdown current flows exceeds V _z of the Zener diode is conducted surge voltage is generated, the threshold V _th near the gate voltage V _GE of IGBT1 As you can see, it rises. Accordingly, the discharge rate of the gate been suppressed, it is possible to slowly perform the turn-off while limiting the di / dt as a surge voltage is in the vicinity of substantially the breakdown voltage V _z.
FIG. 5 is a timing chart showing the relationship between the gate voltage of the IGBT 1 of the upper and lower arms, the collector current of the IGBT 1 of the upper arm, the current and voltage of the freewheeling diode 2 of the lower arm.

Next, FIG. 6 shows the gate voltage waveform of the IGBT 1 of the upper and lower arms in the second embodiment of the present invention. In the first embodiment, as shown in FIG. 3, by turning on the switch 7c, and 7d over a period of time subsequent to IGBT1 is turned off, holds slightly lower gate voltage V _GE than the threshold V _th However, when the dead time is long, the IGBT 1 may be erroneously turned on due to the influence of external noise or the like.
That is, since the gate voltage V _GE is maintained at a level at which it can be turned on, there is a risk that the gate voltage V _GE is susceptible to noise.

Therefore, in the second embodiment, as shown in FIG. 6, immediately after the IGBT 1 is turned off, the switches 7c and 7d are not turned on, but the IGBT 1 of the opposite arm after a certain time Δt ′ has elapsed since the IGBT 1 was turned off. By turning on the switches 7c and 7d only at the timing of turning on the gate voltage _VGE , the gate voltage _VGE is maintained up to the vicinity of the threshold value _Vth , thereby preventing an unstable operation due to external noise.
It is obvious that the control operation of the switches 7a to 7d in this case can be easily set by the timing control circuit 8 in the drive circuit 11.

It is a circuit block diagram which shows 1st Embodiment of this invention. It is a timing chart which shows the operation | movement of the on / off command signal and each switch in 1st Embodiment. It is a wave form diagram which shows the gate voltage of IGBT in 1st Embodiment. It is an operation | movement waveform diagram at the time of turn-off of IGBT in 1st Embodiment. It is an operation | movement waveform diagram of IGBT at the time of reverse recovery of the freewheeling diode in 1st Embodiment. It is a wave form diagram which shows operation | movement of 1st Embodiment. It is a wave form diagram which shows the gate voltage of IGBT in 2nd Embodiment of this invention. It is a block diagram which shows the circuit structure of a power converter device. It is a figure which shows the switching pattern of upper arm side IGBT in FIG. 7, and lower arm side IGBT. FIG. 8 is a circuit diagram for explaining how a surge voltage is generated when the IGBT is turned off in FIG. 7. FIG. 9B is a waveform diagram of voltage and current at each part in FIG. 9A. It is a block diagram of the general drive circuit of IGBT. It is operation | movement explanatory drawing of FIG. It is explanatory drawing of the prior art described in patent document 1. FIG. It is an operation | movement waveform diagram at the time of turn-off of IGBT. It is an operation | movement waveform diagram of IGBT at the time of reverse recovery of a free-wheeling diode.

Explanation of symbols

1: IGBT
2: Freewheeling diode 3: Zener diode 5, 6: Drive power supply 7a, 7b, 7c, 7d: Switch 8: Timing control circuit 9a, 9b, 9c, 9d: Resistor 10: Three-phase AC motor 11, 11A: Drive circuit 12 : DC power supply 13: Pulse distribution unit 14: Control unit 14a: Output voltage command 14b: Reference triangular wave 14c: Comparison calculation unit 15: Floating inductance 16: Gate input capacitance

Claims (3)

Self-extinguishing semiconductor elements having diodes connected in reverse parallel are connected in series to form upper and lower arms, and the semiconductor elements of these upper and lower arms are alternately turned on and off to perform power conversion in the power conversion device A driving circuit for a semiconductor device, comprising: a means for applying a forward bias voltage and a reverse bias voltage to a control terminal of the semiconductor device; and a preliminary charge for precharging by applying a predetermined voltage to the control terminal when the semiconductor device is turned off In a drive circuit comprising a charging means and a timing control means for controlling the operation timing of each of these means,
Between the input terminal and the control terminal of the semiconductor element of the upper and lower arms, a voltage clamp element for suppressing the surge voltage at the time of switching of the semiconductor element below the breakdown voltage of the semiconductor element, respectively,
The timing control means includes
After turning off the semiconductor element of one arm, at least for the period when the semiconductor element of the other arm is turned on, the polarity is set to turn on the semiconductor element with respect to the control terminal of the semiconductor element of one arm. A drive circuit for a self-extinguishing semiconductor element, wherein a voltage having a value lower than a threshold value is output by the precharging means. In the drive circuit of the self-extinguishing semiconductor element according to claim 1,
The drive circuit for a self-extinguishing semiconductor element, wherein the timing control means continuously operates the preliminary charging means after the semiconductor element of one arm is turned off. In the drive circuit of the self-extinguishing semiconductor element according to claim 1,
The drive circuit for a self-extinguishing semiconductor element, wherein the timing control means operates the precharging means after a lapse of a certain period after the semiconductor element of one arm is turned off.

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