JP4770304B2 - Semiconductor device gate drive circuit - Google Patents

Description

  The present invention relates to a gate drive circuit for a semiconductor element such as an IGBT, and more particularly to a drive circuit for a semiconductor element for constituting a power conversion device such as an inverter using a plurality of voltage-driven power semiconductor elements for a DC power supply. .

  FIG. 7 is a circuit diagram illustrating a general configuration example of an inverter using an IGBT. A DC voltage Ed is supplied from the DC power supply circuit 1 to the inverter circuit 2, and the inverter circuit 2 can drive the load 3 such as a motor by converting the DC voltage Ed to AC. A wiring inductance 4 exists between the DC power supply circuit 1 and the inverter circuit 2. In the inverter circuit 2, the upper and lower arms are configured by three sets of IGBTs 5 a to 5 f and diodes 6 a to 6 f connected in antiparallel. Each of these IGBTs 5a to 5f is connected to a gate terminal of each of the gate drive circuits 7 and 8, thereby being turned on / off.

  In FIG. 7, the gate drive circuit 7 is shown as being connected to the gate terminal of the IGBT 5a, and the gate drive circuit 8 is shown as being connected to the gate terminal of the IGBT 5b. Actually, a gate drive circuit (not shown) is connected corresponding to each of the IGBTs 5c to 5f. Moreover, when it is going to comprise the inverter of alternating current input instead of the direct-current power supply circuit 1, a rectifier, an electrolytic capacitor, etc. will be used.

  The control circuit 9 outputs the control signals Sa and Sb for the upper and lower arms to the gate drive circuits 7 and 8 of the IGBTs 5a to 5f. As will be described later, the upper and lower arms are controlled by these control signals Sa to Sf. The IGBTs 5a to 5f constituting the circuit are alternately controlled on and off.

  FIG. 8 is a circuit diagram showing a specific circuit configuration of the conventional gate drive circuit 7. A control signal Sa is supplied to the gate drive circuit 7 from the control circuit 9 via the insulator 10. This gate drive circuit 7 includes a drive DC power supply 11, a first series circuit comprising a turn-on switch element 12 and a gate resistor 13 for connecting the positive side of the DC power supply 11 and the gate of the IGBT 5a, and a DC power supply. 11 is composed of a second series circuit comprising a switch element 14 for turn-off and a gate resistor 15 for connecting between the negative electrode side of 11 and the gate of the IGBT 5a. The other gate drive circuit 8 and the like are configured in the same manner as described above.

  The first and second switching signals S1 and S2 extracted from the control signal Sa are controlled to either the H level or L level logic state, and the switching elements 12 and 14 are turned on / off by these switching signals S1 and S2. Operate. In the gate drive circuit 7, if the logical value of the switching signal S1 is L level, the switch element 12 is turned on, and the gate current Ig1 flows from the positive electrode of the DC power supply 11 to the IGBT 5a. The IGBT 5a is turned on by the gate current Ig1, and the collector current Ic starts to flow. When the logic value of the switching signal S2 is input to the gate drive circuit 7 at the H level, the switch element 14 is turned on and a gate current Ig2 in the opposite direction flows. The IGBT 5a is turned off by the gate current Ig2.

  The other IGBTs 5b to 5f constituting the inverter are also alternately turned on and off by the first and second switching signals S1 and S2 extracted from the same control signals Sb to Sf as the control signal Sa.

FIG. 9 is a circuit diagram showing an equivalent circuit of the IGBT 5b constituting the lower arm, and FIG. 10 is a signal waveform diagram showing current and voltage signal waveforms of each part when the IGBT 5b is turned off.
When the switch element 14 is turned on, the IGBT 5b is turned off, and the IGBT 5a of the opposite arm is turned on, the collector current Ic and the gate current Ig2 simultaneously flow through the IGBT 5b as shown in FIG. At this time, the charge charged in the gate-emitter capacitance Cge of the IGBT 5b is discharged through the gate resistor 15 by the gate current Ig2, and the collector current Ic gradually decreases.

  In FIG. 10, the period until the IGBT 5b is turned off by the control signal Sb is divided into five modes (mode M0 to mode M4), and the collector-emitter voltage Vce, the collector current Ic, and the gate Each of the waveforms of the voltage Vge between the emitters changes in each mode.

  In the mode M0, the control signal Sb inverted to the logical value L is output as an off command from the control circuit 9 (see FIG. 7) to the IGBT 5b constituting the lower arm. At this time, the switching signal S2 changes from the L level to the H level, but the waveforms Vce, Ic, and Vge do not change immediately. The period of this mode M0 is defined by the storage time until the switch elements 12 and 14 actually operate.

In mode M1, the switch element 12 is actually turned off and the switch element 14 is turned on. Therefore, the gate-emitter voltage Vge is reduced to a voltage value V _{GE (on)} (hereinafter referred to as an on-voltage ₎ that is sufficient to allow the current collector current Ic to flow. During this time, neither the collector-emitter voltage Vce nor the collector current Ic change.

In mode M2, when the gate-emitter voltage Vge falls below the on-voltage value VGE _(on) (Vge <VGE _(on) ), the collector-emitter voltage Vce starts to rise. However, the collector current Ic (shown by a dotted line in FIG. 9) flows through the gate-collector capacity (feedback capacity) Cgc of the IGBT 5b and the discharge current from the gate-emitter capacity Cge (shown by a one-dot chain line in FIG. 9). Is substantially balanced, so that the potential variation of the voltage Vge hardly occurs. This mode M2 continues until Vge <Vce.

  In mode M3, the feedback capacitance Cgc decreases rapidly, and the gate-emitter voltage Vge begins to decrease. Along with the rapid reverse charging of the feedback capacitor Cgc, the voltage Vce starts to rise rapidly toward the DC voltage Ed of the DC power supply circuit 1.

Here, in the IGBT 5b in the modes M2 and M3, the collector current Ic varies according to the gate-emitter voltage Vge as shown in the following equation (1).
Ic = gm (Vge−Vth) (1)
Here, gm is the mutual conductance, Vth is the gate threshold voltage of the IGBT 5b, and FIG. 3 to be described later shows an approximate relationship between the collector current Ic and the voltage Vge.

  In mode M4, when the voltage Vce between the collector and emitter of the IGBT 5b reaches the DC voltage Ed, the diode 6a on the opposite arm side starts to conduct, the collector current Ic decreases, and finally becomes zero. At this time, a surge voltage ΔV is generated in the voltage Vce due to the wiring inductance 4 and di / dt of the DC circuit portion. In the power conversion device, the surge voltage ΔV generally increases as the collector current Ic to be cut off increases or the resistance value of the gate resistor 15 decreases.

The reverse bias control circuit described in Patent Document 1 below can reduce the reverse bias voltage without prolonging the turn-off delay time, and can prevent a surge voltage failure.
FIG. 11 is a block diagram showing the configuration of the control circuit of the power converter, and FIG. 12 is a timing diagram showing the control signals Sa and Sb output to the IGBTs 5a and 5b.

  In the control circuit 9 of the power conversion device such as an inverter, the CPU 16 receives an external motor speed command or the like and outputs control signals Sa, Sb and the like to the IGBTs 5a to 5f via the dead time generation unit 17. In the dead time generation unit 17, control signals SA and SB having predetermined on-duty are received from the CPU 16, and the control signal delayed by a certain delay time Td only at the on-side timing of the control signals SA and SB as shown in FIG. Sa and Sb are generated.

  This delay time Td is generally set to several μs for an IGBT. As a result, it is possible to perform gate control so that the upper arm side IGBTs 5a, 5c, and 5e and the lower arm side IGBTs 5b, 5d, and 5f are not simultaneously turned on. This is because the inverter circuit 2 is in a DC short-circuited state when it is turned on at the same time, and an excessive current flows to cause the IGBTs 5a to 5f to be destroyed. In general, this delay time Td is referred to as dead time.

  Patent Document 2 below describes an invention of a semiconductor switching element drive circuit that can reliably maintain an OFF state of a semiconductor switching element and can significantly reduce a through current at turn-on.

  FIG. 13 is a diagram showing the waveform of the collector-emitter voltage Vce in the IGBT mode M4. Here, two signal waveforms at the time of turn-off are shown when the collector current Ic is large by the solid line and small by the dotted line.

  When the collector current Ic is a small current, the current value for reverse charging the feedback capacitor Cgc shown in FIG. 9 is also reduced, so that the rise (dv / dt) of the voltage Vce becomes gentle compared to the case of a large current. That is, the switching time of the IGBT 5b for the turn-off command is extended.

  Therefore, if the dead time Td is set short, a phenomenon occurs in which the IGBT 5a of the opposing arm is turned on before the collector-emitter voltage Vce reaches the DC voltage Ed.

  FIG. 14 is a signal waveform diagram showing current and voltage signal waveforms at various points when the IGBT is turned off. FIG. 15 shows a part of an inverter using an IGBT, and FIG. 16 shows an equivalent circuit of the IGBT. Here, the collector current Ic is smaller than the collector current Ic shown in FIG.

  After the control signal Sb on the lower arm side is turned off, the IGBT 5a on the opposite arm (upper arm) side is turned on at time t0 when the dead time Td has elapsed. At this time, if the voltage Vce between the collector and the emitter of the IGBT 5b does not reach the DC voltage Ed on the lower arm side, a DC short-circuit current Isht as shown in FIG. 15 flows, and the feedback capacitance Cgc is rapidly increased by this DC short-circuit current Isht. The battery is reversely charged.

At that time, the DC short-circuit current Ish flowing into the IGBT 5a is, as shown in FIG. 16, a path that passes through the gate resistor 15 (shown by a one-dot chain line) and a path that flows between the collector and emitter without passing through the gate resistor 15 (dotted line). Is indicated by). Here, when the resistance value of the gate resistor 15 is large to some extent, or when the wiring inside the gate drive circuits 7 and 8 is long and the wiring inductance value not shown here is large, the circuit impedance becomes high and the DC short-circuit current is increased. Ish becomes difficult to flow. As a result, the DC short-circuit current Ish that charges the feedback capacitor Cge is the main current path, and the gate-emitter voltage Vge also increases as shown in FIG. According to the above-described equation (1), the collector current Ic that can be passed through the IGBT 5a increases as the gate-emitter voltage Vge increases, so the collector current value that flows as the DC short-circuit current Isht increases.
Japanese Patent Laid-Open No. 5-129717 JP 2004-215458 A

  Thus, when the collector current Ic increases, a positive feedback phenomenon occurs in which the voltage Vge further increases, and the DC short-circuit current Ish flows excessively in the IGBT 5a. Further, since the DC short-circuit current Ish is cut off at the moment when the collector-emitter voltage Vce reaches the DC voltage Ed, there are problems such as an increase in turn-off loss, an increase in surge voltage, and an increase in noise generation. It was happening.

  In order to deal with these problems, for example, it is possible to take measures such as reducing the resistance of the gate resistor 15, reducing the wiring impedance, or extending the dead time Td. However, if the gate resistance 15 is set to a low resistance, there arises a problem that the surge voltage becomes high at the time of normal large current interruption. Further, when the dead time Td is extended, there is a problem that the control performance on the load side is generally lowered, such as uneven rotation of a motor driven as a load. For this reason, none of them can be a complete measure, and conventionally, the gate resistance value and the dead time Td have been set in a trade-off relationship with these.

In the invention disclosed in Patent Document 2, when the gate-emitter voltage Vge falls below a predetermined value, the IGBT gate-emitter is short-circuited by a switch element such as a MOSFET. ing. However, when the set value here is equal to the ON voltage value V _{GE (on)} of the mode M1 in FIG. 9, the gate resistance for turn-off becomes almost 0Ω, so the surge voltage ΔV becomes high due to a sudden turn-off operation. Surge voltage failure becomes a big problem.

  On the other hand, if the set value of the gate-emitter voltage Vge is made equal to the gate threshold voltage Vth of the mode M3, the mode M2 period becomes longer as in the case where the collector current Ic is small. During the mode M2, the opposing arm is turned on, and there is a problem that a large positive-current short-circuit current similar to that described above flows.

  The present invention has been made in view of the above points, and even if the dead time is set to the minimum necessary length, the gate drive of the semiconductor element can reliably prevent an excessive short-circuit current at the time of small current turn-off. An object is to provide a circuit.

In the present invention, in order to solve the above problem, in a gate drive circuit of a semiconductor element for constituting a power conversion device using a plurality of voltage-driven power semiconductor elements for a DC power supply, Gate driving means for on / off control, non-linear resistance means connected in parallel between the gate and emitter of the power semiconductor element via a switch circuit, and turning on the switch circuit with a delay from the output of an off command to the gate driving means The state is switched and held , and after the off command is output to the gate driving means, the control signal of the power semiconductor element forming the upper and lower arms of the power converter is set to prevent a short circuit when elapsed time approximately equal dead time which is a control means for holding by switching the switching circuit to the oN state, There is provided a gate drive circuit for a semiconductor element, wherein the power semiconductor element is turned off in a state where the resistance means is connected between the gate and emitter of the power semiconductor element by the control means. The
As another invention for solving the above problem, in a gate drive circuit of a semiconductor element for constituting a power converter using a plurality of voltage-driven power semiconductor elements for a DC power supply, the power semiconductor element is Gate driving means for on / off control, non-linear resistance means connected in parallel between the gate and emitter of the power semiconductor element via a switch circuit, and turning on the switch circuit with a delay from the output of an off command to the gate driving means Control means for switching to and holding the state, and the control means includes a current value detection circuit that detects a collector current value that has flowed before the power semiconductor element is turned off. In the current value detection circuit, When the collector current value falls below a third reference value after an off command is output to the gate driving means The switch circuit is switched on and held, and the power semiconductor element is turned off while the resistance means is connected between the gate and emitter of the power semiconductor element by the control means. A gate drive circuit for a semiconductor device is provided.

  According to the gate drive circuit of the semiconductor element of the present invention, when the power semiconductor element of the opposite arm is turned on during the rising period of the collector-emitter voltage during the small current turn-off operation, the gate-emitter terminal of the power semiconductor element Since the voltage between the gate and the emitter is clamped by the non-linear resistance means connected in parallel with the gate, the voltage between the gate and the emitter does not rise even when a short-circuit current reversely charging the feedback capacitor Cgc flows, and positive feedback Therefore, it is possible to reliably prevent a short-circuit current that increases in a continuous manner. Therefore, an excessive short-circuit current phenomenon at the time of small current turn-off does not occur, and a phenomenon such as a loss, surge voltage, or a large increase in noise can be prevented, and a dead-time can be minimized so that a motor becomes a load. The control performance can be improved.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram showing a gate drive circuit of a semiconductor element according to the first embodiment. Here, only parts different from the conventional gate drive circuit will be described, and the parts corresponding to the conventional circuit shown in FIG.

  The gate drive circuit 20 corresponds to a conventional circuit to which the control signal Sa is supplied via the insulator 10, and the connection point of the gate resistors 13 and 15 for on / off control of the IGBT 5a is connected to the gate of the IGBT 5a. Has been. 8 differs from the conventional circuit of FIG. 8 in that a Zener diode 21 is connected in parallel as a non-linear resistance means between the gate and emitter of the IGBT 5a via a switch element 22 such as a MOSFET, and a gate control circuit 30. Thus, the switch element 22 is controlled to be turned on / off.

  The gate control circuit 30 includes a reference power supply 31 for setting the first reference value Vref1, a comparator circuit 32 for comparing the first reference value Vref1 and the gate potential of the IGBT 5a, and an output and switch of the comparator circuit 32. An AND circuit 33 that performs an AND operation with the switching signal S2 that controls on / off of the element 14, and a flip-flop (hereinafter referred to as an SRFF circuit) 34 having a set terminal (S) and a reset terminal (R). Consists of The gate control circuit 30 operates to switch and hold the switch element 22 such as a MOSFET after the control signal Sa for the gate drive circuit 20 is switched to the off command.

FIG. 2 is a signal waveform diagram showing current and voltage signal waveforms of the respective parts when the IGBT is turned off.
As shown in FIG. 2, in the gate drive circuit 20, the detected value of the gate-emitter voltage Vge and the first reference value Vref1 are compared by the comparator circuit 32, and the voltage Vge is compared with the first reference value Vref1. In the following cases, when the control signal Sa becomes H level so as to turn on the switch element 14, the SRFF circuit 34 is set by the logical product operation result from the logical product circuit 33. The SRFF circuit 34 is inserted to latch the output (Q) from the AND circuit 33 and turns on the switch element 22. Here, when the control signal Sa to the IGBT 5a is subsequently switched to the ON command and the switching signal S2 falls to the L level, the SRFF circuit 34 is reset and the switch element 22 is turned off.

As shown in FIG. 2, the gate-emitter voltage Vge has a first reference value Vref1 that is an on-voltage value during the discharge period of the gate-collector capacitor Cgc (mode M2). Set slightly higher than V _{GE (on)} .

FIG. 3 is a characteristic diagram showing a schematic relationship between the collector current Ic and the voltage Vge in the IGBT 5a.
In the IGBT 5 a controlled by the gate drive circuit 20, when the switch element 14 is turned on, the gate-emitter voltage Vge is clamped to the Zener voltage (breakdown voltage) Vz of the Zener diode 21. Therefore, even if the IGBT 5b of the opposite arm is turned on before the collector-emitter voltage Vce reaches the DC voltage Ed, an extreme increase in the voltage Vge does not occur. As a result, the characteristics of the Zener diode 21 shown in FIG. Accordingly, the DC short-circuit current Ish can be suppressed.

Further, the Zener voltage Vz is suitably set in the vicinity of the ON voltage value V _{GE (on)} at the time of a low collector current.
In the gate drive circuit 20 of the semiconductor element according to the first embodiment described above, the Zener diode 21 connected in parallel between the gate and emitter of the IGBT 5a via the switch element 22 and the output of the off command to the gate drive circuit 20 A gate control circuit 30 that switches the switch element 22 to an on state and holds it later is provided. In the gate control circuit 30, after the off command is output to the gate drive circuit 20, the gate potential of the IGBT 5a is the first When the reference value Vref1 or less is reached, the switch element 22 is switched on and held so that the gate control circuit 30 can turn off the IGBT 5a with the Zener diode 21 connected between the gate and emitter of the IGBT 5a. . Therefore, when a power converter is configured using a plurality of voltage-driven power semiconductor elements with respect to the DC power supply, it is possible to reduce the loss at the time of turn-off and reduce the surge voltage and noise.

(Embodiment 2)
FIG. 4 is a circuit diagram showing a gate drive circuit of the semiconductor element according to the second embodiment.
In the gate drive circuit 20, as in the first embodiment, a Zener diode 21 is connected in parallel as a non-linear resistance means between the gate and emitter of the IGBT 5 a via a switch element 22. The element 22 is on / off controlled.

  The gate control circuit 40 includes a reference power supply 41 for setting the second reference value Vref2, a comparator circuit 42 for comparing the second reference value Vref2 and the collector-emitter potential of the IGBT 5a, and a comparator circuit 42. A logical product circuit 43 that performs a logical product (AND) operation between the output and the switching signal S2 that controls on / off of the switch element 14, and a flip-flop (hereinafter referred to as an SRFF circuit) having a set terminal (S) and a reset terminal (R). 44). Further, a current source circuit 23 and a diode 24 are provided to detect the voltage Vce between the collector and emitter of the IGBT 5a. The gate control circuit 40 operates so that the switch element 22 such as a MOSFET is switched on and held after the control signal Sa to the gate drive circuit 20 is switched to the off command.

  In the gate drive circuit 20 configured in this way, the detected value of the collector-emitter voltage Vce and the second reference value Vref2 are compared by the comparator circuit 42, and the voltage Vce is equal to or higher than the second reference value Vref2. When the control signal Sa becomes H level so as to turn on the switch element 14, the SRFF circuit 44 is set according to the AND operation result from the AND circuit 43 and turns on the switch element 22. be able to.

The SRFF circuit 44 in the gate control circuit 40 functions in the same manner as the SRFF circuit 34 of the first embodiment, but the voltage Vce in the transition process from the mode M2 to the mode M3 is almost as shown in FIG. Since it becomes equal to the ON voltage value V _{GE (on)} , it is desirable here to set the second reference value Vref2 so that Vref2 ≦ V _{GE (on)} .

  In the gate drive circuit 20 shown in FIG. 4, the voltage Vce is detected by the anode potential of the diode 24 connected between the current source circuit 23 and the collector of the IGBT 5a. However, even in other cases, the voltage Vce detection circuit can be configured by, for example, a resistance voltage dividing circuit.

(Embodiment 3)
FIG. 5 is a circuit diagram showing a gate drive circuit of a semiconductor element according to the third embodiment.
In addition to the gate control circuit 30 (Embodiment 1) or the gate control circuit 40 (Embodiment 2) for controlling on / off of the switch element 22, the gate drive circuit 20 flows before the IGBT 5a is turned off. A current value detection circuit 50 is provided for detecting the current value of the collector current Ic. However, in the gate drive circuit 20 of FIG. 5, description of the gate control circuits 30, 40, etc. is omitted.

  The current value detection circuit 50 includes a reference power source 51 for setting the third reference value Vref3, a comparator circuit 52 for comparing the third reference value Vref3 and the collector current value of the IGBT 5a, and an output of the comparator circuit 52. Is sampled by a switching signal S2 for controlling on / off of the switch element 14, and an AND circuit 54 for performing an AND operation on the output of the sample hold circuit 53 and the output of the gate control circuit. Composed. In this current value detection circuit 50, in the sample hold circuit 53, the timing for detecting the magnitude of the collector current is set at the time when the switching signal S2 rises. The AND circuit 54 is supplied with an input signal to the switch element 22 in the gate control circuit 30 (Embodiment 1) or the gate control circuit 40 (Embodiment 2). Therefore, in the gate drive circuit 20 shown in FIGS. 1 and 4, the AND circuit 54 is provided on the signal line 55 for turning on the switch element 22, and the detected value of the collector current Ic when the IGBT 5a is turned off is the first value. An algorithm can be configured to turn on the switch element 22 only when the reference value Vref3 is 3 or less.

  In this current value detection circuit 50, the current from the second emitter of the IGBT 5a is passed through the sense resistor 25, and the voltage value at both ends of the sense resistor 25 is detected, so that the comparator circuit 52 causes the collector current Ic to be less than the set current value. The gate control circuit 30 or the gate control circuit 40 can be operated only when the current is determined to be equal to or greater than the set current value and the current is small enough to cause the arm short circuit phenomenon. That is, if the gate control circuit 30 or the gate control circuit 40 is operated only at a small current that may cause the IGBT 5a to turn off and extend the upper and lower arms, the dead time Td is minimized. Even when the length is set, an excessive short-circuit current at the time of small current turn-off can be surely prevented.

  As a method of detecting the collector current when turning off the IGBT 5a, it is also possible to detect the voltage between both ends from a current transformer (CT) (not shown) or a resistor connected in series with the main IGBT 5a. .

(Embodiment 4)
FIG. 6 is a circuit diagram showing a gate drive circuit of a semiconductor element according to the fourth embodiment.
As in the first embodiment, the gate drive circuit 20 includes a Zener diode 21 connected in parallel as a non-linear resistance means between the gate and emitter of the IGBT 5a via a switch element 22 such as a MOSFET. The gate control circuit 60 controls the series circuit of the switch 21 and the switch element 22.

  Specifically, the gate control circuit 60 is composed of, for example, a delay circuit and a one-shot circuit, and after the control signal Sa becomes H level so as to turn on the switch element 14, a time substantially equal to the dead time Td in the delay circuit. When the delay period set to Tz elapses, the one-shot circuit operates to operate so as to switch and hold the switch element 22 for the predetermined on-period Ton.

  The ON period Ton for holding the switch element 22 in the ON state can be determined according to the characteristics of the Zener diode 21. For example, it is only necessary to set a time for reverse charging the feedback capacitance of the IGBT 5a with the current value Iz shown in FIG. 3 as the ON period Ton.

  According to each of the first to fourth embodiments described above, it is possible to reduce turn-off loss, surge voltage, and generated noise as compared with the conventional gate control circuit. Therefore, it is possible to construct an inexpensive power conversion system by reducing the rating of a voltage-driven power semiconductor element constituting the power conversion device, for example, IGBT, or by reducing the size of a radiator such as an inverter circuit. In addition, the control performance on the load side of the motor or the like is improved by shortening the dead time.

2 is a circuit diagram showing a gate drive circuit of the semiconductor element according to the first embodiment. FIG. It is a signal waveform diagram which shows the electric current of each part at the time of turning off IGBT, and a voltage signal waveform. It is a characteristic view which shows the rough relationship between the collector current Ic and voltage Vge in IGBT. FIG. 6 is a circuit diagram showing a gate drive circuit of a semiconductor element according to a second embodiment. FIG. 6 is a circuit diagram showing a gate drive circuit of a semiconductor element according to a third embodiment. FIG. 10 is a circuit diagram showing a gate drive circuit of a semiconductor element according to a fourth embodiment. It is a circuit diagram which shows the general structural example of the inverter using IGBT. It is a circuit diagram which shows the specific circuit structure of the conventional gate drive circuit. It is a circuit diagram which shows the equivalent circuit of IGBT which comprises a lower arm. It is a signal waveform diagram which shows the electric current of each part at the time of turning off IGBT, and a voltage signal waveform. It is a block diagram which shows the structure of the control circuit of a power converter device. It is a timing diagram which shows the control signals Sa and Sb output to the IGBT. It is a figure which shows the waveform of the voltage Vce between collector | corrector emitters in the mode M4 of IGBT. It is a signal waveform diagram which shows the electric current of each part at the time of turning off IGBT, and a voltage signal waveform. It is a circuit diagram which shows a part of inverter using IGBT. It is a circuit diagram which shows the equivalent circuit of IGBT.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply circuit 2 Inverter circuit 3 Load 4 Wiring inductance 5a-5f IGBT
6a to 6f Diode 7, 8 Gate drive circuit 9 Control circuit 10 Insulator 11 DC power supply (Vg)
12, 14 Switch element 13 Gate resistance (for turn-on)
15 Gate resistance (for turn-off)
DESCRIPTION OF SYMBOLS 20 Gate drive circuit 21 Zener diode 22 Switch element 23 Current source circuit 24 Diode 25 Sense resistance 30, 40 Gate control circuit 31 Reference power supply 32 Comparator circuit 33 AND circuit 34 SRFF circuit (flip-flop)
41 Reference power supply 42 Comparator circuit 43 AND circuit 44 SRFF circuit (flip-flop)
DESCRIPTION OF SYMBOLS 50 Current value detection circuit 51 Reference power supply 52 Comparator circuit 53 Sample hold circuit 54 AND circuit 60 Gate control circuit

Claims (9)

In a gate drive circuit of a semiconductor element for constituting a power conversion device using a plurality of voltage-driven power semiconductor elements for a DC power supply,
Gate driving means for controlling on / off of the power semiconductor element;
Non-linear resistance means connected in parallel between the gate and emitter of the power semiconductor element via a switch circuit;
The switch circuit is turned on and held after the output of the off command to the gate drive means, and after the off command is output to the gate drive means, the upper and lower arms of the power converter Control means for switching the switch circuit to an ON state when a time substantially equal to a dead time set for prevention of a short circuit has elapsed with respect to the control signal of the power semiconductor element ,
With
A gate drive circuit for a semiconductor element, wherein the power semiconductor element is turned off in a state where the resistance means is connected between the gate and the emitter of the power semiconductor element by the control means.   In a gate drive circuit of a semiconductor element for constituting a power conversion device using a plurality of voltage-driven power semiconductor elements for a DC power supply,
  Gate driving means for controlling on / off of the power semiconductor element;
  Non-linear resistance means connected in parallel between the gate and emitter of the power semiconductor element via a switch circuit;
  Control means for switching and holding the switch circuit in an on state with a delay from the output of an off command to the gate drive means;
  With
  The control means includes a current value detection circuit that detects a collector current value that was flowing before the power semiconductor element was turned off,
  In the current value detection circuit, after the off command is output to the gate driving means, when the collector current value is equal to or lower than a third reference value, the switch circuit is switched on and held, and
  A gate drive circuit for a semiconductor element, wherein the power semiconductor element is turned off in a state where the resistance means is connected between the gate and the emitter of the power semiconductor element by the control means. 3. The control device according to claim 1, wherein the control means switches and holds the switch circuit for an amount of time necessary for reverse charging the feedback capacitance of the power semiconductor element . A gate drive circuit for a semiconductor device according to any one of the above. The resistance means is a Zener diode having a predetermined breakdown voltage,
The breakdown voltage is set to be substantially equal to a voltage between a gate and an emitter during discharge of a charge charged in the positive direction in the feedback capacitor when the power semiconductor element is turned off. 4. A gate drive circuit for a semiconductor device according to 3.   When the gate potential of the power semiconductor element becomes equal to or lower than a first reference value after an off command is output to the gate driving means, the control means switches the switch circuit to an on state and holds it. 5. The gate drive circuit for a semiconductor device according to claim 4, wherein the gate drive circuit is configured as described above.   6. The gate drive circuit for a semiconductor device according to claim 5, wherein the first reference value is set higher than the breakdown voltage of the Zener diode.   The control means switches the switch circuit to an ON state when a collector-emitter potential of the power semiconductor element becomes equal to or higher than a second reference value after an OFF command is output to the gate driving means. 5. The gate drive circuit for a semiconductor device according to claim 4, wherein   8. The gate drive circuit for a semiconductor device according to claim 7, wherein the second reference value is set lower than a breakdown voltage of the Zener diode.   The gate driving means includes a driving DC power supply, a first series circuit including a switch element and a resistance element for turn-on connecting between a positive electrode side of the DC power supply and the power semiconductor element, and the DC power supply. 3. The device according to claim 1, further comprising: a second series circuit including a switch element for turning off and a resistance element for connecting between the negative electrode side of the power semiconductor element and the power semiconductor element. A gate drive circuit for the semiconductor device according to 1.

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