JP4326277B2 - Gate drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gate drive circuit for driving a power switching element.
[0002]
[Prior art]
Power converters that apply power switching elements are steadily expanding their application ranges as the switching elements increase in capacity and speed. In particular, MOS gate type switching elements such as IGBTs and MOSFETs have recently been expanded in application fields.
[0003]
IGBTs and MOSFETs are non-latching switching elements that do not continue their on and off states, and one of the advantages is that they have higher controllability by gate driving than latching switching elements such as thyristors. In particular, active gate drive technology that has been put into practical use in recent years can suppress surge voltage and surge current by gate control even during turn-on and turn-off switching transients, and can freely adjust the current and voltage gradient during switching transients. Can be controlled.
[0004]
For example, surge suppression at the time of current interruption in a gate drive circuit to which an active gate drive technology is applied is achieved as follows. That is, when the switching operation of the switching element is performed by switching the gate voltage from the positive voltage to the negative voltage, the voltage at both ends of the switching element rises rapidly, but when this voltage exceeds a predetermined value, the gate voltage is raised. If the control is performed, the switching operation of the switching element is delayed, and the voltage surge at both ends of the switching element can be suppressed.
[0005]
The above is a mode in which the switching element itself is cut off. However, depending on the load power factor, the current cut-off of the main circuit is a mode that is performed by the current cut-off of a flywheel diode connected in antiparallel to the switching element. In this case, the gate potential is already a sufficiently low negative voltage, and the above-described conventional active gate driving as described above is not performed because the transient control is not performed while the gate potential changes from positive to negative as described above. Technology cannot suppress voltage surges.
[0006]
On the other hand, in order to suppress the voltage surge, a technique has been devised in which the inductance of the main circuit is used to detect the voltage at both ends thereof to temporarily increase the gate potential (see, for example, Patent Document 1). .
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 7-99429 (page 7-8, FIG. 1)
[0008]
[Problems to be solved by the invention]
However, in order to suppress the surge voltage by the method disclosed in Patent Document 1, a certain amount of main circuit inductance is required. In addition to the problem that the surge voltage is increased by itself, there is a problem that the loss is increased because the entire interruption time becomes longer.
[0009]
The present invention has been made in view of the above problems, and an object thereof is to provide a simple and low-cost gate driving circuit for suppressing a surge voltage generated by turn-off of a fly-hole diode.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a gate drive circuit according to the present invention is a gate drive circuit that drives a control electrode of a power switching element. Current driving means for injecting current, and clamping means for preventing a voltage applied to the gate electrode from becoming a predetermined value or less during a turn-off transient period of the power switching element are provided.
[0011]
According to the present invention, it is possible to suppress the surge voltage generated by the turn-off of the fly-hole diode only by adding a relatively simple control means such as a clamp means.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of a gate driving circuit according to the present invention will be described below with reference to FIGS. FIG. 1 is a configuration diagram of a gate driving circuit of the present invention.
[0013]
The gate drive power supplies 1 a and 1 b are respectively used as a positive power supply and a negative power supply, and the gate terminal of the switching element 9 is driven from the output of the voltage amplifier 2 via the resistor 3. A gate control signal for the switching element 9 is input to the voltage amplifier 2. A gate injection current Ig is injected from the control current source 8 into the gate terminal of the switching element 9. Similar to the voltage amplifier 2, the control current source 8 is controlled by a voltage amplifier 7 using the gate drive power supplies 1a and 1b as positive and negative power supplies, respectively. The voltage amplifier 7 uses a voltage obtained by dividing the voltage applied to the switching element 9 by the voltage dividing resistors 4a and 4b as a non-inverting input. The inverting input of the voltage amplifier 7 is a voltage obtained by adding a value obtained by dividing the potential difference between the output potential of the voltage amplifier 7 and the reference voltage source 5 by the feedback resistors 6 a and 6 b to the voltage of the reference voltage source 5. A flywheel diode 10 is connected to the switching element 9 in antiparallel.
[0014]
The clamp means 11 is connected between the gate and emitter of the switching element 9, and this control input terminal is connected to the output terminal of the voltage amplifier 2. The clamp means 11 detects the start of the turn-off transient period at the timing when the voltage at the control input terminal drops, and clamps the gate-emitter voltage Vge to a certain voltage for a certain period.
[0015]
Hereinafter, the turn-off operation of the main circuit in the configuration diagram of FIG. 1 will be described.
[0016]
First, a normal turn-off operation in which the switching element 9 is conductive and the flywheel diode 10 is not conductive will be described. In FIG. 1, the voltage of the gate control signal to the voltage amplifier 2 is switched from positive to negative, and accordingly, the output voltage of the voltage amplifier 2 changes from a positive voltage determined by the gate power supply 1a to a negative voltage determined by the gate power supply 1b. Start the migration. As a result, the gate voltage of the switching element 9 begins to drop, and when the gate voltage falls below a certain threshold voltage determined by the static characteristics of the switching element 9, the current flowing through the switching element 9 begins to be interrupted, and at the same time 9 collector-emitter voltage Vce starts to rise rapidly. Since the collector-emitter voltage Vce is divided by the voltage dividing resistors 4 a and 4 b and applied to the non-inverting input terminal of the voltage amplifier 7, the collector-emitter voltage Vce is determined by the feedback resistors 6 a and 6 b and the reference voltage source 5. When a certain value is exceeded, the output voltage of the voltage amplifier 7 rises rapidly, whereby the output current of the control current source 8 also rises. Since the output of the control current source 8 is connected to the gate terminal of the switching element 9, this becomes the gate injection current Ig, and the gate terminal voltage of the switching element 9 temporarily rises due to this gate injection current Ig, and switching The shutoff operation of the element 9 is delayed, and the collector-emitter voltage Vce does not rise any further.
[0017]
The above operation is a surge voltage suppressing operation in the case where the switching element 9 is turned off in a state where the flywheel diode 10 is not conductive, and this operation is performed without providing the clamp means 11.
[0018]
Next, the surge suppression operation during turn-off when the flywheel diode 10 is conducting in FIG. 1 will be described with reference to the operation waveform diagram shown in FIG. FIG. 2 shows the waveform of each part when the flywheel diode 10 is turned off.
[0019]
The gate-emitter voltage Vge decreases as the turn-off operation starts at time t1. In the case of the switching operation of the switching element 9 described above, the switching operation of the switching element 9 starts at this time t1, and the collector-emitter voltage Vce starts to rise, but when the flywheel diode 10 is conductive, the switching operation Since the main circuit current continues to flow even after the element 9 is shut off, the collector-emitter voltage Vce does not increase at time t1.
[0020]
Thereafter, the gate-emitter voltage Vge reaches the predetermined voltage Vcl at time t2, but does not drop below the predetermined voltage Vcl due to the action of the clamping means 11. When the cutoff operation of the flywheel diode 10 starts at time t3 and the collector-emitter voltage Vce rises and exceeds a certain value, the gate injection current Ig rises at time t4. As the gate injection current Ig rises, the gate-emitter voltage Vge immediately rises to reach the threshold voltage of the switching element 9, and the switching element 9 becomes conductive. Due to the conduction of the switching element 9, the rise of the collector-emitter voltage Vce is suppressed, and the peak surge voltage can be suppressed.
[0021]
Therefore, when the clamping means 11 of FIG. 1 is not provided, the gate-emitter voltage Vge remains negative and the flywheel diode 10 is cut off. The waveform at that time is shown by a broken line in FIG. The surge voltage has a large peak such as “Vce when there is no clamping means”.
[0022]
The predetermined voltage Vcl set by the clamping means 11 is preferably set to a value slightly lower than the threshold voltage of the switching element 9.
[0023]
2 is a turn-on timing of a switching element (not shown) that forms a pair with the switching element 9, and this is from the start of turn-off of the switching element 9. This is the time when the dead time of the switching element 9 has elapsed. Therefore, for a certain period during which the clamping means 11 performs the clamping operation, for example, a value obtained by adding a slight interruption time of the flywheel diode 10 to the dead time may be set by a timer or the like.
[0024]
As described above, according to the gate drive circuit of the present invention, it is possible to perform a surge suppression operation during turn-off even when the flywheel diode 10 is conductive.
[0025]
(Second Embodiment)
FIG. 3 is a configuration diagram of a gate control circuit according to the second embodiment of the present invention. Regarding the respective parts of the second embodiment, the same parts as those of the gate control circuit according to the first embodiment of FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. The second embodiment is different from the first embodiment in that the clamp means 11 is connected between the gate and emitter of the switching element 9 in FIG. 1, whereas the clamp means in FIG. 11 is connected between the output terminal of the voltage amplifier 2 and the emitter terminal of the switching element 9.
[0026]
Thus, even if the output voltage of the voltage amplifier 2 is clamped without directly clamping the gate-emitter voltage Vge, the same object can be achieved. That is, if the output voltage of the voltage amplifier 2 is clamped so as not to be lower than a predetermined value during the turn-off transition period, the gate-emitter voltage Vge of the switching element 9 is clamped so as not to be lower than the predetermined value, and the switching element is effectively Thus, the surge voltage of the collector-emitter voltage Vce of 9 can be suppressed.
[0027]
(Third embodiment)
FIG. 4 is a configuration diagram of a gate control circuit according to the third embodiment of the present invention. Regarding the respective parts of the third embodiment, the same parts as those of the gate control circuit according to the first embodiment of FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. The third embodiment is different from the first embodiment in that the specific internal configuration of the clamping means 11 is shown in FIG. That is, the inside of the clamp means 11 is controlled by the timing detector 12, the timing detector 12, the switch element 13 whose emitter is connected to the positive electrode of the gate drive power source 1 a, and the collector terminal of the switch element 13 and the switching element 9. The zener diode 14 is connected between the gate terminals.
[0028]
When the timing detector 12 detects that the output of the voltage amplifier 2 has started to drop, the output voltage of the timing detector 12 drops for a certain period of time as described above, and the switch element 13 is turned on. When the switch element 13 is turned on, the gate voltage of the switching element 9 does not drop below a certain voltage determined by the voltage of the gate drive power supply 1 a and the characteristics of the Zener diode 14. When the turn-off transient period ends, the output voltage of the timing detector 12 rises again, and the switch element 13 is turned off, the gate voltage of the switching element 9 resumes the fall to the voltage determined by the gate drive power supply 1b again.
[0029]
In this way, it is possible to suppress a surge voltage generated by turn-off of the flyhole diode 10 with a relatively simple circuit that is a combination of the switch element 13 and the Zener diode 14.
[0030]
(Fourth embodiment)
FIG. 5 is a block diagram of a gate control circuit according to the fourth embodiment of the present invention. Regarding the respective parts of the fourth embodiment, the same parts as those of the gate control circuit according to the third embodiment of FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted. The fourth embodiment differs from the third embodiment in that a voltage dividing resistor 15a and a voltage dividing resistor 15b are connected in series between the positive and negative electrodes of the gate drive power supply 1a instead of the Zener diode 14 in the clamp means 11. The capacitor 16 is inserted in parallel with the circuit and the voltage dividing resistor 15b. In FIG. 5, the voltage of the gate drive power source 1 a is divided by the voltage dividing resistors 15 a and 15 b and is given to the capacitor 16. Since the switching element 13 is turned on by the output of the timing detector 12 during the turn-off transition period, the gate-emitter voltage Vge of the switching element 9 does not become lower than the voltage of the capacitor 16.
[0031]
Here, the reason for using the capacitor 16 as well as the voltage dividing resistors 15a and 15b is to reduce the impedance in the turn-off transient period. Even if the values of the voltage dividing resistors 15a and 15b are reduced, the impedance is reduced, but if so, the power consumed by the voltage dividing resistors 15a and 15b is also increased. By using the capacitor 16, it is possible to reduce the impedance while suppressing power consumption.
[0032]
As described above, it is possible to suppress the surge voltage generated by the turn-off of the fly-hole diode 10 even if the gate drive power supply 1a is clamped with the divided voltage regardless of the Zener diode 14.
[0033]
(Fifth embodiment)
FIG. 6 is a configuration diagram of a gate control circuit according to the fifth embodiment of the present invention. Regarding the respective parts of the fifth embodiment, the same parts as those of the gate control circuit according to the third embodiment of FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted. The fifth embodiment is different from the third embodiment in that the collector terminal of the switch element 13 in the clamping means 11 is connected to the gate terminal of the switching element 9, and the Zener diode 14 is different from the third embodiment. Instead, the voltage source 17 is inserted between the emitter terminal of the switch element 13 and the negative electrode of the gate drive power supply 1b. Here, the negative electrode of the voltage source 17 may be connected to the zero point, that is, the positive electrode of the gate drive power supply 1b. In this case, the voltage of the voltage source 17 is the clamp voltage Vcl itself.
[0034]
Thus, even if the voltage source 17 is used for clamping, the surge voltage generated by the turn-off of the fly-hole diode 10 can be suppressed.
[0035]
(Sixth embodiment)
FIG. 7 is a block diagram of a gate control circuit according to the sixth embodiment of the present invention. Regarding the respective parts of the sixth embodiment, the same parts as those of the gate control circuit according to the third embodiment of FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted. The fourth embodiment differs from the third embodiment in that a series circuit including a variable voltage source 18 and a diode 19 is inserted in place of the series circuit including the switch element 13 and the Zener diode 14 in the clamping unit 11. Is a point. In FIG. 7, the output of the timing detector 12 is input to the control input terminal of the variable voltage source 18, and the voltage generated by the variable voltage source 18 is input to the gate terminal of the switching element 9 via the diode 19. When the timing detector 12 detects the turn-off transient period, the output voltage of the variable voltage source 18 rises and is set to a desired clamp voltage. For this reason, when the gate-emitter voltage Vge of the switching element 9 falls below the output voltage of the variable voltage source 18, the diode 19 becomes conductive and clamps the gate-emitter voltage Vge. After the turn-off transient period, the output voltage of the variable voltage source 18 becomes equal to or lower than the voltage of the gate drive power supply 1b, so that the diode 19 does not conduct and the clamping means 11 does not affect the switching element 9.
[0036]
Here, the voltage value of the variable voltage source 18 may be varied continuously or stepwise. The important point is that the voltage value of the variable voltage source 18 is set to a predetermined voltage during the turn-off transition period, and is sufficiently low during other periods.
[0037]
As described above, the surge voltage generated by the turn-off of the fly-hole diode 10 can be suppressed also by the method using the variable voltage source 18.
[0038]
(Seventh embodiment)
FIG. 8 is a configuration diagram of a gate control circuit according to the seventh embodiment of the present invention. About each part of this 7th Embodiment, the same part as each part of the gate control circuit which concerns on 6th Embodiment of FIG. 7 is shown with the same code | symbol, and the description is abbreviate | omitted. The seventh embodiment is different from the sixth embodiment in that the diode 19 of the clamping unit 11 is omitted and the connection position between the timing detector 12 and the variable voltage source 18 is changed. That is, the timing detector 12 detects the input voltage of the voltage amplifier 2, and the variable voltage source 18 is connected so as to be the power supply voltage on the negative side of the voltage amplifier 2.
[0039]
Since the output voltage of the voltage amplifier 2 never falls below the negative power supply voltage, the lower limit value of the output voltage of the voltage amplifier 2 is equal to the output voltage of the variable voltage source 18. Therefore, when the timing detector 12 detects the turn-off transient period, the output voltage of the variable voltage source 18 is increased and the lower limit value of the output voltage value of the voltage amplifier 2 is raised. In this way, the gate-emitter voltage Vge of the switching element 9 can be maintained above a certain value. When the output voltage value of the variable voltage source 18 is returned to a steady value when the turn-off transient period ends, the voltage amplifier 2 can output the normal output voltage.
[0040]
As described above, the surge voltage generated by the turn-off of the fly-hole diode 10 can also be suppressed by making the control power source on the negative side of the voltage amplifier 2 variable.
[0041]
(Eighth embodiment)
FIG. 9 is a configuration diagram of a gate control circuit according to the eighth embodiment of the present invention. Regarding the respective parts of the eighth embodiment, the same parts as those of the gate control circuit according to the seventh embodiment of FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted. The eighth embodiment differs from the seventh embodiment in that the connection point of the detection input of the timing detector 12 is changed. That is, in the seventh embodiment shown in FIG. 8, the input terminal of the timing detector 12 is connected to the input terminal of the voltage amplifier 2, whereas in the eighth embodiment, the timing detector The 12 input terminals are connected to the non-inverting input terminal of the voltage amplifier 7. That is, the timing detector 12 receives, as a control input, a value obtained by dividing the collector-emitter voltage Vce applied between the main electrodes of the switching element 9 by the voltage dividing resistors 4a and 4b. Thus, until the collector-emitter voltage Vce of the switching element 9 exceeds a certain value, the output voltage of the variable voltage source 18 becomes equal to the predetermined voltage Vcl that is the clamp level of the gate-emitter voltage Vge, and thereafter Performs the operation of returning to the original output voltage.
[0042]
According to the eighth embodiment, the clamp means 11 always operates at the timing when the switching element 9 is turned on. However, the gate-emitter voltage Vge of the switching element 9 is sufficiently set. Since it is necessary to perform negative bias only during the period when the switching element 9 is off, there is no problem in operation.
[0043]
Even if the end point of the turn-off transient period is detected by detecting the collector-emitter voltage Vce of the switching element 9 as described above, the surge voltage generated by turning off the fly-hole diode 10 is suppressed. The object of the invention can be achieved.
[0044]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a simple and low-cost gate driving circuit for suppressing a surge voltage generated by turn-off of a fly-hole diode.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a gate drive circuit according to a first embodiment of the present invention.
FIG. 2 is a waveform of each part when the flywheel diode is turned off.
FIG. 3 is a configuration diagram of a gate control circuit according to a second embodiment of the present invention.
FIG. 4 is a configuration diagram of a gate control circuit according to a third embodiment of the present invention.
FIG. 5 is a configuration diagram of a gate control circuit according to a fourth embodiment of the present invention.
FIG. 6 is a configuration diagram of a gate control circuit according to a fifth embodiment of the present invention.
FIG. 7 is a configuration diagram of a gate control circuit according to a sixth embodiment of the present invention.
FIG. 8 is a configuration diagram of a gate control circuit according to a seventh embodiment of the present invention.
FIG. 9 is a configuration diagram of a gate control circuit according to an eighth embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Gate drive power supply 2 Voltage amplifier 3 Gate resistance 4a, 4b Voltage dividing resistor 5 Reference voltage source 6a, 6b Feedback resistor 7 Voltage amplifier 8 Control current source 9 Switching element 10 Flywheel diode 11 Clamp means 12 Timing detector 13 Switch element 14 Zener diodes 15a and 15b Resistor 16 Capacitor 17 Voltage source 18 Variable voltage source 19 Diode

Claims (10)

In the gate drive circuit that drives the control electrode of the power switching element,
Current driving means for injecting a current into the gate electrode in accordance with a voltage applied between the main electrodes of the power switching element;
A gate driving circuit comprising: clamping means for preventing a voltage applied to the gate electrode from becoming a predetermined value or less during a turn-off transient period of the power switching element. In the gate drive circuit that drives the control electrode of the power switching element,
Current driving means for injecting a current into the gate electrode in accordance with a voltage applied between the main electrodes of the power switching element;
In response to an on / off command of the power switching element, voltage driving means for applying a voltage to the gate electrode through a gate resistor,
The gate driving circuit according to claim 1, wherein the voltage driving means includes clamping means for preventing an output voltage value from becoming a predetermined value or less during a turn-off transition period of the power switching element. 3. The gate drive circuit according to claim 1, wherein the clamp means is a voltage limiting means in which a Zener diode and a switch element are connected in series. 3. The gate drive circuit according to claim 1, wherein the clamp means is a voltage limiting means in which a switch element and a capacitor are connected in series. 3. The gate drive circuit according to claim 1, wherein the clamp means is a voltage limiting means in which a switch element and a voltage source are connected in series. 3. The gate drive circuit according to claim 1, wherein the clamp means is a voltage limiting means in which a variable voltage source and a diode are connected in series. 3. The gate driving circuit according to claim 2, wherein a voltage value of a power source used for the voltage driving means can be changed continuously or stepwise. 3. The gate drive circuit according to claim 1, wherein a turn-off transient period for operating the clamp means is substantially equal to a dead time of the power switching element. The turn-off transient period for operating the clamp means is a time until the voltage applied between the main electrodes of the power switching element exceeds a predetermined value. Gate drive circuit. 3. The gate drive circuit according to claim 1, wherein a voltage level clamped by the clamp means is lower than a threshold voltage of the power switching element.

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