JP5298557B2 - Voltage-driven semiconductor device gate drive device - Google Patents

Voltage-driven semiconductor device gate drive device Download PDF

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JP5298557B2
JP5298557B2 JP2008032966A JP2008032966A JP5298557B2 JP 5298557 B2 JP5298557 B2 JP 5298557B2 JP 2008032966 A JP2008032966 A JP 2008032966A JP 2008032966 A JP2008032966 A JP 2008032966A JP 5298557 B2 JP5298557 B2 JP 5298557B2
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JP2009195017A (en
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邦夫 松原
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Fuji Electric Co Ltd
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<P>PROBLEM TO BE SOLVED: To solve a problem of large loss at a normal current and large loss of an apparatus and hence upsizing of the apparatus in a system which increases an on-gate resistance value of an opposing arm to suppress a surge voltage and voltage fluctuations when FWD is in a small and reverse-recovery current state. <P>SOLUTION: A gate drive includes a voltage detection circuit 12 for detecting a voltage generated at an internal inductance 5 connected to IGBT3 during a turn-off and a comparison circuit 13 for comparing a detection time from an input of an off-gate signal to voltage detection by a voltage detection circuit 12 with a predetermined setting time. A gate driving resistor 8 or 11 for turn-on is switched with switch devices 6, 10 according to a comparative result. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、電力変換装置に適用される電圧駆動型半導体素子のゲート駆動装置に関し、特に還流ダイオードが逆回復する時に発生するサージ電圧や振動電圧を抑制するためのゲート駆動技術に関する。   The present invention relates to a gate drive device for a voltage-driven semiconductor element applied to a power conversion device, and more particularly to a gate drive technique for suppressing a surge voltage and an oscillating voltage generated when a freewheeling diode reversely recovers.

図7に、電圧駆動型半導体素子としてIGBTを使用した周知の電圧形インバータの回路構成図を示す。21が三相交流電源、22が整流回路、23が平滑用コンデンサ、24〜29がダイオードが逆並列接続されたIGBT、30がモータ負荷である。   FIG. 7 shows a circuit configuration diagram of a known voltage source inverter that uses an IGBT as a voltage-driven semiconductor element. 21 is a three-phase AC power source, 22 is a rectifier circuit, 23 is a smoothing capacitor, 24 to 29 are IGBTs with diodes connected in antiparallel, and 30 is a motor load.

図8は、図7に示した電圧形インバータの1相分の等価回路図である。図8において、36が平滑用コンデンサ、37が回路の配線インダクタンス、38がL負荷、3、33がIGBT、4、34がフリーホイルダイオード(以下、FWD)、5、35がIGBTモジュールの内部インダクタンス、32が上アームのIGBTモジュール、2が下アームのIGBTモジュール、31が上アームのIGBTモジュール32に接続するゲート駆動装置(GDU1)、1が下アームのIGBTモジュール2に接続するゲート駆動装置(GDU2)である。   FIG. 8 is an equivalent circuit diagram for one phase of the voltage source inverter shown in FIG. In FIG. 8, 36 is a smoothing capacitor, 37 is a wiring inductance of the circuit, 38 is an L load, 3 and 33 are IGBTs, 4 and 34 are free wheel diodes (hereinafter referred to as FWD), and 5 and 35 are internal inductances of the IGBT module. 32 is an upper arm IGBT module, 2 is a lower arm IGBT module, 31 is a gate drive device (GDU1) connected to the upper arm IGBT module 32, and 1 is a gate drive device (1) connected to the lower arm IGBT module 2 GDU2).

図9に、ゲート駆動装置1の主要部の回路図を示す。図9において、6、7がIGBTをターンオン及びターンオフさせるためのスイッチ素子、8がゲートオン抵抗、9がゲートオフ抵抗、15がオン信号及びオフ信号を出力するインターフェイス回路である。尚、この種のゲート駆動装置としては、特許文献1に開示されているとおりである。   FIG. 9 shows a circuit diagram of the main part of the gate driving device 1. In FIG. 9, 6 and 7 are switch elements for turning on and off the IGBT, 8 is a gate-on resistance, 9 is a gate-off resistance, and 15 is an interface circuit that outputs an on signal and an off signal. This type of gate driving device is as disclosed in Patent Document 1.

図10及び図11に、図9のIGBT3がスイッチングした時のIGBT3のコレクタ−エミッタ間電圧VCE及びコレクタ電流Icの動作波形、FWD34のアノード−カソード間電圧VAK及びFWDの電流(順電流IFと逆回復電流)の動作波形を示す。ここで、図10は通常電流時の動作波形、図11は小電流時(一般的に素子定格電流の約1/10以下)の動作波形である。   10 and 11 show the operation waveforms of the collector-emitter voltage VCE and the collector current Ic of the IGBT 3 when the IGBT 3 of FIG. 9 is switched, the anode-cathode voltages VAK and FWD of the FWD 34 (the reverse of the forward current IF). The operation waveform of the recovery current is shown. Here, FIG. 10 shows an operation waveform at a normal current, and FIG. 11 shows an operation waveform at a small current (generally about 1/10 or less of the element rated current).

図8において、IGBT3がオン状態の時には、平滑用コンデンサ36→配線インダクタンス37→L負荷38→IGBT3→内部インダクタンス5→平滑用コンデンサ36の経路で電流が流れる(オンモード)。IGBT3がターンオフすると、IGBT3のコレクタ−エミッタ間電圧VCEが上昇する。VCEが直流電圧Edに達すると、FWD34がオンすることによって、負荷電流ILはFWD34に転流して、L負荷38→FWD34→L負荷38の経路で電流が流れる(フリーホイリングモード)。この状態から、IGBT3がターンオンすると、平滑用コンデンサ36→回路配線インダクタンス37→FWD34→IGBT3→平滑用コンデンサ36の経路でFWD34に逆回復電流が流れ、逆回復する。FWD34の逆回復動作が終了すると、再びIGBT3がオン状態(オンモード)となる。ここで、FWD34の逆回復時にサージ電圧Vp1が発生する(図10参照)。   In FIG. 8, when the IGBT 3 is in the ON state, a current flows through the path of the smoothing capacitor 36 → the wiring inductance 37 → the L load 38 → the IGBT 3 → the internal inductance 5 → the smoothing capacitor 36 (on mode). When the IGBT 3 is turned off, the collector-emitter voltage VCE of the IGBT 3 increases. When the VCE reaches the DC voltage Ed, the FWD 34 is turned on, whereby the load current IL is commutated to the FWD 34, and a current flows through the path of L load 38 → FWD 34 → L load 38 (free wheeling mode). When the IGBT 3 is turned on from this state, a reverse recovery current flows through the FWD 34 through the path of the smoothing capacitor 36 → the circuit wiring inductance 37 → FWD 34 → IGBT 3 → the smoothing capacitor 36, and reverse recovery is performed. When the reverse recovery operation of the FWD 34 is completed, the IGBT 3 is turned on again (on mode). Here, a surge voltage Vp1 is generated during reverse recovery of the FWD 34 (see FIG. 10).

図8のフリーホイリングモード時において、電流が小電流の場合にFWD34が逆回復すると、図11に示すように高いサージ電圧Vp2と高周波の振動現象が発生し、最悪の場合、発生ノイズの増大と共に、素子破壊に至る可能性がある。   In the freewheeling mode of FIG. 8, when the FWD 34 reversely recovers when the current is small, a high surge voltage Vp2 and a high-frequency vibration phenomenon occur as shown in FIG. 11, and in the worst case, the generated noise increases. At the same time, there is a possibility of element destruction.

このFWDの低電流逆回復時のサージ電圧と振動現象による素子破壊を防ぐために、図8の従来のゲート駆動装置において、IGBT3のゲートオン抵抗8を大きくすることで、サージ電圧と振動現象を抑制することができる。このゲート抵抗値を大きくすることにより、IGBTのコレクタ電流の立ち上がりを緩和する方法は、特許文献2に開示されている。
特開2002−165435号公報 特開平10−32976号公報
In order to prevent the element breakdown due to the surge voltage and the vibration phenomenon during the low current reverse recovery of the FWD, the surge voltage and the vibration phenomenon are suppressed by increasing the gate-on resistance 8 of the IGBT 3 in the conventional gate drive device of FIG. be able to. A method of relaxing the rise of the collector current of the IGBT by increasing the gate resistance value is disclosed in Patent Document 2.
JP 2002-165435 A Japanese Patent Laid-Open No. 10-32976

上述のように、小電流時のFWD逆回復時のサージ電圧と振動現象を抑制するためにゲートオン抵抗8を大きくすると、通常電流時のターンオン損失が増加してしまうという問題がある。   As described above, if the gate-on resistance 8 is increased in order to suppress the surge voltage and the vibration phenomenon at the time of reverse recovery of the FWD at a small current, there is a problem that the turn-on loss at the normal current increases.

上述の課題を解決するために、第1の発明においては、電力変換装置に用いる電圧駆動型半導体素子を駆動するゲート駆動装置において、ターンオフ時に電圧駆動型半導体素子に接続されている内部インダクタンスに発生する電圧を検出するインダクタンス電圧検出手段と、オフゲート信号が入力されてから前記インダクタンス電圧検出手段が電圧検出するまでの検出時間と予め定められた設定時間とを比較する比較手段と、前記比較結果に応じてターンオン用のゲート駆動条件を切替える切替手段と、を備え、前記オフゲート信号が入力されてから前記インダクタンス電圧検出手段が電圧検出するまでの検出時間が前記予め定められた設定時間より長い場合に、前記切替手段は次のターンオン用ゲート駆動条件としてゲートオン抵抗を通常のゲートオン抵抗より高抵抗のゲートオン抵抗に切替えるIn order to solve the above-mentioned problem, in the first invention, in a gate driving device for driving a voltage-driven semiconductor element used in a power converter, it is generated in an internal inductance connected to the voltage-driven semiconductor element at turn-off. An inductance voltage detecting means for detecting a voltage to be detected, a comparing means for comparing a detection time from when an off-gate signal is input until the inductance voltage detecting means detects a voltage with a predetermined set time, and Switching means for switching the gate drive condition for turn-on in response, and when the detection time from when the off-gate signal is input until the inductance voltage detection means detects the voltage is longer than the predetermined set time The switching means normally uses a gate-on resistance as the next turn-on gate drive condition. It switched to the gate-on resistance of the high resistance than the gate-on resistance.

第2の発明においては、電力変換装置に用いる電圧駆動型半導体素子を駆動するゲート駆動装置において、ターンオフ時に電圧駆動型半導体素子に接続されている内部インダクタンスに発生する電圧を検出するインダクタンス電圧検出手段と、オフゲート信号が入力されてから前記インダクタンス電圧検出手段が電圧検出するまでの検出時間と予め定められた設定時間とを比較する比較手段と、前記比較結果に応じてターンオン用のゲート駆動条件を切替える切替手段と、を備え、前記オフゲート信号が入力されてから前記インダクタンス電圧検出手段が電圧検出するまでの検出時間が前記予め定められた設定時間より長い場合に、前記切替手段はゲート駆動電源電圧を次のターンオン用ゲート駆動条件として通常のゲート駆動電源電圧より低い電圧のゲート駆動電源電圧に切替えるIn the second invention, in the gate driving device for driving the voltage driven semiconductor element used in the power converter , the inductance voltage detecting means for detecting the voltage generated in the internal inductance connected to the voltage driven semiconductor element at the turn-off time Comparing means for comparing a detection time from when the off-gate signal is input until the inductance voltage detection means detects a voltage with a predetermined set time, and a gate drive condition for turn-on according to the comparison result. Switching means for switching, and when the detection time from when the off-gate signal is input to when the inductance voltage detection means detects a voltage is longer than the predetermined set time, the switching means is a gate drive power supply voltage. From the normal gate drive power supply voltage as the gate drive condition for the next turn-on It has switched to the gate drive power supply voltage of the voltage.

本発明によれば、このゲート駆動装置をインバータ等の電力変換装置に適用すれば、自アーム素子のターンオフ時にコレクタ電流が流れ始める時間を検出することだけで、ターンオン損失を増加させずに、FWD小電流逆回復時のサージ電圧と振動現象を抑制でき、発生ノイズの低減、素子破壊の防止が可能となる。また、各アームにIGBTが複数個直列接続された電力変換装置に適用した場合においても同様な効果がある。   According to the present invention, when this gate driving device is applied to a power conversion device such as an inverter, it is possible to detect FWD without increasing the turn-on loss only by detecting the time when the collector current starts flowing when the self-arm element is turned off. Surge voltage and vibration phenomenon during small current reverse recovery can be suppressed, noise generated can be reduced, and element breakdown can be prevented. The same effect can be obtained when applied to a power converter in which a plurality of IGBTs are connected in series to each arm.

本発明の要点は、ターンオフ時に電圧駆動型半導体素子に接続されている内部インダクタンスに発生する電圧を検出するインダクタンス電圧検出手段と、オフゲート信号が入力されてから前記インダクタンス電圧検出手段が電圧検出するまでの検出時間と予め定められた設定時間とを比較する比較手段と、を備え、前記比較結果に応じてターンオン用のゲート駆動条件を切替えることである。   The main points of the present invention are an inductance voltage detecting means for detecting a voltage generated in an internal inductance connected to the voltage-driven semiconductor element at the time of turn-off, and from when an off-gate signal is inputted until the inductance voltage detecting means detects the voltage. Comparing means for comparing the detected time with a predetermined set time, and switching the gate drive condition for turn-on according to the comparison result.

図1に本発明の第1の実施例を示す。図1の実施例において、1がゲート駆動装置、2がIGBTモジュール、3がIGBT、4がFWD、5がIGBTモジュール内部のインダクタンスである。図1より、IGBTモジュール2は、IGBT3、FWD4、内部インダクタンス5から構成され、IGBTモジュール2のゲート端子G、主エミッタ端子E1、補助エミッタ端子E2にゲート駆動装置1が接続される。   FIG. 1 shows a first embodiment of the present invention. In the embodiment of FIG. 1, 1 is a gate driving device, 2 is an IGBT module, 3 is an IGBT, 4 is an FWD, and 5 is an inductance inside the IGBT module. As shown in FIG. 1, the IGBT module 2 includes IGBTs 3, FWD 4, and internal inductance 5, and the gate driving device 1 is connected to the gate terminal G, main emitter terminal E 1, and auxiliary emitter terminal E 2 of the IGBT module 2.

図2に、本発明のゲート駆動装置の回路構成例を示す。図9の従来例と同様な機能を有するものには、同様な符号を付けている。図2において、従来のゲート駆動回路(図9)に、ターンオフ時にIGBTモジュール2の内部インダクタンス5に発生する電圧を検出する電圧検出回路12、ターンオフ信号が入力されてから電圧検出回路12が電圧を検出するまでの時間と予め定められた設定時間とを比較する検出時間比較回路13、検出時間比較回路13の結果に応じてゲートオン抵抗値を選定する抵抗値選定回路、小電流逆回復時に高抵抗11でIGBT3をドライブするスイッチ素子11で構成される。   FIG. 2 shows a circuit configuration example of the gate driving device of the present invention. Components having the same functions as those of the conventional example of FIG. In FIG. 2, a voltage detection circuit 12 for detecting a voltage generated in the internal inductance 5 of the IGBT module 2 at the time of turn-off, and a voltage detection circuit 12 after the turn-off signal is input to the conventional gate drive circuit (FIG. 9). A detection time comparison circuit 13 that compares a time until detection with a predetermined set time, a resistance value selection circuit that selects a gate-on resistance value according to the result of the detection time comparison circuit 13, and a high resistance during small current reverse recovery 11 includes a switch element 11 that drives the IGBT 3.

次に本発明によるゲート駆動装置の動作を、図3及び図4に基づいて説明する。図3は通常電流時の動作波形、図4は小電流時の動作波形である。図2において、インターフェイス回路15からオフ信号が出力されて、ゲート電圧VGEがしきい値電圧VGE(th)まで下降すると、コレクタ−エミッタ間電圧VCEが上昇を始める。VCEが電源電圧Edまで達すると、コレクタ電流Icが減少し、IGBTモジュール2の内部インダクタンス5に電圧VLinが発生する。この電圧VLinを電圧検出回路12が検出すると、検出時間比較回路13が、ターンオフ信号が出力されてから電圧検出回路12が電圧を検出するまでの時間T1と予め定められた設定時間T0とを比較する。   Next, the operation of the gate driving apparatus according to the present invention will be described with reference to FIGS. FIG. 3 shows an operation waveform at a normal current, and FIG. 4 shows an operation waveform at a small current. In FIG. 2, when the off signal is output from the interface circuit 15 and the gate voltage VGE falls to the threshold voltage VGE (th), the collector-emitter voltage VCE starts to rise. When VCE reaches the power supply voltage Ed, the collector current Ic decreases and a voltage Vlin is generated in the internal inductance 5 of the IGBT module 2. When the voltage detection circuit 12 detects this voltage VLin, the detection time comparison circuit 13 compares the time T1 from when the turn-off signal is output until the voltage detection circuit 12 detects the voltage with a predetermined set time T0. To do.

ターンオフ時の電流が小さい場合はIGBTの帰還容量(コレクタ・ゲート間容量)を充電する時間が長くなり、ターンオフ時の電流が大きければ充電時間は短くなる。この結果、コレクタ電流Icが下降し始めるまでの時間T1は電流が小さい時は長く、電流が大きい時は短くなる。従って、検出時間比較回路13の比較結果がT1<T0であれば(図3参照)、抵抗値選定回路14が、次のターンオン時における対抗アームのFWDが通常電流で逆回復することを推測し、通常のゲートオン抵抗8を選定する。比較結果がT1>T0であれば(図4参照)、抵抗値選定回路14が、次のターンオン時における対抗アームのFWDが小電流で逆回復することを推測し、高抵抗のゲートオン抵抗11を選定する。   When the current at turn-off is small, the time for charging the feedback capacity (collector-gate capacity) of the IGBT becomes long, and when the current at turn-off is large, the charge time becomes short. As a result, the time T1 until the collector current Ic starts to decrease is long when the current is small and short when the current is large. Therefore, if the comparison result of the detection time comparison circuit 13 is T1 <T0 (see FIG. 3), the resistance value selection circuit 14 estimates that the FWD of the opposing arm at the next turn-on reversely recovers with the normal current. The normal gate-on resistance 8 is selected. If the comparison result is T1> T0 (see FIG. 4), the resistance value selection circuit 14 estimates that the FWD of the opposing arm at the next turn-on reversely recovers with a small current, and sets the high resistance gate-on resistance 11 Select.

次にインターフェイス回路15からオン信号が出力されると、通常のゲートオン抵抗8が選定されている場合は、スイッチ素子6がオンして、通常のゲートオン抵抗8でIGBT3がターンオン動作する。また、高抵抗のゲートオン抵抗11が選定されている場合は、スイッチ素子10がオンして、高抵抗のゲートオン抵抗11でIGBT3がターンオン動作をする。   Next, when an on signal is output from the interface circuit 15, if the normal gate-on resistance 8 is selected, the switch element 6 is turned on, and the IGBT 3 is turned on by the normal gate-on resistance 8. When the high resistance gate-on resistance 11 is selected, the switch element 10 is turned on, and the IGBT 3 is turned on by the high resistance gate-on resistance 11.

このことにより、対向アームのFWDが、通常電流で逆回復する時は通常抵抗でターンオン、小電流で逆回復する時は高抵抗でターンオンさせることができ、通常電流動作時のターンオン損失を増加させずに、FWDが小電流で逆回復する時のサージ電圧と振動現象を抑制することが可能となる。   As a result, when the FWD of the opposing arm reverses with normal current, it can be turned on with normal resistance, and when it recovers with small current, it can be turned on with high resistance, increasing the turn-on loss during normal current operation. In addition, it is possible to suppress the surge voltage and vibration phenomenon when the FWD is reversely recovered with a small current.

図5に、本発明の第2の実施例を示す。
第1の実施例である図2との違いは、第1の実施例が対向アームのFWDが通常電流で逆回復する時はIGBTを通常抵抗でターンオンさせ、小電流で逆回復する時は高抵抗でターンオンさせるのに対し、第2の実施例では、ゲート抵抗値は切替えずに、対向アームのFWDが通常電流で逆回復する時はIGBTを通常のゲート駆動電源電圧Pでターンオンさせ、小電流で逆回復する時は通常より低いゲート駆動電源電圧P1でターンオンさせる点である。これを実現するため、抵抗値選定回路14の代わりに電源電圧選定回路14aを設け、図2の抵抗11は用いず、スイッチ素子10とダイオード11aの直列回路を通常のゲート駆動電源電圧Pよりも低いゲート駆動電源電圧P1とスイッチ素子6と抵抗8との接続点に接続した回路構成としている。
FIG. 5 shows a second embodiment of the present invention.
The difference from FIG. 2 which is the first embodiment is that when the FWD of the opposite arm reversely recovers with a normal current, the IGBT is turned on with a normal resistance, and when the reverse recovery with a small current is high, the first embodiment is high. On the other hand, in the second embodiment, the gate resistance value is not switched and the IGBT is turned on with the normal gate drive power supply voltage P when the FWD of the opposite arm is reversely recovered with the normal current. When reverse recovery is performed with current, it is turned on at a lower gate drive power supply voltage P1 than usual. In order to realize this, a power supply voltage selection circuit 14a is provided in place of the resistance value selection circuit 14, and the series circuit of the switch element 10 and the diode 11a is used rather than the normal gate drive power supply voltage P without using the resistor 11 of FIG. The circuit configuration is such that it is connected to the connection point of the low gate drive power supply voltage P 1, the switch element 6 and the resistor 8.

このことにより、対向アームのFWDが、通常電流で逆回復する時は通常のゲート駆動電源電圧でターンオン、小電流で逆回復する時は通常より低いゲート駆動電源電圧でターンオンさせることができ、通常電流動作時のターンオン損失を増加させずに、FWDが小電流で逆回復する時のサージ電圧と振動現象を抑制することが可能となる。 As a result, the FWD of the opposite arm can be turned on with a normal gate drive power supply voltage when reversely recovered with a normal current, and can be turned on with a lower gate drive power supply voltage than normal when reversely recovered with a small current. Without increasing the turn-on loss during the current operation, it is possible to suppress the surge voltage and vibration phenomenon when the FWD reversely recovers with a small current.

図6に本発明の第3の実施例を示す。図6は、本発明によるゲート駆動装置を接続したIGBTモジュールを、複数個直列に接続した場合の例である(2直列分を図示)。図6において、IGBTモジュール2は、IGBT3、FWD4、内部インダクタンス5から構成され、IGBTモジュール17は、IGBT18、FWD19、内部インダクタンス20から構成され、IGBTモジュール2のゲート端子G、主エミッタ端子E1、補助エミッタ端子E2にゲート駆動装置1が、IGBTモジュール17のゲート端子G、主エミッタ端子E1、補助エミッタ端子E2にゲート駆動装置2が接続される。   FIG. 6 shows a third embodiment of the present invention. FIG. 6 shows an example in which a plurality of IGBT modules connected to the gate driving device according to the present invention are connected in series (two series components are shown). In FIG. 6, the IGBT module 2 is composed of IGBT3, FWD4, and internal inductance 5, and the IGBT module 17 is composed of IGBT18, FWD19, and internal inductance 20, and includes the gate terminal G, main emitter terminal E1, auxiliary circuit of the IGBT module2. The gate driver 1 is connected to the emitter terminal E2, and the gate driver 2 is connected to the gate terminal G, the main emitter terminal E1, and the auxiliary emitter terminal E2 of the IGBT module 17.

本実施例では、ゲート駆動装置1および2が同期した信号を入力として直列接続したIGBT2及び17を駆動する。各々のゲート駆動装置の動作は、上述した第1の実施例および第2の実施例と同様である。 In this embodiment, the gate drivers 1 and 2 drive the IGBTs 2 and 17 connected in series with the synchronized signal as an input. The operation of each gate driving device is the same as in the first and second embodiments described above.

以上より、IGBTモジュールを複数個直列に接続した場合においても、各IGBTモジュールについて、通常電流動作時のターンオン損失を増加させずに、FWDが小電流で逆回復する時のサージ電圧と振動現象を抑制することが可能となる。   From the above, even when multiple IGBT modules are connected in series, the surge voltage and vibration phenomenon when FWD reversely recovers with a small current without increasing the turn-on loss during normal current operation for each IGBT module. It becomes possible to suppress.

本発明は、IGBTと逆並列にFWDを接続したスイッチ回路を用いて構成する、スイッチング電源、電動機駆動装置、無停電電源装置などの電力変換装置への適用が可能である。   The present invention can be applied to power conversion devices such as switching power supplies, electric motor drive devices, and uninterruptible power supply devices that are configured using a switch circuit in which an FWD is connected in antiparallel with the IGBT.

本発明の構成を示すゲート駆動装置とIGBTモジュールの接続構成図Connection diagram of gate drive device and IGBT module showing configuration of the present invention 本発明の第1の実施例を示すゲート駆動装置の回路構成Circuit configuration of gate drive apparatus showing first embodiment of the present invention 通常電流時の図2の動作説明図Operation explanatory diagram of FIG. 2 at normal current 小電流時の図2の動作説明図Operation explanatory diagram of FIG. 2 at a small current 本発明の第2の実施例を示すゲート駆動装置の回路構成Circuit configuration of gate driving apparatus showing second embodiment of the present invention 本発明の第3の実施例を示すゲート駆動装置とIGBTモジュールの接続構成図Connection diagram of gate drive device and IGBT module showing third embodiment of the present invention IGBTを使用した周知の電圧形インバータの回路構成図Circuit configuration diagram of known voltage source inverter using IGBT 図7の1相分の等価回路図Equivalent circuit diagram for one phase in Fig. 7 従来のゲート駆動装置の回路構成例Circuit configuration example of a conventional gate drive device 通常電流時の図9の動作説明図9 is an operation explanatory diagram of normal current. 小電流時の図9の動作説明図Explanation of operation in Fig. 9 at low current

符号の説明Explanation of symbols

1、16、31・・・ゲート駆動装置(GDU)
2、17、32・・・IGBTモジュール 3、18、33・・・IGBT
4、19、34・・・FWD
5、20、24〜29、35・・・内部インダクタンス
6、7、10・・・スイッチ素子 8,9,11・・・抵抗
11a・・・ダイオード 12・・・電圧検出回路
13・・・検出時間比較回路 14・・・抵抗値選定回路
14a・・・駆動電源選択回路 15・・・インターフェイス回路
21・・・交流電源 22・・・整流器 23、36・・・コンデンサ
30・・・電動機 37・・・配線インダクタンス
38・・・L負荷
1, 16, 31 ... Gate drive unit (GDU)
2, 17, 32 ... IGBT module 3, 18, 33 ... IGBT
4, 19, 34 ... FWD
5, 20, 24 to 29, 35 ... internal inductance 6, 7, 10 ... switch element 8, 9, 11 ... resistor 11a ... diode 12 ... voltage detection circuit 13 ... detection Time comparison circuit 14 ... resistance value selection circuit 14a ... drive power supply selection circuit 15 ... interface circuit 21 ... AC power supply 22 ... rectifier 23, 36 ... capacitor 30 ... electric motor 37 ..Wiring inductance 38 ... L load

Claims (2)

電力変換装置に用いる電圧駆動型半導体素子を駆動するゲート駆動装置において、ターンオフ時に電圧駆動型半導体素子に接続されている内部インダクタンスに発生する電圧を検出するインダクタンス電圧検出手段と、オフゲート信号が入力されてから前記インダクタンス電圧検出手段が電圧検出するまでの検出時間と予め定められた設定時間とを比較する比較手段と、前記比較結果に応じてターンオン用のゲート駆動条件を切替える切替手段と、を備え、前記オフゲート信号が入力されてから前記インダクタンス電圧検出手段が電圧検出するまでの検出時間が前記予め定められた設定時間より長い場合に、前記切替手段は次のターンオン用ゲート駆動条件としてゲートオン抵抗を通常のゲートオン抵抗より高抵抗のゲートオン抵抗に切替えることを特徴とする電圧駆動型半導体素子のゲート駆動装置。 In a gate driving device for driving a voltage driven semiconductor element used in a power converter, an inductance voltage detecting means for detecting a voltage generated in an internal inductance connected to the voltage driven semiconductor element at the time of turn-off, and an off gate signal are input. Comparison means for comparing a detection time from when the inductance voltage detection means detects a voltage to a preset set time, and a switching means for switching the gate drive condition for turn-on according to the comparison result. When the detection time from when the off-gate signal is input until the inductance voltage detection means detects the voltage is longer than the predetermined set time, the switching means sets the gate-on resistance as the next turn-on gate drive condition. Switch to higher gate-on resistance than normal gate-on resistance The gate drive voltage driven type semiconductor element, characterized in that. 電力変換装置に用いる電圧駆動型半導体素子を駆動するゲート駆動装置において、ターンオフ時に電圧駆動型半導体素子に接続されている内部インダクタンスに発生する電圧を検出するインダクタンス電圧検出手段と、オフゲート信号が入力されてから前記インダクタンス電圧検出手段が電圧検出するまでの検出時間と予め定められた設定時間とを比較する比較手段と、前記比較結果に応じてターンオン用のゲート駆動条件を切替える切替手段と、を備え、前記オフゲート信号が入力されてから前記インダクタンス電圧検出手段が電圧検出するまでの検出時間が前記予め定められた設定時間より長い場合に、前記切替手段はゲート駆動電源電圧を次のターンオン用ゲート駆動条件として通常のゲート駆動電源電圧より低い電圧のゲート駆動電源電圧に切替えることを特徴とする電圧駆動型半導体素子のゲート駆動装置。 In a gate driving device for driving a voltage driven semiconductor element used in a power converter, an inductance voltage detecting means for detecting a voltage generated in an internal inductance connected to the voltage driven semiconductor element at the time of turn-off, and an off gate signal are input. Comparison means for comparing a detection time from when the inductance voltage detection means detects a voltage to a preset set time, and a switching means for switching the gate drive condition for turn-on according to the comparison result. When the detection time from when the off-gate signal is input to when the inductance voltage detection means detects a voltage is longer than the predetermined set time, the switching means supplies the gate drive power supply voltage to the next turn-on gate drive. As a condition, the gate drive voltage is lower than the normal gate drive voltage The gate drive voltage driven type semiconductor element and switches the voltage.
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