JP2020014315A - Semiconductor device - Google Patents

Abstract

To prevent breakdown of a power semiconductor element by suppressing surge voltage.SOLUTION: A semiconductor device 1 has a power semiconductor element 1a, a current detection circuit 1b1, and a high-side control circuit 1b3. The power semiconductor element 1a includes multi-phase high-side switch elements sw1 and sw2, multi-phase low-side switch elements sw11 and sw12, and supplies power from wirings 3a and 3b to a load M. The current detection circuit 1b1 detects a short-circuit current flowing in the power semiconductor element 1a when the wirings 3a and 3b are short circuited, and outputs an overcurrent detection signal dc. The high-side control circuit 1b3 delays a transition time when the high-side switch element transits from ON to OFF on the basis of a high-side logic signal Hin and an overcurrent detection signal dc.SELECTED DRAWING: Figure 1

Description

  The present technology relates to a semiconductor device.

  The power semiconductor module has a drive circuit including a power semiconductor element (IGBT: Insulated Gate Bipolar Transistor) and a control circuit for controlling the operation of the drive circuit, and is used for a three-phase inverter for supplying power to a load such as a motor. Applied.

<Overall configuration of conventional power semiconductor module>
FIG. 12 is a diagram illustrating an example of the configuration of the power semiconductor module. The power semiconductor module 100 includes a power semiconductor element 10, a control circuit 20, capacitors C1 and C2, and a resistor R1.

Power semiconductor element 10 includes IGBTs 11 to 16 and diodes D1 to D6.
The control circuit 20 includes a high-side control circuit 21 that drives and controls the IGBTs 11, 13, and 15 that are located on the high side of the power semiconductor device 10, and a low-side control that drives and controls the IGBTs 12, 14, and 16 that are located on the low side of the power semiconductor device 10. A control circuit 22 is included.

  In the power semiconductor device 10, the U phase includes IGBTs 11 and 12 and diodes D1 and D2, the V phase includes IGBTs 13 and 14, and diodes D3 and D4, and the W phase includes IGBTs 15 and 16 and a diode. D5 and D6 are included.

  Further, the capacitor C1 functions as a smoothing capacitor, and the capacitor C2 functions as a stub circuit for absorbing a surge voltage. The resistor R1 is a shunt resistor for current detection.

  For example, a motor M is connected as a load to the output terminals out1 to out3. The power semiconductor element 10 converts a DC high voltage flowing through the line L1 into a three-phase AC, and converts the AC wiring Lu (U-phase line), the wiring Lv (V-phase line) and the wiring Lw (W-phase line) to the motor M. To supply AC.

  Further, in the power semiconductor element 10, since the current is turned on / off with respect to the inductive load such as the motor M to drive the load, the IGBTs 11 to 16 are subjected to FWD (Free) in order to return the load current. The diodes D1 to D6, which are Wheel Diodes, are respectively connected to the diodes D1 to D6.

  That is, at the moment when the IGBTs 11 to 16 are turned off, a counter electromotive force is generated from the inductive load of the motor M. Therefore, the diodes D1 to D6 are connected in anti-parallel to the IGBTs 11 to 16, respectively. The load current is circulated.

  The connection relationship between the components will be described. One end of each of the capacitors C1, C2, the collectors of the IGBTs 11, 13, 15 and the cathodes of the diodes D1, D3, D5 are connected through a line L1 connected to the P terminal.

  The other ends of the capacitors C1 and C2, one end of the resistor R1, and a reference potential (hereinafter referred to as GND) are connected through a line L2 connected to the N terminal. The other end of the resistor R1 is connected to the emitters of the IGBTs 12, 14, and 16, the anodes of the diodes D2, D4, and D6, and the low-side control circuit 22.

  The emitter of the IGBT 11 is connected to the anode of the diode D1, the collector of the IGBT 12, the cathode of the diode D2, the high-side control circuit 21, and the output terminal out1. The output terminal out1 is connected to the motor M through the U-phase line Lu.

  The connection point between the emitter of the IGBT 11 and the collector of the IGBT 12 is a U-phase output terminal. Through this connection point, a U-phase current flowing through the U-phase line Lu is output from the output terminal out1 to the motor M.

  The emitter of the IGBT 13 is connected to the anode of the diode D3, the collector of the IGBT 14, the cathode of the diode D4, the high-side control circuit 21, and the output terminal out2. The output terminal out2 is connected to the motor M through the V-phase line Lv.

  A connection point between the emitter of the IGBT 13 and the collector of the IGBT 14 is a V-phase output terminal, and a V-phase current flowing through the V-phase line Lv is output from the output terminal out2 to the motor M through this connection point.

  The emitter of the IGBT 15 is connected to the anode of the diode D5, the collector of the IGBT 16, the cathode of the diode D6, the high-side control circuit 21, and the output terminal out3. The output terminal out3 is connected to the motor M through the W-phase line Lw.

  A connection point between the emitter of the IGBT 15 and the collector of the IGBT 16 is a W-phase output terminal, and a W-phase current flowing through the W-phase line Lw is output from the output terminal out3 to the motor M through this connection point.

  On the other hand, high-side logic signals Hin1, Hin2, and Hin3 are input to the high-side control circuit 21 from the higher order. The drive signals g1, g2, g3 output from the high-side control circuit 21 are input to the gates of the IGBTs 11, 13, and 15, respectively.

  The low-side logic signals Lin1, Lin2, and Lin3 are input to the low-side control circuit 22 from the higher order. The drive signals g4, g5, and g6 output from the low-side control circuit 22 are input to the gates of the IGBTs 12, 14, and 16, respectively.

<Configuration of conventional high-side control circuit>
FIG. 13 is a diagram illustrating an example of the configuration of the high-side control circuit. The high side control circuit 21 includes a high side U phase control circuit 21u, a high side V phase control circuit 21v, and a high side W phase control circuit 21w.

  The high-side U-phase control circuit 21u includes a driver circuit 21u1, the high-side V-phase control circuit 21v includes a driver circuit 21v1, and the high-side W-phase control circuit 21w includes a driver circuit 21w1.

  The driver circuit 21u1 generates a drive signal g1 based on the level of a high-side logic signal Hin1 output from a higher-level (hereinafter, referred to as a higher-level processor) such as a CPU (Central Processing Unit), and drives the IGBT 11 with the drive signal g1. .

  For example, when the high-side logic signal Hin1 is true (hereinafter referred to as H level), the driver circuit 21u1 outputs a drive signal g1 having a level required to turn on the IGBT 11. When the high-side logic signal Hin1 is false (hereinafter referred to as L level), the drive signal g1 having the level required for turning off the IGBT 11 is output.

  Similarly, the driver circuit 21v1 generates a drive signal g2 based on the level of the high-side logic signal Hin2 output from the host processor, and drives the IGBT 13 with the drive signal g2.

  Similarly, the driver circuit 21w1 generates a drive signal g3 based on the level of the high-side logic signal Hin3 output from the host processor, and drives the IGBT 15 with the drive signal g3.

<Configuration of conventional low-side control circuit>
FIG. 14 is a diagram illustrating an example of the configuration of the low-side control circuit. The low-side control circuit 22 includes a low-side U-phase control circuit 22u, a low-side V-phase control circuit 22v, a low-side W-phase control circuit 22w, and an overcurrent protection circuit 23.

  The low-side U-phase control circuit 22u includes a driver circuit 22u1, the low-side V-phase control circuit 22v includes a driver circuit 22v1, and the low-side W-phase control circuit 22w includes a driver circuit 22w1.

  The driver circuit 22u1 generates a drive signal g4 based on the level of the low side logic signal Lin1 output from the host processor, and drives the IGBT 12 with the drive signal g4.

  That is, when the low-side logic signal Lin1 is at the H level, the driver circuit 22u1 outputs a drive signal g4 having a level required to turn on the IGBT 12. When the low-side logic signal Lin1 is at L level, the drive signal g4 having the level required to turn off the IGBT 12 is output.

  Similarly, the driver circuit 22v1 generates a drive signal g5 based on the level of the low-side logic signal Lin2 output from the host processor, and drives the IGBT 14 with the drive signal g5.

  Similarly, the driver circuit 22w1 generates a drive signal g6 based on the level of the low-side logic signal Lin3 output from the host processor, and drives the IGBT 16 with the drive signal g6.

  The overcurrent protection circuit 23 includes a current detection circuit 23a. The current detection circuit 23a detects a current flowing through the IGBT and detects whether or not the current is in an overcurrent state. In the case of an overcurrent state, an overcurrent detection signal dc is transmitted to the driver circuits 22u1, 22v1, and 22w1. The driver circuits 22u1, 22v1, and 22w1 that have received the overcurrent detection signal dc turn off the IGBTs 12, 14, and 16.

<Prior art documents>
As a conventional technique of a power semiconductor module, there has been proposed a technique of suppressing a surge voltage by performing an operation of turning off a switch element of one of an upper arm and a lower arm and turning off a switch element of the other arm in a stepwise manner ( Patent Document 1).

JP 2014-217151 A

  In the configuration of the power semiconductor module 100 shown in FIG. 12 described above, when a short circuit occurs between output phases, the IGBT located on the high side may be destroyed by a surge voltage.

<IGBT breakdown during short circuit between U-phase and V-phase>
The process leading to IGBT destruction will be described using an example in which a short circuit occurs between the U-phase line Lu and the V-phase line Lv.

FIGS. 15 to 18 are diagrams for explaining an operation leading to IGBT destruction when a short circuit occurs between output phases. 15 to 18 show states St1 to St4, respectively.
[State St1] A short circuit occurs between the U-phase line Lu and the V-phase line Lv (short-circuit point s1), the IGBT 11 is turned on (the IGBTs 13 and 15 are turned off), and then the IGBT 14 is turned on (the IGBTs 12 and 16 are turned off). Shall be.

  The flow of the short-circuit current at this time is indicated by an arrow ar1. That is, a short-circuit current flows in the direction of the collector of the IGBT 11, the emitter of the IGBT 11, the short-circuit point s1, the collector of the IGBT 14, and the emitter of the IGBT 14.

  [State St2] When the short-circuit current generated in state St1 is an overcurrent state, the IGBT 14 switches from on to off. The flow of the short-circuit current at this time is indicated by an arrow ar2. That is, a short-circuit current flows in the direction of the collector of the IGBT 11, the emitter of the IGBT 11, the short-circuit point s1, the anode of the diode D3, and the cathode of the diode D3, and a high-side reflux operation is performed.

The operation of switching the IGBT 14 from on to off will be described. First, the short-circuit current flowing through the IGBT 14 is converted into a voltage by the shunt resistor R1.
The current detection circuit 23a illustrated in FIG. 14 compares the converted voltage with a preset threshold value, and when the voltage exceeds the threshold value, detects that an overcurrent has occurred, and supplies an overcurrent to the driver circuit 22v1. The detection signal dc is transmitted.

  Upon receiving the overcurrent detection signal dc, the driver circuit 22v1 sets the drive signal g5 to L level and turns off the IGBT 14. With such a flow, the IGBT 14 switches from on to off.

  [State St3] When the short-circuit current is in an overcurrent state, the IGBT 11 switches from on to off. At this time, the wiring inductor on the wiring through which the short-circuit current flows acts to keep the initial current flowing, so that the flow of the short-circuit current is indicated by an arrow ar3.

That is, a short-circuit current flows in the direction of the anode of the diode D2 → the cathode of the diode D2 → the short-circuit point s1 → the anode of the diode D3 → the cathode of the diode D3.
The operation of switching the IGBT 11 from ON to OFF will be described. When the driver circuit 21u1 receives the L-level high-side logic signal Hin1, it generates an L-level drive signal g1 and turns off the IGBT 11. With such a flow, the IGBT 11 switches from on to off.

  As described above, in the operations in the states St2 and St3, the short-circuit between the U-phase and the V-phase causes the IGBT 14 to be turned off, and then the IGBT 11 to be turned off to perform the overcurrent protection operation.

  However, if the short-circuit current generated when the output phase is short-circuited is excessive, di / dt (current change (slope of cutoff current) during transition of the IGBT from turn-on to turn-off) during the regenerative operation increases. In this case, in the state St3, a surge voltage of (L × di / dt) is applied to the IGBT 11 due to the influence of the wiring inductance L such as the short-circuit point s1, and the avalanche breakdown occurs in the IGBT 11.

  [State St4] When avalanche breakdown occurs in the IGBT 11, a voltage (surge voltage) higher than the withstand voltage of the IGBT 11 is applied, and the IGBT 11 is destroyed by avalanche. Immediately after the power regeneration, the high-side U-phase IGBT 11 is destroyed or short-circuited by the surge voltage, so that the reflux operation as shown in the state St4 is performed. The flow of the short-circuit current at this time is indicated by an arrow ar2, which is the same as the flow of the state St2 in FIG.

<Operation waveform of IGBT destruction at the time of short circuit between U phase and V phase>
FIGS. 19 and 20 are diagrams showing operation waveforms of IGBT breakdown when a short circuit occurs between the U-phase and the V-phase. FIG. 19 shows the operation waveforms in FIGS. 15 to 18 described above, and FIG. 20 shows an enlarged waveform in the period T3 in FIG. The vertical axis is voltage or current, and the horizontal axis is time.

  The waveform ch1 is a PU voltage between the node P and the node U, and is a collector-emitter voltage VCE of the IGBT11. The waveform ch2 is a PN voltage between the node P and the node N, and the waveform ch3 is a U-phase current.

[Period T1] This is an operation waveform in the state St1 of FIG. The high-side IGBT 11 and the low-side IGBT 14 are turned on, and a short circuit between output phases occurs.
[Period T2] This is an operation waveform in the state St2 of FIG. The overcurrent protection function is activated by the occurrence of the short-circuit current, and the low-side IGBT 14 is turned off, so that the high-side reflux operation is performed.

[Period T3] An operation waveform in the state St3 of FIG. Turning off the high-side IGBT 11 leads to power regeneration.
[Period T4] This is an operation waveform in the state St4 of FIG. Immediately after power regeneration, the high-side U-phase IGBT 11 is destroyed or short-circuited by a surge voltage. FIG. 20 shows the peak of the PU voltage, the peak of the PN voltage, and the slope (−di / dt) of the cutoff current.

<IGBT breakdown at the time of short circuit between V phase and W phase>
As described above, even when a short circuit occurs between the V-phase line Lv and the W-phase line Lw, IGBT breakdown may occur.

FIGS. 21 to 24 are diagrams for explaining an operation leading to IGBT destruction when a short circuit occurs between output phases. 21 to 24 show states St11 to St14, respectively.
[State St11] A short circuit occurs between the V-phase line Lv and the W-phase line Lw (short-circuit point s2), the IGBT 13 is turned on (the IGBTs 11 and 15 are turned off), and the IGBT 16 is turned on (the IGBTs 12 and 14 are turned off). Shall be.

  The flow of the short-circuit current at this time is indicated by an arrow ar11, and the short-circuit current flows in the direction of the collector of the IGBT 13, the emitter of the IGBT 13, the short-circuit location s2, the collector of the IGBT 16, and the emitter of the IGBT 16.

  [State St12] The IGBT 16 switches from on to off (the description of the switching operation is omitted). The flow of the short-circuit current at this time is indicated by an arrow ar12, and a short-circuit current flows in the direction of the collector of the IGBT 13, the emitter of the IGBT 13, the short-circuit point s2, the anode of the diode D5, and the cathode of the diode D5.

  [State St13] The IGBT 13 switches from ON to OFF (the description of the switching operation is omitted). The flow of the short-circuit current at this time is indicated by an arrow ar13, and the short-circuit current flows in the direction of the anode of the diode D4 → the cathode of the diode D4 → the short-circuit location s2 → the anode of the diode D5 → the cathode of the diode D5. If the short-circuit current is excessive, a surge voltage (L × di / dt) is generated in the IGBT 13, and avalanche breakdown occurs in the IGBT 13.

  [State St14] When avalanche breakdown occurs in the IGBT 13, a voltage higher than the breakdown voltage of the IGBT 13 is applied, and the IGBT 13 is destroyed by avalanche. Immediately after the power regeneration, the high-side V-phase IGBT 13 is destroyed or short-circuited by the surge voltage, so that a recirculation operation as shown in a state St14 is performed. The flow of the short-circuit current at this time is indicated by an arrow ar12, which is the same flow as the state St12 in FIG.

<IGBT breakdown during short circuit between U and W phases>
As described above, even when a short circuit occurs between the U-phase line Lu and the W-phase line Lw, IGBT breakdown may occur.

FIGS. 25 to 28 are diagrams showing an operation leading to IGBT destruction when a short circuit occurs between output phases. FIGS. 25 to 28 show states St21 to St24, respectively.
[State St21] A short circuit occurs between the U-phase line Lu and the W-phase line Lw (short-circuit point s3), the IGBT 15 is turned on (the IGBTs 11 and 13 are turned off), and then the IGBT 12 is turned on (the IGBTs 14 and 16 are turned off). Shall be.

  The flow of the short-circuit current at this time is indicated by an arrow ar21, and the short-circuit current flows in the direction of the collector of the IGBT 15, the emitter of the IGBT 15, the short-circuit location s3, the collector of the IGBT 12, and the emitter of the IGBT 12.

  [State St22] The IGBT 12 switches from on to off (the description of the switching operation is omitted). The flow of the short-circuit current at this time is indicated by an arrow ar22, and a short-circuit current flows in the direction of the collector of the IGBT 15, the emitter of the IGBT 15, the short-circuit point s3, the anode of the diode D1, and the cathode of the diode D1, thereby performing a high-side reflux operation.

  [State St23] The IGBT 15 switches from on to off (the description of the switching operation is omitted). The flow of the short-circuit current at this time is indicated by an arrow ar23, and the short-circuit current flows in the direction of the anode of the diode D6 → the cathode of the diode D6 → the short-circuit point s3 → the anode of the diode D1 → the cathode of the diode D1. If the short-circuit current is excessive, a surge voltage (L × di / dt) is generated in the IGBT 15 and avalanche breakdown occurs in the IGBT 15.

  [State St24] When avalanche breakdown occurs in the IGBT 15, a voltage higher than the withstand voltage of the IGBT 15 is applied, and the IGBT 15 is avalanche-destructed. Immediately after the power regeneration, the high-side W-phase IGBT 15 is destroyed or short-circuited by the surge voltage, so that the reflux operation as shown in the state St24 is performed. The flow of the short-circuit current at this time is indicated by an arrow ar22, which is the same as the flow of the state St22 in FIG.

As described above, when a short circuit occurs between the output phases, the IGBT located on the high side may be destroyed by the surge voltage.
The present invention has been made in view of such a point, and an object of the present invention is to provide a semiconductor device which suppresses a surge voltage and prevents IGBT from being destroyed.

  In order to solve the above problems, a semiconductor device is provided. In the semiconductor device, a plurality of high-side switch elements arranged in a multi-phase and a plurality of low-side elements arranged in a multi-phase are connected in series to each phase, respectively, and each of the high-side switch element and the low-side switch element A power semiconductor element for supplying power from a connection point to a load, a current detection circuit for detecting a current value flowing through the power semiconductor element, a high-side control circuit for controlling on / off driving of a plurality of high-side switch elements, and a plurality of low-side switches And a low-side control circuit for controlling on / off driving of the elements. When the current detection circuit detects a current value exceeding the reference value, the high-side control circuit delays the time until the high-side switch element that is being driven is turned off.

  It is possible to suppress the surge voltage and prevent the power semiconductor element from being destroyed.

FIG. 3 illustrates an example of a configuration of a semiconductor device. FIG. 3 illustrates an example of a configuration of a semiconductor device. FIG. 3 is a diagram illustrating an example of a configuration of a high-side control circuit. FIG. 3 is a diagram illustrating an example of a configuration of a low-side control circuit. FIG. 4 is a diagram illustrating detection of a short-circuit current by a current detection circuit. FIG. 4 is a diagram illustrating detection of a short-circuit current by a current detection circuit. FIG. 4 is a diagram illustrating detection of a short-circuit current by a current detection circuit. FIG. 3 is a diagram illustrating an example of a configuration of a drive stop delay circuit. FIG. 4 is a diagram illustrating input / output characteristics of a drive stop delay circuit. It is a figure showing an operation time chart of a conventional device. It is a figure showing an operation time chart of the present invention. It is a figure showing an example of composition of a power semiconductor module. FIG. 3 is a diagram illustrating an example of a configuration of a high-side control circuit. FIG. 3 is a diagram illustrating an example of a configuration of a low-side control circuit. FIG. 9 is a diagram for explaining an operation leading to IGBT breakdown when a short circuit occurs between output phases (short circuit between U phase and V phase). FIG. 9 is a diagram for explaining an operation leading to IGBT breakdown when a short circuit occurs between output phases (short circuit between U phase and V phase). FIG. 9 is a diagram for explaining an operation leading to IGBT breakdown when a short circuit occurs between output phases (short circuit between U phase and V phase). FIG. 9 is a diagram for explaining an operation leading to IGBT breakdown when a short circuit occurs between output phases (short circuit between U phase and V phase). FIG. 9 is a diagram illustrating an operation waveform of IGBT breakdown when a short circuit occurs between a U phase and a V phase. FIG. 9 is a diagram illustrating an operation waveform of IGBT breakdown when a short circuit occurs between a U phase and a V phase. FIG. 7 is a diagram for explaining an operation leading to IGBT breakdown when a short circuit occurs between output phases (short circuit between V phase and W phase). FIG. 7 is a diagram for explaining an operation leading to IGBT breakdown when a short circuit occurs between output phases (short circuit between V phase and W phase). FIG. 7 is a diagram for explaining an operation leading to IGBT breakdown when a short circuit occurs between output phases (short circuit between V phase and W phase). FIG. 7 is a diagram for explaining an operation leading to IGBT breakdown when a short circuit occurs between output phases (short circuit between V phase and W phase). FIG. 9 is a diagram for explaining an operation leading to IGBT destruction when a short circuit occurs between output phases (short circuit between U phase and W phase). FIG. 9 is a diagram for explaining an operation leading to IGBT destruction when a short circuit occurs between output phases (short circuit between U phase and W phase). FIG. 9 is a diagram for explaining an operation leading to IGBT destruction when a short circuit occurs between output phases (short circuit between U phase and W phase). FIG. 9 is a diagram for explaining an operation leading to IGBT destruction when a short circuit occurs between output phases (short circuit between U phase and W phase).

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
A first embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device. The semiconductor device 1 has a power semiconductor element 1a and a control circuit 1b. The power semiconductor element 1a includes high-side switch elements sw1, sw2,... Arranged in multiple phases, and low-side switch elements sw11, sw12,. For the high-side / low-side switch element, for example, an IGBT that is a power semiconductor element is used.

  In addition, power is supplied to the load M from a wire 3a connected to a connection point between the high-side switch element sw1 and the low-side switch element sw11 and a wire 3b connected to a connection point between the high-side switch element sw2 and the low-side switch element sw12. . The wiring 3a and the wiring 3b are short-circuited by the short-circuit point s0.

  On the other hand, the control circuit 1b has a current detection circuit 1b1 and a high-side control circuit 1b3. The current detection circuit 1b1 detects a short-circuit current flowing through the power semiconductor element 1a when the multi-phase wirings 3a and 3b are short-circuited, and outputs an overcurrent detection signal dc when the short-circuit current exceeds a threshold.

  The high side control circuit 1b3 receives the high side logic signal Hin for controlling the switching operation of the high side switch element and the overcurrent detection signal dc. The high-side control circuit 1b3 causes the high-side switch element, in which the short-circuit current is flowing, to transition from on to off based on a combination of the logic levels of the high-side logic signal Hin and the overcurrent detection signal dc. Delay the transition time.

  With the configuration of the semiconductor device 1 described above, the transition time when the high-side switch element in which the short-circuit current is flowing transitions from on to off is delayed, so that the corresponding high-side switch element when an output phase short-circuit occurs. Such a surge voltage can be suppressed. Further, it is possible to prevent the destruction of the high-side switch element.

[Second embodiment]
Next, a second embodiment will be described in detail below. In the second embodiment, the mechanism of the semiconductor device 1 of FIG. 1 is applied to a power semiconductor module. Hereinafter, the same components as those described above are denoted by the same reference numerals, and the description of the components described above will be omitted as appropriate.

<Overall configuration>
FIG. 2 is a diagram illustrating an example of a configuration of a semiconductor device. The semiconductor device 1-1 includes a power semiconductor element 10 and a control circuit 20-1. The control circuit 20-1 includes a high-side control circuit 21-1 and a low-side control circuit 22-1.

  The high-side control circuit 21-1 controls driving of the IGBT 11 (high-side U-phase switch), IGBT 13 (high-side V-phase switch), and IGBT 15 (high-side W-phase switch) in the power semiconductor device 10. The high-side control circuit 21-1 implements the mechanism of the high-side control circuit 1b3 in FIG.

  The low-side control circuit 22-1 controls driving of the IGBT 12 (low-side U-phase switch), IGBT 14 (low-side V-phase switch), and IGBT 16 (low-side W-phase switch) in the power semiconductor device 10.

  The control circuit 20-1 has a mechanism for suppressing a surge voltage generated in the power semiconductor element 10, and the high side control circuit 21-1 has an overcurrent detection signal from the low side control circuit 22-1. dc has been input.

<Configuration of high-side control circuit>
FIG. 3 is a diagram illustrating an example of the configuration of the high-side control circuit. The high side control circuit 21-1 includes a high side U phase control circuit 21u-1, a high side V phase control circuit 21v-1 and a high side W phase control circuit 21w-1.

  The high side U-phase control circuit 21u-1 includes a driver circuit 21u1-1 and a drive stop delay circuit 21u2, and the high side V-phase control circuit 21v-1 includes a driver circuit 21v1-1 and a drive stop delay circuit 21v2. The high side W-phase control circuit 21w-1 includes a driver circuit 21w1-1 and a drive stop delay circuit 21w2.

  In the U phase, the drive stop delay circuit 21u2 receives the high side logic signal Hin1 output from the host processor and the overcurrent detection signal dc output from the low side control circuit 22-1.

  The drive stop delay circuit 21u2 generates and outputs a control signal for delaying a transition time from turning on to off the IGBT 11 by a predetermined time, based on a combination of the levels of the high side logic signal Hin1 and the overcurrent detection signal dc. .

  The driver circuit 21u1-1 outputs a control signal as a drive signal g1a of the IGBT 11, and drives the IGBT 11. In this case, the driver circuit 21u1-1 converts the level of the control signal to a predetermined level so as to be in a voltage range required for driving the IGBT 11, and outputs the same as the drive signal g1a.

  In the V phase, the drive stop delay circuit 21v2 receives the high side logic signal Hin2 output from the host processor and the overcurrent detection signal dc output from the low side control circuit 22-1.

  The drive stop delay circuit 21v2 generates and outputs a control signal for delaying a transition time from turning on the IGBT 13 to turning off the IGBT 13 by a predetermined time based on a combination of each level of the high side logic signal Hin2 and the overcurrent detection signal dc. .

  The driver circuit 21v1-1 outputs a control signal as a drive signal g2a of the IGBT 13, and drives the IGBT 13. In this case, the driver circuit 21v1-1 converts the level of the control signal to a predetermined level so as to be in a voltage range required for driving the IGBT 13, and outputs the same as the drive signal g2a.

  In the W phase, the drive stop delay circuit 21w2 receives the high side logic signal Hin3 output from the host processor and the overcurrent detection signal dc output from the low side control circuit 22-1.

  The drive stop delay circuit 21w2 generates and outputs a control signal for delaying a transition time from turning on to turning off the IGBT 15 by a predetermined time, based on a combination of each level of the high side logic signal Hin3 and the overcurrent detection signal dc. .

  The driver circuit 21w1-1 outputs a control signal as a drive signal g3a of the IGBT 15, and drives the IGBT 15. In this case, the driver circuit 21w1-1 converts the level of the control signal to a predetermined level so as to be in a voltage range required for driving the IGBT 15, and outputs the same as the drive signal g3a.

<Configuration of low-side control circuit>
FIG. 4 is a diagram illustrating an example of the configuration of the low-side control circuit. The low-side control circuit 22-1 includes the same components as the low-side control circuit 22 described above with reference to FIG. 14 is that the overcurrent detection signal dc is transmitted to the low-side U / V / W-phase control circuits 22u, 22v, and 22w in FIG. 14, but the low-side control circuit 22-1 shown in FIG. The current detection signal dc is also transmitted to the high side control circuit 21-1. Other configurations are the same as those in FIG. Note that the current detection circuit 23a corresponds to the current detection circuit 1b1 in FIG.

<Detection of short-circuit current>
5 to 7 are diagrams showing detection of a short-circuit current by the current detection circuit. In FIG. 5, when the U-phase line Lu and the V-phase line Lv are short-circuited, a short-circuit current flows in the direction of arrow ar1. At this time, the current detection circuit 23a detects a short-circuit current output from the emitter of the IGBT 14.

  In FIG. 6, when the V-phase line Lv and the W-phase line Lw are short-circuited, a short-circuit current flows in the direction of arrow ar11. At this time, the current detection circuit 23a detects a short-circuit current output from the emitter of the IGBT16.

  In FIG. 7, when the U-phase line Lu and the W-phase line Lw are short-circuited, a short-circuit current flows in the direction of the arrow ar21. At this time, the current detection circuit 23a detects a short-circuit current output from the emitter of the IGBT 12.

<Configuration of drive stop delay circuit>
FIG. 8 is a diagram showing an example of the configuration of the drive stop delay circuit. The drive stop delay circuit 30 of FIG. 8 is applied to the drive stop delay circuits 21u2, 21v2, 21w2 shown in FIG. The drive stop delay circuit 30 includes logic circuits 31 and 33 having two inputs and one output, a logical sum element 34 having two inputs and one output, and a delay circuit 35.

  The logic circuit 31 outputs the H level when the high side logic signal Hin is at the H level and the overcurrent detection signal dc is at the L level. The logic circuit 33 outputs the H level when the high side logic signal Hin is at the H level and the overcurrent detection signal dc is at the H level. The OR element 34 outputs an H level when at least one input has an H level, and outputs an L level when both inputs are at the L level.

The connection relationship between the circuits is described. The input terminal a1 of the logic circuit 31 is connected to the input terminal c1 of the logic circuit 33, and the high-side logic signal Hin is input to the input terminal a1.
The input terminal a3 of the logic circuit 31 is connected to the input terminal c3 of the logic circuit 33, and the overcurrent detection signal dc is input to the input terminal a3.

  The output terminal a0 of the logic circuit 31 is connected to the input terminal d1 of the OR element 34. The output terminal c0 of the logic circuit 33 is connected to the input terminal e1 of the delay circuit 35, and the output terminal e0 of the delay circuit 35 is connected to the input terminal d3 of the OR element 34. The output terminal d0 of the OR element 34 is connected to the input terminals of the U-phase / V-phase / W-phase driver circuits.

  Here, the delay circuit 35 delays the pulse signal output from the logic circuit 33 by a predetermined time and outputs the delayed pulse signal. The delay circuit 35 has, for example, a configuration in which inverter elements are connected in multiple stages, and a time constant circuit using a capacitor and a resistor.

  By setting a delay time, the drive stop delay circuit 30 delays (extends) the ON state of the IGBT until the value of the collector current flowing through the IGBT at the time of short circuit decreases to the value of the maximum allowable current that does not cause avalanche breakdown. The IGBT is turned off when the value of the maximum allowable current is reached.

  Therefore, the delay time set by the delay circuit 35 is at least the time (for example, 30 to 40 μs) from the time when the collector current starts flowing through the IGBT to the time when the collector current reaches the value of the maximum allowable current. .

<Input / output characteristics of drive stop delay circuit>
FIG. 9 is a diagram showing input / output characteristics of the drive stop delay circuit. Table 4 shows the input / output characteristics of the drive stop delay circuit 30, and has items such as input, output (output of the drive stop delay circuit 30), and output state. The input is divided into a high side logic signal Hin and an overcurrent detection signal dc.

  When the high side logic signal Hin is H, the high side IGBT is on, and when the high side logic signal Hin is L, the high side IGBT is off. Further, when the overcurrent detection signal dc is H, it indicates that there is a short circuit between the output phases (overcurrent detection), and when the overcurrent detection signal dc is L, there is no short circuit between the output phases.

  Here, when (high side logic signal Hin, overcurrent detection signal dc) = (H, H), the output of drive stop delay circuit 30 shifts from H level to L level, and delay circuit 35 operates. A state in which a predetermined delay time is set for the output of the drive stop delay circuit 30 is established. When (high-side logic signal Hin, overcurrent detection signal dc) = (H, L), the output state of high-side logic signal Hin is set, and the output of drive stop delay circuit 30 at this time goes to H level. .

  When (high-side logic signal Hin, overcurrent detection signal dc) = (L, H), the output state of high-side logic signal Hin is set, and the output of drive stop delay circuit 30 at this time goes to L level. When (high-side logic signal Hin, overcurrent detection signal dc) = (L, L), the output state of high-side logic signal Hin is set, and the output of drive stop delay circuit 30 at this time goes to L level. .

<Operation time chart>
Next, the operation will be described using a time chart. It should be noted that a time chart of the conventional device (power semiconductor module 100) and a time chart of the device of the present invention are shown together so that the operation of the present invention can be easily understood.

FIG. 10 is a diagram showing an operation time chart of the conventional device. Each waveform of the high side logic signal Hin, the overcurrent detection signal dc, and the current (for example, U-phase current) is shown.
[Time t1] A short circuit between output phases occurs. The high-side logic signal Hin goes high, turning on the target high-side IGBT.

  [Time t2] An overcurrent is detected due to the occurrence of a short circuit between the output phases, and the overcurrent detection signal dc transitions from the L level to the H level (overcurrent detection at H). Then, when the overcurrent state is detected, the low-side IGBT is turned off.

[Period Ta] A period in which the short-circuit current flows and the short-circuit current increases (for example, corresponds to the flow of the short-circuit current in FIG. 15).
[Time t3] The high-side logic signal Hin goes low, turning off the high-side IGBT.

  [Period Tb] When the high-side IGBT is turned off, the short-circuit current flowing through the high-side IGBT is cut off, but the high-side IGBT is short-circuited due to avalanche breakdown, and the short-circuit current flows again This is the reflux period.

  FIG. 11 is a diagram showing an operation time chart of the present invention. Each waveform of the high side logic signal Hin, the overcurrent detection signal dc, the output of the drive stop delay circuit 30 and the current (for example, U-phase current) is shown.

  [Time t11] An output phase short circuit occurs. The high-side logic signal Hin goes high, turning on the target high-side IGBT. Further, the output of the drive stop delay circuit 30 becomes H level.

  [Time t12] An overcurrent is detected due to the occurrence of a short circuit between the output phases, and the overcurrent detection signal dc changes from the L level to the H level. Then, when the overcurrent state is detected, the low-side IGBT is turned off.

[Period Ta1] A period in which the short-circuit current flows and the short-circuit current increases (for example, corresponds to the flow of the short-circuit current in the case of FIG. 15).
[Time t13] The high side logic signal Hin becomes L level.

  [Period Tb1] The delay time of the high-side IGBT is delayed by the delay function of the drive stop delay circuit 30 (because the output of the drive stop delay circuit 30 becomes a substantial drive signal), and the high-side IGBT is avalanche. This is a high-side reflux period in which the short-circuit current is cut off without breaking. Note that the period of τ in FIG. 11 is the delay time.

  Here, the high-side reflux period Tb1 shown in FIG. 11 is longer than the high-side reflux period Tb shown in FIG. 10 due to the delay function of the drive stop delay circuit 30. Therefore, the short-circuit current flowing through the high-side IGBT is reduced, and di / dt after the regenerative operation immediately after turning off is reduced. Therefore, a surge voltage generated by the wiring inductance and di / dt during the regenerative operation can be suppressed, and IGBT destruction can be prevented.

  As described above, the embodiment has been exemplified, but the configuration of each unit described in the embodiment can be replaced with another having the same function. Further, other arbitrary components and steps may be added. Further, in the above description, the logic signal is described as positive logic, but it goes without saying that the logic signal may be configured as negative logic.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 1a Power semiconductor element sw1, sw2 High-side switch element sw11, sw12 Low-side switch element 3a, 3b Wiring 1b Control circuit 1b1 Current detection circuit 1b3 High-side control circuit s0 Short-circuit location Hin high-side logic signal dc Overcurrent detection signal M load

Claims (5)

A plurality of high-side switch elements arranged in a multi-phase and a plurality of low-side elements arranged in a multi-phase are connected in series to each phase, respectively, and each connection point between the high-side switch element and the low-side switch element A power semiconductor element for supplying power to the load from the
A current detection circuit for detecting a value of a current flowing through the power semiconductor element;
A drive control circuit including a high-side control circuit that controls on-off driving of each of the plurality of high-side switch elements and a low-side control circuit that controls on-off driving of each of the plurality of low-side switch elements,
With
The semiconductor device, wherein, when the current detection circuit detects a current value exceeding a reference value, the high-side control circuit delays a time until the high-side switch element during on-drive is turned off. . The power semiconductor element,
The high-side switch element includes a high-side U-phase switch, a high-side V-phase switch, and a high-side W-phase switch. The low-side switch element includes a low-side U-phase switch, a low-side V-phase switch, and a low-side W-phase switch. And
A U-phase line connected to a connection point between the emitter of the high-side U-phase switch and the collector of the low-side U-phase switch; and a V-phase line connected to a connection point between the emitter of the high-side V-phase switch and the collector of the low-side V-phase switch. The semiconductor device according to claim 1, wherein power is supplied to the load from a line and a W-phase line connected to a connection point between an emitter of the high-side W-phase switch and a collector of the low-side W-phase switch. The current detection circuit,
A short circuit when at least one of a short circuit between the U phase line and the V phase line, a short circuit between the V phase line and the W phase line, and a short circuit between the U phase line and the W phase line occurs The semiconductor device according to claim 2, wherein a current is detected. The drive control circuit includes:
A high-side U-phase control circuit that delays the time until the high-side U-phase switch through which the short-circuit current flows when the U-phase line and the V-phase line are short-circuited from on to off,
A high-side V-phase control circuit that delays a time required to transition from on to off with respect to the high-side V-phase switch through which the short-circuit current flows when the V-phase line and the W-phase line are short-circuited;
A high-side W-phase control circuit that delays the time from when the W-phase line and the U-phase line are short-circuited to the high-side W-phase switch when the short-circuit current flows, to transition from on to off,
The semiconductor device according to claim 3, further comprising: The drive control circuit includes:
A high-side U-phase control circuit that delays the time from when the U-phase line and the W-phase line are short-circuited to the high-side U-phase switch, in which the short-circuit current flows, to transition from on to off,
A high-side W-phase control circuit that delays a time required to transition from on to off with respect to the high-side W-phase switch through which the short-circuit current flows when the W-phase line and the V-phase line are short-circuited;
A high-side V-phase control circuit that delays a time required to transition from on to off with respect to the high-side V-phase switch through which the short-circuit current flows when the V-phase line and the U-phase line are short-circuited;
The semiconductor device according to claim 3, further comprising:

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