JP2008118834A - Surge reduction circuit and inverter device equipped with surge reduction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a surge voltage generated when turning off switching elements due to an overcurrent, in a power supply unit having a plurality of switching elements. <P>SOLUTION: A control device 40 generates upper arm control signals for controlling upper arm switching elements 11, 21, 31 and lower arm control signals for controlling lower arm switching elements 12, 22, 32. An interrupt signal generation circuit 50 generates an upper arm interrupt signal and a lower arm interrupt signal when the overcurrent is detected. The upper arm interrupt signal is obtained by delaying the lower arm interrupt signal with a delay circuit 52. A lower arm interrupt circuit 70 interrupts the lower arm control signals when the lower arm interrupt signal is inputted, while an upper arm interrupt circuit 60 interrupts the upper arm control signals when the upper arm interrupt signal is inputted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a surge reduction circuit that reduces a surge generated due to switching, and an inverter device including such a surge reduction circuit.

  In general, an inverter device includes a plurality of switching elements, and can control each switching element to generate alternating current with a desired frequency. For example, when power is supplied to the motor, the switching element is controlled so as to generate the required rotation speed or torque.

  By the way, when the switching element is turned off, a surge voltage is generated as is well known. The magnitude of this surge voltage depends on the inductance component of the bus (DC power supply line) and the current flowing through the bus at the time of turn-off. That is, the magnitude of the surge voltage can be estimated in advance. The breakdown voltage of each switching element is determined in consideration of such a surge voltage.

  However, a large surge voltage may occur depending on the switching timing. That is, for example, when a plurality of switching elements are turned off at the same time, a surge voltage due to them is added to generate a large surge voltage. Therefore, in order to protect the circuit elements (mainly switching elements) of the inverter device from such a large surge voltage, it is necessary to increase the breakdown voltage of each switching element. However, a switching element with a high breakdown voltage is generally expensive.

As a configuration for solving this problem, a power supply device having a function of constantly monitoring the turn-off timing of each switching element and shifting the turn-off timing of any of the switching elements when the turn-off timings of a plurality of switching elements coincide with each other Has been proposed. According to this configuration, since a plurality of surge voltages are not generated at the same time, generation of a large surge voltage can be suppressed. (For example, Patent Document 1)
JP 2004-194449 A

  By the way, when the load is short-circuited, a large current (overcurrent) may be generated and the switching element may be broken. For this reason, there has been proposed an inverter device provided with a protection circuit for stopping all currents by turning off all switching elements when a large current is detected. However, if the switching element is stopped in a state where a large current is generated, a large surge voltage is generated, and this surge voltage may cause a failure of the switching element. Note that the protection function described in Patent Document 1 is to reduce the surge voltage during steady operation, and cannot be applied during abnormal operation where high-speed response is required.

  An object of the present invention is to reduce a surge voltage generated when a switching element is stopped due to an overcurrent in a power supply device including a plurality of switching elements.

  The surge reduction circuit of the present invention is used in a power supply device including a switch circuit including an upper arm switch and a lower arm switch connected in series with each other, and when an overcurrent is detected in the power supply device. In addition, a cut-off signal generation circuit for outputting an upper arm cut-off signal and a lower arm cut-off signal with a timing shifted from each other by a predetermined time, and a control signal to be supplied to the upper arm switch when the upper arm cut-off signal is input An upper arm cutoff circuit; and a lower arm cutoff circuit that shuts off a control signal to be supplied to the lower arm switch when the lower arm cutoff signal is input.

  According to the above invention, when an overcurrent is detected, first, one of the upper arm switch or the lower arm switch is stopped, and the other of the upper arm switch or the lower arm switch is stopped after a predetermined time has elapsed. Therefore, the surge voltage generated due to the turn-off (cutoff) of the upper arm switch and the surge voltage generated due to the turn-off of the lower arm switch do not overlap, and a large surge voltage is avoided.

  In the above invention, the cutoff signal generation circuit may include a delay circuit that generates the upper arm cutoff signal by delaying the lower arm cutoff signal by a predetermined time. According to this configuration, the lower arm switch can be reliably stopped before the upper arm switch. Instead of delaying the lower arm cutoff signal by a predetermined time to generate the upper arm cutoff signal, the cutoff signal generating circuit delays the upper arm cutoff signal by a predetermined time to generate the lower arm cutoff signal. You may make it do.

  The predetermined time is preferably longer than the time during which a surge voltage is generated when the upper arm switch is shut off or the lower arm switch is turned off. By setting in this way, it is possible to reliably avoid the surge voltage from overlapping.

  An inverter device according to the present invention includes a power conversion unit including a switch circuit including an upper arm switch and a lower arm switch connected in series to each other, and a control signal generation unit that generates a control signal for controlling each switch. Detecting means for detecting a current flowing through the switch circuit; and an upper arm cutoff signal and a lower arm cutoff signal that are shifted in timing by a predetermined time when the current detected by the detection means exceeds a threshold value A cut-off signal generating circuit for outputting a signal, an upper arm cut-off circuit for cutting off a control signal to be supplied to the upper arm switch when the upper arm cut-off signal is input, and a lower arm when the lower arm cut-off signal is input A lower arm cut-off circuit for cutting off a control signal to be supplied to the switch; According to the present invention, an inverter device having a function of reducing a surge voltage is realized.

  ADVANTAGE OF THE INVENTION According to this invention, in a power supply device provided with a some switching element, the surge voltage which generate | occur | produces when stopping a switching element due to an overcurrent can be reduced.

  FIG. 1 is a diagram illustrating a configuration of an inverter device according to an embodiment of the present invention. In this embodiment, the inverter device 1 according to the embodiment generates a three-phase alternating current from a direct-current voltage input from the battery 101 and supplies the three-phase alternating current to the motor 102. The inverter device 1 includes an input capacitor C.

  The power conversion unit of the inverter device 1 includes a U-phase switch circuit 10, a V-phase switch circuit 20, and a W-phase switch circuit 30. Each of the switch circuits 10, 20, and 30 includes an upper arm switch and a lower arm switch connected in series with each other. That is, the U-phase switch circuit 10 includes switching elements 11 and 12, the V-phase switch circuit 20 includes switching elements 21 and 22, and the W-phase switch circuit 30 includes switching elements 31 and 32. Each switching element is, for example, a transistor such as a MOS transistor or an IGBT. A diode is connected to each switching element.

  The current sensors (detection means) 13, 23, and 33 detect currents that flow through the corresponding switch circuits 10, 20, and 30, respectively. These current sensors are not particularly limited, but may be, for example, shunt resistors or non-contact type sensors that measure magnetic flux.

  The control unit (control signal generating means) 40 generates a control signal for controlling the switching elements 11, 12, 21, 22, 31, 32. These control signals are generated, for example, so that the number of rotations of the motor 102 is set to a desired value, or a desired torque is generated in the motor 102. Each control signal for controlling the upper arm switching elements 11, 21, 31 is guided to the control terminal of the corresponding element via the upper arm cutoff circuit 70. In addition, each control signal for controlling the lower arm switching elements 12, 22, 32 is led to the control terminal of the corresponding element via the lower arm cutoff circuit 60. As will be described later in detail, the cutoff circuits 60 and 70 pass these control signals as they are during normal operation.

  The inverter device 1 having the above configuration has a function (surge reduction circuit) for reducing a surge voltage. The surge reduction circuit includes a cutoff signal generation circuit 50, a lower arm cutoff circuit 60, and an upper arm cutoff circuit 70.

  The cutoff signal generation circuit 50 includes an overcurrent detection circuit 51 and a delay circuit 52. The overcurrent detection circuit 51 constantly monitors the output signals of the current sensors 13, 23, and 33, and when a current exceeding a threshold is detected in one or more of the current sensors, the lower arm cutoff signal Is output. The lower arm cutoff signal is given to the lower arm cutoff circuit 60. Further, the delay circuit 52 generates the upper arm cutoff signal by delaying the lower arm cutoff signal by a predetermined time. The upper arm cutoff signal is given to the upper arm cutoff circuit 70.

  The lower arm cutoff circuit 60 includes three gate circuits (AND gates in this embodiment). Each gate circuit passes the control signal output from the control unit 40 as it is when the inverter device 1 is operating normally. On the other hand, when an overcurrent occurs and a lower arm cutoff signal is given from the cutoff signal generation circuit 50 to the lower arm cutoff circuit 60, each gate circuit cuts off the control signal output from the control unit 40. Then, the lower arm switching elements 12, 22, and 32 are controlled to be in an off state.

  The configuration and operation of the upper arm cutoff circuit 70 are basically the same as those of the lower arm cutoff circuit 60. That is, when the inverter device 1 is operating normally, the control signal output from the control unit 40 is passed as it is. Then, when an overcurrent occurs and the upper arm cutoff signal is given from the cutoff signal generation circuit 50, the control signal output from the control unit 40 is cut off. Then, the upper arm switching elements 11, 21, and 31 are controlled to the off state.

  In the inverter device 1 configured as described above, the overcurrent detection circuit 51 is realized by a comparator, for example. In this embodiment, the overcurrent detection circuit 51 outputs “H” if the detected current is less than or equal to the threshold, and outputs “L” if the detected current exceeds the threshold.

  The delay circuit 52 is realized by, for example, the circuit shown in FIG. In the circuit shown in FIG. 2, if the input signal is “H”, the switch M1 is in the ON state, and the charge of the capacitor C1 is discharged through the switch M1, so that the potential at the − terminal of the comparator 53 is zero. It becomes a state close to. Therefore, in this case, the output of the comparator 53 is also “H”. Subsequently, when the input signal is switched from “H” to “L”, the capacitor C1 is charged by the current flowing through the resistor R1. When the voltage across the capacitor C1 rises and the potential of the negative terminal of the comparator 53 exceeds the potential of the positive terminal, the output of the comparator 53 is also switched from “H” to “L”. Thus, the delay circuit 52 delays the input signal and outputs it. At this time, the delay time is determined by the resistance value of the resistor R1 and the capacitance of the capacitor C1.

  Next, the operation of the inverter device 1 when an overcurrent occurs will be described with reference to FIG. Here, it is assumed that an overcurrent occurs when the load is short-circuited (in FIG. 1, the V phase / W phase of the motor 102 is short-circuited).

  In FIG. 3, the “upper arm control signal” schematically shows three control signals given to the control terminals of the upper arm switching elements 11, 21, and 31. Similarly, “lower arm control signal” schematically shows three control signals given to the control terminals of the lower arm switching elements 12, 22, and 32. In addition, “current” schematically indicates a current detected by the current sensors 13, 23, and 33 (here, a current detected by the current sensor 33).

  When the inverter device 1 is operating normally, the detected current is smaller than the threshold value, and both the upper arm cutoff signal and the lower arm cutoff signal hold “H”. Therefore, the control signal generated by the control unit 40 is given to the corresponding switching element as it is.

  It is assumed that the load is short-circuited (here, the V phase / W phase of the motor 102 is short-circuited) at time T1. Then, the current flowing from the positive electrode of the battery 101 to the negative electrode of the battery 101 via the upper arm switching element 21, the motor 102, and the lower arm switching element 32 increases rapidly. This current is detected by the current sensor 33. And when this electric current exceeds a threshold value, a lower arm interruption | blocking signal will switch from "H" to "L". Note that the upper arm cutoff signal remains “H”.

  When the lower arm cut-off signal becomes “L”, the lower arm control signal is cut off by the lower arm cut-off circuit 60 thereafter. As a result, the lower arm switching elements 12, 22, and 32 are controlled to the off state. At this time, since a large current flowing through the bus line decreases, a surge voltage is generated.

  When the time ΔT elapses from when the lower arm cutoff signal is switched from “H” to “L”, the upper arm cutoff signal is switched from “H” to “L” at time T2. Then, the upper arm control signal is cut off by the upper arm cut-off circuit 70, and the upper arm switching elements 11, 21, and 31 are controlled to be turned off. As a result, a surge voltage is generated again. The time ΔT is a delay time by the delay circuit 52, and is set to be longer than the time when the surge voltage is assumed to exist. However, if the time ΔT is excessively long, the period during which the control signal is given only to the upper arm switching elements 11, 21, and 31 becomes long, so that the operation of the inverter device 1 may become unstable. Therefore, it is preferable to appropriately set the time ΔT according to the time when the surge voltage is assumed to exist. Here, “the time when the surge voltage is assumed to exist” depends on the circuit configuration and can be obtained in advance by simulation or the like.

  As described above, in the inverter device 1 of the embodiment, when an overcurrent occurs, the current is reduced by cutting off the control signal for controlling the switching element. At this time, the upper arm cutoff signal is delayed by a predetermined time with respect to the lower arm cutoff signal. For this reason, the surge voltage generated due to the turn-off of the upper arm switching elements 11, 21, 31 and the surge voltage generated due to the turn-off of the lower arm switching elements 12, 22, 32 do not occur simultaneously. That is, these surge voltages are not added. Therefore, generation of a large surge voltage is avoided.

  In addition, the structure which interrupts | blocks a lower arm ahead of an upper arm at the time of an overcurrent of an inverter apparatus is also described in Unexamined-Japanese-Patent No. 8-223934 (henceforth, patent document 2). In the inverter device described in Patent Document 2, two threshold values are set to monitor overcurrent. When the current flowing through the inverter device exceeds the first threshold value, the lower arm switch is stopped, and the current is The upper arm switch is stopped when a second threshold value higher than the first threshold value is exceeded.

  However, in the configuration described in Patent Document 2, when the current flowing through the inverter device is larger than the first threshold value and less than or equal to the second threshold value, the upper arm switch does not stop. May become unstable. On the other hand, in the inverter device 1 of the embodiment, since all the switching elements are surely stopped when an overcurrent occurs, an unstable operation state does not continue.

  In addition, in the configuration described in Patent Document 2, when the current increases rapidly due to a load short circuit or the like, the time required for the current to exceed the second threshold after exceeding the first threshold is extremely short. The upper arm switch and the lower arm switch are turned off almost simultaneously. In this case, the surge voltage caused by the turn-off of the upper arm switch and the surge voltage caused by the turn-off of the lower arm switch are overlapped to generate a large surge voltage. On the other hand, in the inverter device 1 of the embodiment, even when the current suddenly increases due to a load short circuit or the like, the turn-off timing of the upper arm and the lower arm is shifted by the delay circuit 52. The surge voltage generated due to the turn-off of the arm switching element and the surge voltage generated due to the turn-off of the lower arm switching element do not overlap, and no large surge voltage is generated.

  In the above-described embodiment, the configuration in which the upper arm switching element is stopped after stopping the lower arm switching element has been described. However, the structure in which the lower arm switching element is stopped after the upper arm switching element is stopped may be employed. . That is, the delay circuit 52 may be configured to generate the lower arm cutoff signal by delaying the upper arm cutoff signal by a predetermined time. Thus, the same effect can be obtained by delaying the lower arm cutoff signal by a predetermined time with respect to the upper arm cutoff signal.

  In the above-described embodiment, the current sensors 13, 23, and 33 are configured to detect U-phase, V-phase, and W-phase currents respectively, but the current sensor 81 is used to detect the total current of the inverter device 1. It may be configured to.

  In the above-described embodiment, the power conversion unit includes a U-phase, V-phase, and W-phase three-phase switch circuit, but is not limited to three-phase, and includes, for example, a two-phase or four-phase switch circuit It may be a configuration.

  Furthermore, the present invention is not only applied to the inverter device, but can be applied to a power supply device including a switch circuit including an upper arm switch and a lower arm switch connected in series to each other.

It is a figure which shows the structure of the inverter apparatus of embodiment of this invention. It is an Example of a delay circuit. It is a timing chart explaining operation at the time of overcurrent occurrence.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Inverter apparatus 10 U-phase switch circuit 20 V-phase switch circuit 30 W-phase switch circuit 11, 21, 31 Upper arm switching element 12, 22, 32 Lower arm switching element 13, 23, 33 Current sensor 40 Control part 50 Breaking signal production | generation Circuit 51 Overcurrent detection circuit 52 Delay circuit 53 Comparator 60 Lower arm cutoff circuit 70 Upper arm cutoff circuit 81 Current sensor

Claims (6)

A surge reduction circuit for reducing a surge voltage in a power supply device including a switch circuit including an upper arm switch and a lower arm switch connected in series with each other,
A shut-off signal generating circuit that outputs an upper arm shut-off signal and a lower arm shut-off signal by shifting the timing by a predetermined time when an overcurrent is detected in the power supply device;
An upper arm cutoff circuit that cuts off a control signal to be given to the upper arm switch when the upper arm cutoff signal is input;
A lower arm cutoff circuit that shuts off a control signal to be applied to the lower arm switch when the lower arm cutoff signal is input;
A surge reduction circuit. The surge reduction circuit according to claim 1, wherein the cutoff signal generation circuit includes a delay circuit that delays the lower arm cutoff signal by a predetermined time to generate the upper arm cutoff signal. The surge reduction circuit according to claim 1, wherein the cutoff signal generation circuit includes a delay circuit that delays the upper arm cutoff signal by a predetermined time to generate the lower arm cutoff signal. 4. The surge according to claim 2, wherein the predetermined time is a time longer than a time in which a surge voltage generated by the upper arm switch being cut off or the lower arm switch being cut off is present. Reduction circuit. A power converter having a switch circuit including an upper arm switch and a lower arm switch connected in series with each other;
Control signal generating means for generating a control signal for controlling each switch;
Detecting means for detecting a current flowing through the switch circuit;
An interruption signal generation circuit that outputs an upper arm interruption signal and a lower arm interruption signal that are shifted in timing by a predetermined time when the current detected by the detection means exceeds a threshold;
An upper arm cutoff circuit that cuts off a control signal to be given to the upper arm switch when the upper arm cutoff signal is input;
A lower arm cutoff circuit that shuts off a control signal to be applied to the lower arm switch when the lower arm cutoff signal is input;
An inverter device having The inverter device according to claim 5, wherein the predetermined time is a time longer than a time during which a surge voltage generated when the upper arm switch is shut off or the lower arm switch is shut off.

Images