JP2013093992A - Inverter control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the technology which, while protecting a lower arm side switch from an overcurrent, avoids regeneration from a voltage inverter to a DC bus bar.SOLUTION: The timing with which a converter commutates is when a carrier C1 takes on a value drt. A carrier C3 comes in the same form as the carrier C1 and is 180 degrees out of phase with it. Switching of an inverter takes place when the carrier C3 assumes a signal waveform dst+drt(d7+d6+d4), dst+drt(1-d4), dst+drt×(1-d4-d6), dst(1-d7-d6-d4), dst×d4, or dst(d4+d6). These signal waveforms can be properly set, so that even when this switching takes place, any one of upper arm side switches conducts a current. Therefore, even when all of lower arm switches are turned off at any point of time, a reflux operation occurs in the inverter, whereby regeneration is avoided.

Description

  The present invention relates to a technique for controlling an inverter, particularly a voltage source inverter.

  FIG. 1 is a circuit diagram illustrating the configuration of a power converter that employs a voltage source inverter 4. The voltage source inverter 4 includes three current paths connected in parallel between the DC buses LH and LL to which the DC voltage Vdc is applied. The DC bus LH has a higher potential than the DC bus LL.

  The first current path has a connection point Pu, an upper arm side switch Qup, and a lower arm side switch Qun. The second current path has a connection point Pv, an upper arm side switch Qvp, and a lower arm side switch Qvn. The third current path has a connection point Pw, an upper arm side switch Qwp, and a lower arm side switch Qwn.

  The upper arm switches Qup, Qvp, and Qwp flow current from the DC bus LH to the connection points Pu, Pv, and Pw, respectively, when conducting. The lower arm side switches Qun, Qvn, Qwn flow current from the connection points Pu, Pv, Pw to the DC bus LL when conducting. Three-phase voltages Vu, Vv, Vw are applied to the three-phase load 5 from the connection points Pu, Pv, Pw.

  Upper arm side diodes Dup, Dvp, Dwp are connected in antiparallel to the upper arm side switches Qup, Qvp, Qwp, respectively. Lower arm side diodes Dun, Dvn, Dwn are connected in antiparallel to the lower arm side switches Qun, Qvn, Qwn, respectively. Note that “reverse parallel” refers to a mode in which two elements are connected in parallel and the conduction directions of the two elements are opposite to each other.

  For protection, the voltage source inverter 4 performs a specific operation (hereinafter referred to as “overcurrent protection operation”) when the current flowing through the voltage inverter 4 exceeds a threshold value. Specifically, the current is a link current Idc flowing through the DC bus LH and the DC bus LL. Here, the link current Idc is detected as a voltage drop CIN in the shunt resistor 3 provided in the DC bus LL. When the voltage drop CIN exceeds the threshold, the current flowing through the voltage source inverter 4 is detected as an overcurrent, and an overcurrent protection operation is executed. Specifically, in the overcurrent protection operation, all of the lower arm switches Qun, Qvn, and Qwn are turned off to protect them from overcurrent. However, even if an overcurrent is detected and the lower arm switches Qun, Qvn, Qwn are all turned off, the operation of the upper arm switches Qup, Qvp, Qwp is not changed.

  Such an overcurrent protection operation is introduced, for example, in Non-Patent Document 2 described later. In FIG. 1, following the non-patent document 2, the voltage drop CIN is not a voltage drop itself in the shunt resistor 3 but a low-pass transmission filtering is performed on the voltage drop by the filter 9. Such filtering is advantageous in that it does not generate overcurrent protection even if the voltage drop CIN exceeds a threshold in an extremely short period.

  Patent documents and non-patent documents disclosing techniques related to the present application are listed below. In Non-Patent Document 1 and Patent Document 1, a modified triangular wave is employed as a carrier, and in Patent Document 2 and Patent Document 3, a symmetrical triangular wave is employed. In Patent Document 2, the control of the inverter is synchronized with the control of the converter by changing the carrier cycle. In Patent Document 3, the amplitude of the signal wave is variable.

JP 2004-222337 A JP 2004-266972 A Japanese Patent No. 4135026 JP 2009-213252 A

L.wei, T.A.Lipo, "A Novel Matrix converter Topology with Simple Commutation", IEEE ISA2001, vol3, pp1749-1754, 2001 Mitsubishi Electric Corporation “DIPIPM Ver.3 Application Note” (August 2009)

  The upper arm switches Qup, Qvp, Qwp and the lower arm switches Qun, Qvn, Qwn are switched in various patterns in order to control the instantaneous amplitude in the three-phase voltages Vu, Vv, Vw output from the voltage source inverter 4. The The pattern is determined by a so-called unit voltage vector Vj (j = 0, 1, 2, 3, 4, 5, 6, 7), and the amplitude and phase of the three-phase voltages Vu, Vv, Vw are determined by a combination of these patterns. Be controlled.

  In particular, a voltage vector commonly referred to as a zero voltage vector is adopted as a pattern that substantially matches the three-phase voltages Vu, Vv, and Vw.

  As introduced in Non-Patent Document 1 and Patent Document 1, the zero voltage vector V0 in which all the lower arm switches Qun, Qvn, Qwn are conducted is always employed as the zero voltage vector. At this time, the upper arm switches Qup, Qvp, and Qwp are all non-conductive to avoid a short circuit that does not pass through the three-phase load 5 between the DC buses LH and LL.

  In the state where the zero voltage vector V0 is adopted and the lower arm side switches Qun, Qvn, Qwn are conducting, current can flow from the connection points Pu, Pv, Pw to the DC bus LL, and the lower arm side Current can also flow from the DC bus LL to the connection points Pu, Pv, Pw via the diodes Dun, Dvn, Dwn. Therefore, in this state, the current flowing between the three-phase load 5 and the voltage source inverter 4 circulates through the lower arm side switches Qun, Qvn, Qwn and the lower arm side diodes Dun, Dvn, Dwn. No overcurrent is detected by the drop CIN.

  However, as described above, the overcurrent protection operation forcibly turns off only the lower arm switches Qun, Qvn, and Qwn, but does not change the operation of the upper arm switches Qup, Qvp, and Qwp. Therefore, during the overcurrent protection operation, when the voltage source inverter 4 operates based on the zero voltage vector V0 in which the lower arm side switches Qun, Qvn, Qwn are nonconductive, all the switches of the voltage source inverter 4 are nonconductive. Become. At this time, since the voltage source inverter 4 functions as a diode bridge, the back electromotive force generated by the three-phase load 5 is regenerated to the DC bus. In order to cope with such regenerative energy, there arises a problem that the capacity of the clamp circuit 8 provided between the DC buses LH and LL is increased.

  Therefore, an object of the present invention is to provide a technique for avoiding regeneration from the voltage source inverter to the DC bus while protecting the lower arm side switch from overcurrent in the voltage source inverter.

  The inverter control device according to the present invention is a device that controls a voltage source inverter (4) that converts a DC voltage (Vdc) into a three-phase AC voltage (Vu, Vv, Vw).

  The voltage source inverter (4) includes three current paths connected in parallel to each other between the first and second DC buses (LH, LL) to which the DC voltage is applied.

  The first DC bus (LH) has a higher potential than the second DC bus (LL).

  Each of the current paths includes a connection point (Pu, Pv, Pw), an upper arm side switch (Qup, Qvp, Qwp), a lower arm side switch (Qun, Qvn, Qwn), and an upper arm side diode (Dup). , Dvp, Dwp) and lower arm side diodes (Dun, Dvn, Dwn).

  The upper arm side switch is connected between the first DC bus and the connection point, and is turned on / off in accordance with an upper arm side switching signal (Sup, Svp, Swp). A current is passed from the bus to the connection point.

  The lower arm side switch is connected between the connection point and the second DC bus, and is turned on / off according to a lower arm side switching signal (Sun, Svn, Swn). A current is passed through the second DC bus.

  The upper arm side diode is connected in antiparallel to each of the upper arm side switches. The lower arm side diode is connected in antiparallel to each of the lower arm side switches.

  A first aspect of an inverter control device according to the present invention includes an upper arm side switching signal generation unit (30), a protection signal generation device (11), and a lower arm side switching signal generation unit (12).

  The upper arm side switching signal generation unit generates the upper arm side switching signals (Sup, Svp, Swp) based on a comparison between the inverter signal wave and the inverter carriers (C2, C3).

  The protection signal generating device activates the protection signal (M) when a current flowing through the pair of DC buses exceeds a threshold value.

  The lower arm switching signal generator employs a signal complementary to the upper arm switching signal as the lower arm switching signal when the protection signal is inactive, and the upper arm when the protection signal is active. The lower arm side switching signal is deactivated without depending on the side switching signal.

  The upper arm side switching signal generation unit always activates any one of the upper arm side switching signals when the voltage source inverter is driven.

  The second aspect of the inverter control device according to the present invention is the first aspect, in which all the connection points (Pu, Pv, Pw) are connected to each other by the voltage source inverter (4). All the upper arm side switching signals (Sup, Svp, Swp) are activated, and all the lower arm side switching signals (Sun, Svn, Swn) are deactivated.

  A third aspect of the inverter control device according to the present invention is the first aspect, wherein there is a multiphase between the first DC bus (LH) and the second DC bus (LL). A current source converter (2) for converting an AC voltage (Vr, Vs, Vt) into the DC voltage (Vdc) is connected.

  At least when switching for commutation occurs in the current converter, all the upper arm side switching signals (Sup, Svp, Swp) are activated and all the lower arm side switching signals (Sun, Svn). , Swn) is deactivated.

  A fourth aspect of the inverter control device according to the present invention is the third aspect thereof, wherein in the current source converter (2), the commutation takes one cycle (T0) of the converter carrier (C1). It occurs at the timing divided into one period (dst · T0) and second period (drt · T0).

  The upper arm side switching signal (Sup) corresponding to the upper arm side switch (Qup) provided in the first current path corresponding to the maximum phase (Vu) of the three-phase AC voltage is the inverter carrier. Is activated when a value between the first inverter signal wave and the second inverter signal wave is taken.

  The upper arm side switching signal (Svp) corresponding to the upper arm side switch (Qvp) provided in the second current path corresponding to the intermediate phase (Vv) of the three-phase AC voltage is the inverter carrier. Is activated when taking a value between the third inverter signal wave and the fourth inverter signal wave.

  The upper arm side switching signal (Swp) corresponding to the upper arm side switch (Qwp) provided in the third current path corresponding to the minimum phase (Vw) of the three-phase AC voltage is the inverter carrier. Is activated when taking a value between the fifth inverter signal wave and the sixth inverter signal wave.

  The second inverter signal wave takes the value 1.

  The fourth inverter signal wave takes the value dbc + dac (1-dg1).

  The sixth inverter signal wave takes the value dbc + dac (1-dg1-dg2)].

  The first inverter signal wave takes a value of zero.

  The third inverter signal wave takes the value dbc · dg1.

  The fifth inverter signal wave takes the value dbc (dg1 + dg2).

  However, the ratio of the length of the first period to the second period is dac: dbc (where dbc = 1-dac), and only the upper arm side switch (Qup) provided in the first current path A first section (V4) in which only the two upper arm switches (Qup, Qvp) provided in the first and second current paths are conductive, The ratio of the length to the third section (V7) in which the three upper arm switches (Qup, Qvp, Qwp) provided in all the current paths are conducted is dg1: dg2: dg3 (where dg1 + dg2 + dg3 = 1) The inverter carrier exhibited a triangular wave, and its minimum and maximum values were 0 and 1, respectively. The inverter carrier takes the value dbc at the timing.

  According to the first aspect of the inverter control device of the present invention, when the overarm protection operation is performed by turning off the lower arm side switch when the current exceeds the threshold value, any one of the upper arm side switching is performed. Since one is always conducting, regeneration from the voltage source inverter to the DC bus is avoided.

  According to the second aspect of the inverter control device according to the present invention, even when the voltage source inverter is operating based on a so-called zero voltage vector, any one of the upper arm side switching is always conducted. Therefore, even if an overcurrent protection operation occurs in this state, regeneration is avoided.

  According to the third aspect of the inverter control device of the present invention, since no current flows through the DC bus in switching for commutation of the converter, loss in the converter is reduced.

  According to the fourth aspect of the inverter control device of the present invention, when switching for commutation occurs in the current source converter, all the upper arm switches are turned on.

It is a circuit diagram which shows an example of a notional structure of a direct form AC power converter device. It is a graph explaining the operation | movement in a current source converter. It is a graph which shows the conventional operation | movement of a direct AC power converter. It is a graph which shows the waveform of the signal wave about the carrier for voltage source inverters in the conventional operation. It is a graph which shows the operation | movement in the 1st example of this Embodiment of a direct form AC power converter device. It is a graph which shows the waveform of the signal wave about the carrier for voltage source inverters in the operation concerning the 1st example of this embodiment. It is a graph which shows the operation | movement in the 2nd example of this Embodiment of a direct form AC power converter device. It is a block diagram which shows the structure which controls the operation | movement concerning this Embodiment.

  FIG. 1 is a circuit diagram showing an example of a conceptual configuration of a direct AC power converter. Although there is a part already explained about the composition and it overlaps partially, it explains also below. Even if not described below, the contents already described for the configuration are valid in the following description. However, details of the control device 6 that performs the operation relating to this embodiment will be described later.

  The direct AC power converter illustrated here is an indirect matrix converter, and includes a current source converter 2 that performs AC / DC conversion and a voltage source inverter 4 that performs DC / AC conversion. Current source converter 2 and voltage source inverter 4 are connected by DC buses LH and LL.

  The current source converter 2 has three input terminals Pr, Ps, and Pt. The input terminals Pr, Ps, and Pt are connected to, for example, a three-phase AC power supply 1 and input three-phase AC voltages Vr, Vs, and Vt for each phase. The current source converter 2 commutates the line currents ir, is, it supplied from the input terminals Pr, Ps, Pt in a period divided into a first period and a second period, and between the DC buses LH, LL. Apply the link current Idc. Hereinafter, the line currents ir, is, it will be described with the direction from the input terminals Pr, Ps, Pt toward the voltage source inverter 4 being the positive direction.

  In the first period, among the input terminals Pr, Ps, and Pt, a pair of currents to which an alternating voltage that exhibits the maximum phase and an alternating voltage that exhibits the minimum phase are applied is a link current Idc between the DC buses LH and LL. It is a period to be supplied. Further, in the second period, a pair of currents to which an AC voltage exhibiting an intermediate phase and an AC voltage exhibiting a minimum phase are applied among the input terminals Pr, Ps, and Pt are linked currents Idc between the DC buses LH and LL. It is a period supplied as.

  The DC bus LH has a higher potential than the DC bus LL due to the difference in the link voltage Vdc, which is a DC voltage.

  The voltage source inverter 4 has connection points Pu, Pv and Pw. The voltage source inverter 4 switches the link voltage Vdc with a switching pattern based on pulse width modulation, and outputs multiphase AC to the connection points Pu, Pv, and Pw.

  The current source converter 2 includes switching elements Qxp, Qxn (where x represents r, s, t, and so on). The switching element Qxp is provided between the input terminal Px and the DC bus LH. The switching element Qxn is provided between the input terminal Px and the DC bus LL.

  The switching elements Qxp and Qxn both have reverse blocking capability, and these are illustrated as RB-IGBT (Reverse Blocking IGBT) in FIG. Alternatively, these switching elements can also be realized by connecting an insulated gate bipolar transistor (IGBT) and a diode in series.

  Switching signals Sxp and Sxn are input to the switching elements Qxp and Qxn, respectively. The switching element Qxp is turned on / off according to the activation / inactivation of the switching signal Sxp, and the switching element Qxn is turned on / off according to the activation / inactivation of the switching signal Sxn.

  Switching signals Syp and Syn are input to the switching elements Qyp and Qyn, respectively, where y represents u, v, and w (the same applies hereinafter). The switching element Qyp is turned on / off according to the activation / inactivation of the switching signal Syp, and the switching element Qyn is turned on / off according to the activation / inactivation of the switching signal Syn.

  A clamp circuit 8 is provided between the DC buses LH and LL. The clamp circuit 8 suppresses a voltage increase between the DC buses LH and LL caused by regenerative energy from the inverter 4.

  FIG. 2 is a graph for explaining the operation of the current source converter 2. The upper graph shows the three-phase AC voltages Vr, Vs, and Vt, and the lower graph shows the conduction ratios dr, ds, and dt, respectively.

  In FIG. 2, temporal regions R1 to R6 are added above the upper graph. The regions R1 to R6 are temporally separated from each other at the timing when the one having the largest absolute value among the three-phase AC voltages Vr, Vs, and Vt is switched. This switching timing is also a timing at which any of the three-phase AC voltages Vr, Vs, Vt takes zero. Since the regions R1 to R6 are divided in this way, each has a length of π / 3 obtained by dividing one period of the three-phase AC voltages Vr, Vs, and Vt into six equal parts. For example, the region R1 is a region where the absolute value of the AC voltage Vt is larger than the absolute value of any of the AC voltages Vr and Vs, and starts when the AC voltage Vs switches from negative to positive, and the AC voltage Vr changes from positive to negative. The time of switching will be the end.

  The three-phase AC voltages Vr, Vs, and Vt are expressed as a ratio with respect to the maximum value of the line voltage. Therefore, the maximum absolute value of the three-phase AC voltages Vr, Vs, and Vt is 1 / √3. . Here, the time point at which the three-phase AC voltage Vr takes the maximum value is adopted as the reference (0 °) for the phase angle of the three-phase AC voltage.

  The conduction ratio dx indicates the ratio of the time when the line current ix flows by switching of the switching elements Qxp and Qxn. If the current ratio dx is positive, the switching element Qxp is conductive and the ratio of the current flowing into the current source converter 2 to the input terminal Px. If it is negative, the switching element Qxn is conductive and the three-phase from the input terminal Px. The time ratio at which current flows to the AC power source 1 is shown. Specifically, for example, in the region R1, since the AC voltage Vt is the smallest, the switching element Qtn continues to conduct, and is expressed as dt = −1. In this case, the switching elements Qrp and Qsp are turned on alternately, and the ratio of the time when they are turned on is indicated by the flow ratios dr and ds. The switching elements Qrp and Qsp are turned on alternately in a short cycle with respect to one cycle of the three-phase AC voltages Vr, Vs, and Vt, and pulse width modulation is performed.

  As understood from FIG. 2, in the region R1, if the alternating voltage Vr is larger than the alternating voltage Vs, the conduction ratio dr is larger than the conduction ratio ds, and if the alternating voltage Vr is smaller than the alternating voltage Vs, the conduction ratio. dr is smaller than the flow ratio ds. Thus, it is desirable to make the current ratio of the line current corresponding to the AC voltage that is the maximum phase larger than the current ratio of the line current that is the intermediate phase in order to make the line current ix closer to a sine wave. Since the technique for determining the conduction ratio dx to make the line current ix sinusoidal is well known (for example, Non-Patent Document 1, Patent Documents 3 and 4, etc.), the specific contents of the technique are omitted here.

  Hereinafter, the description will be continued by taking the region R1 as an example. Since the flow ratio dt is fixed to the value −1 in the region R1, the flow ratios dr and ds in the region R1 are expressed as the flow ratios drt and dst, respectively. As for other regions R2 to R6, it is obvious that the following explanation is valid by reading the phase sequence and mutually reading the switching elements Qxp and Qxn because of the symmetry of the phase voltage waveform.

  FIG. 3 is a graph showing the conventional operation of the direct AC power converter. In order to switch the current source converter 2 in accordance with the current ratios drt and dst, a carrier C1 exhibiting a triangular wave that transitions between a minimum value 0 and a maximum value 1 is employed here. Since dst + drt = 1, the timing at which the carrier C1 becomes equal to the conduction ratio drt can be used as the timing at which the current source converter 2 commutates.

  When one cycle T0 of the carrier C1 is introduced, since the waveform of the carrier C1 is a triangular wave, the length of the period in which the carrier C1 is between the value 0 and the conduction ratio drt is drt · T0 (hereinafter, this period is referred to as “ The length of the period in which the carrier C1 is between the flow ratio drt and the value 1 is represented by dst · T0 (hereinafter, this period is also referred to as “period dst · T0”). The In each of the following drawings, a case where dst> drt is satisfied, that is, a case where the phase angle is large in the second half (phase angle 60 to 90 ° in FIG. 2) in the region R1 is illustrated. In this case, the alternating voltages Vr, Vs, and Vt are the intermediate phase, the maximum phase, and the minimum phase, respectively. The periods dst · T0 and drt · T0 can be grasped as the first period and the second period, respectively.

  In the period dst · T0, among the input terminals Pr, Ps, and Pt of the current source converter 2, the pair of input terminals Ps and Pt to which the AC voltage Vs that exhibits the maximum phase and the AC voltage Vt that exhibits the minimum phase are applied. The flowing current is supplied to the DC bus LH.

  During the period drt · T0, among the input terminals Pr, Ps, and Pt, the current flowing through the pair of the input terminals Pr and Pt to which the AC voltage Vr that exhibits the intermediate phase and the AC voltage Vt that exhibits the minimum phase are applied is DC. Supplied to bus LH. Since the generation of the switching signals Sxp and Sxn for realizing such commutation is known in, for example, Patent Document 3, the description thereof is omitted.

  In order to perform instantaneous space voltage vector modulation of the voltage source inverter 4, the carrier C2 is compared with the signal wave, and the switching signals Syp and Syn are generated based on the comparison result. A waveform having the same shape and the same phase as the carrier C1 is adopted as the carrier C2. In the following, for the sake of simplicity of explanation, the carriers C1 and C2 are taken as an example where the minimum value is 0 and the maximum value is 1. However, arbitrary values can be selected as the minimum value and the maximum value by appropriately performing linear conversion on the signal wave.

  It is assumed that a voltage vector to be adopted by the voltage source inverter 4 is represented by d4 · V4 + d6 · V6 by using vector calculation (d4 + d6 ≦ 1). Here, “unit voltage vector Vg” was introduced. However, in this notation, the value g is a value obtained by assigning the values 4, 2, and 1 to the U phase, V phase, and W phase, respectively, and adding up the assigned values when the corresponding upper arm is conductive. Then, an integer of 0 to 7 is taken.

  For example, the unit voltage vector V4 represents a switching pattern in which the switching elements Qup, Qvn, and Qwn are turned on and the switching elements Qun, Qvp, and Qwp are turned off. The unit voltage vector V6 represents a switching pattern in which the switching elements Qup, Qvp, and Qwn are turned on and the switching elements Qun, Qvn, and Qwp are turned off.

  In FIG. 3, a voltage vector representing a switching pattern to be adopted by the voltage source inverter 4 is represented by d4 · V4 + d6 · V6 by using vector calculation, and d0 + d7 = 1− (d4 + d6)> 0, d0> 0, d7> 0. The case where is established is illustrated. In such a case, the unit voltage vectors V0, V4, V6, and V7 are employed with the length of the ratio d0: d4: d6: (1-d0-d4-d6). In this case, switching is performed using unit voltage vectors V0, V4, V6, and V7 in a ratio of d0: d4: d6: (1-d0-d4-d6) in one cycle T0 of carrier C2. . Unlike the case of two-phase modulation shown in FIGS. 4 and 6 to be described later, FIG. 3 shows the case of three-phase modulation because d0> 0 and d7> 0.

  Thus, the ratio of the length in which each unit voltage vector is employed to one carrier cycle is also referred to as a time ratio. Here, d0 + d4 + d6 + d7 = 1.

  When the unit voltage vectors V0 and V7 are employed, no current flows through the voltage source inverter 4, so the link current Idc is zero. Therefore, if switching is performed so that the current source converter 2 commutates during a period in which the switching pattern corresponding to the unit voltage vector V0 is employed, so-called zero current switching is realized in which current does not flow through the switching element in the switching. The Zero current switching is desirable from the viewpoint of reducing the loss of the current source converter 2.

  Based on the above-mentioned viewpoint, it is known how to set the period in which the unit voltage vectors V0, V4, V6, V7 are adopted as the switching pattern in the voltage source inverter 4 (for example, Patent Document 3). Etc.), the specific content of the technology is omitted here.

  As a specific example, in FIG. 3, when the carrier C2 takes a signal wave drt (1-d0) or less or a signal wave (drt + dst · d0) or more, the switching signal Sup is activated, and the carrier C2 becomes the signal wave drt (1 −d0−d4) or lower or a signal wave (drt + dst (d0 + d4)) or higher, the switching signal Svp is activated, and the carrier C2 is equal to or lower than the signal wave drt (1−d0−d4−d6) or the signal wave (drt + dst (d0 + d4 + d6). )) The case where the switching signal Swp is activated when taking the above is illustrated. Note that the switching signals Sun, Svn, Swn are activated complementarily to the switching signals Sup, Svp, Swp, respectively, if the dead time is not taken into consideration due to the control characteristics of the voltage source inverter 4.

  Since the carrier C2 has the same shape and the same phase as the carrier C1, the timing at which the carrier C2 takes the value drt coincides with the timing at which the carrier C1 takes the value drt. By setting each signal wave for the carrier C2 as described above, the switching signals Sup, Svp, Swp are all inactive at the timing when the carrier C2 takes the value drt.

  Thus, conventionally, the zero voltage near the carrier C1 adopts the conduction ratio drt so that the commutation of the current source converter 2 realizes zero current switching regardless of whether or not the zero voltage vector V7 is adopted. Vector V0 was adopted.

  FIG. 4 is a graph showing the waveforms of signal waves Vu *, Vv *, and Vw * for the carrier C2. However, the horizontal axis is different from that of FIG. 2 and employs the phase angle for the output voltage. Further, the case where the zero voltage vector V7 is not adopted (d7 = 0) is illustrated, Vw * = 0 at a phase angle of 0 to 120 °, Vu * = 0 at a phase angle of 120 to 240 °, At the phase angle of 240 to 360 °, Vv * = 0. At the phase angle of 0 to 120 °, the signal waves Vu *, Vv *, and Vw * are the signal waves drt (1-d0), drt (1-d0-d4), drt (1-d0-d4-d6), respectively. ).

  When the phase angle is 0 to 60 °, the phase voltages Vu, Vv, and Vw are the maximum phase, intermediate phase, and minimum phase, respectively. In this phase angle range, the signal wave difference S41 = Vu * −Vv * = drt · d4 and S61 = Vv * −Vw * = drt · d6 employ the voltage vectors V4 and V6 in the period drt · T0, respectively. Corresponds to the length of the period. Similarly, the lengths of the periods in which the voltage vectors V4 and V6 are employed in the period dst · T0 are dst · d4 = (dst / drt) S41. dst · d6 = (dst / drt) S61. Therefore, at the phase angle of 0 to 60 °, the length of the period in which the voltage vectors V4 and V6 are employed in one cycle of the carrier C2 (which is also one cycle of the carrier C1) depends on whether or not the zero voltage vectors V0 and V7 exist. Regardless, it is determined by the difference between signal waves S41 and S61.

  In other words, as long as the signal wave differences S41 and S61 are maintained, the phase voltages Vu, Vv, and Vw do not depend on the position and length of the period in which the zero voltage vector is employed. Therefore, in the present embodiment, the zero voltage vector V7 is set in the vicinity where the carrier C1 takes the conduction ratio drt so that switching for commutation of the current source converter 2 realizes zero current switching as described below. adopt.

  FIG. 5 is a graph showing the operation in the first example of the present embodiment of the direct AC power converter. Similar to the situation shown in FIG. 3, the time when the carrier C1 becomes equal to the conduction ratio drt is adopted as the timing when the current source converter 2 commutates.

  In order to perform instantaneous space voltage vector modulation of the voltage source inverter 4, the carrier C3 is compared with the signal wave, and the switching signals Syp and Syn are generated based on the comparison result. As the carrier C3, a waveform having the same shape and opposite phase as that of the carrier C1 is employed.

  That is, when the carrier C1 for the current converter 2 takes the maximum value, the carrier C3 for the inverter takes the minimum value, and when the carrier C1 takes the minimum value, the carrier C3 takes the maximum value.

  In the following, in order to simplify the description, the carriers C1 and C3 are taken as an example where the minimum value is 0 and the maximum value is 1. However, arbitrary values can be selected as the minimum value and the maximum value by appropriately performing linear conversion on the signal wave.

  In FIG. 5 as well, the voltage vector representing the switching pattern to be adopted by the voltage source inverter 4 is represented by d4 · V4 + d6 · V6 using vector calculation, and exemplifies the case where d0 + d7 = 1− (d4 + d6)> 0 Yes. However, d0 = 0 in the operation in the present embodiment.

  When the zero voltage vector V7 is employed, all of the connection points Pu, Pv, Pw are short-circuited by the upper arm side switches Qup, Qvp, Qwp and the upper arm side diodes Dup, Dvp, Dwp.

  Therefore, the link current Idc becomes zero. Therefore, so-called zero current switching is realized in the switching for commutation of the current source converter 2 during the period in which the switching pattern corresponding to the zero voltage vector V7 is employed.

  Based on the above viewpoint, the period in which the unit voltage vectors V4, V6, V7 are employed as the switching pattern in the voltage source inverter 4 is set as follows. In FIG. 5, the switching signal Sup is activated when the carrier C3 takes a value between the signal wave dst + drt (d7 + d6 + d4) and the signal wave dst (1-d7-d6-d4). Here, since d4 + d6 + d7 = 1 is set, the switching signal Sup is activated in both the periods dst · T0 and drt · T0.

  The switching signal Svp is activated when the carrier C3 takes a value between the signal wave (dst + drt (1-d4)) and the signal wave dst · d4, and the carrier C3 becomes the signal wave (dst + drt (1-d4-d6)). The case where the switching signal Swp is activated when taking a value between the signal wave dst (d4 + d6) is exemplified.

  Since the carrier C3 has the same shape and opposite phase as the carrier C1, the timing at which the carrier C3 takes the value dst coincides with the timing at which the carrier C1 takes the value drt. By setting each signal wave for the carrier C3 as described above, the switching signals Sup, Svp, Swp are all activated at the timing when the carrier C3 takes the value dst. Therefore, zero current switching can be realized.

  Even if such zero current switching is not realized, any one of the switching signals Sup, Svp, and Swp can always be activated when the voltage source inverter 4 is driven. Therefore, when the voltage source inverter 4 is driven, any one of the upper arm side switches Qup, Qvp, and Qwp is always on, so that an overcurrent protection operation occurs and all of the lower arm side switches Qun, Qvn, Qwn Even if is turned off, the voltage source inverter 4 does not operate as a diode bridge. Therefore, during the overcurrent protection operation, current flows back in the voltage source inverter 4, and regeneration from the voltage source inverter to the DC bus is avoided.

  FIG. 6 is a graph showing the waveforms of signal waves Vu **, Vv **, and Vw ** for the carrier C3. Since the zero voltage vector V0 is not adopted (d0 = 0), Vu ** = 0 at a phase angle of 0 to 60 ° and 300 to 360 °, and Vv ** = 0 at a phase angle of 60 to 180 °. When the phase angle is 180 to 300 °, Vw ** = 0. At the phase angles of 0 to 60 ° and 300 to 360 °, the signal waves Vu **, Vv **, and Vw ** are the signal waves dst + drt (d7 + d6 + d4), dst + drt (1-d4), dst + drt · (1- d4-d6) is adopted.

  At the phase angle of 0 to 60 °, the phase voltages Vu, Vv, and Vw become the maximum phase, the intermediate phase, and the minimum phase, respectively, similarly to the waveform shown in FIG. In this phase angle range, the signal wave differences S42 = Vu ** − Vv ** = drt · d4 and S62 = Vv ** − Vw ** = drt · d6 are voltage vectors V4 and V6 in the period drt · T0, respectively. Corresponds to the length of the period in which is adopted. Similarly, the lengths of the periods in which the voltage vectors V4 and V6 are employed in the period dst · T0 are dst · d4 = (dst / drt) S42 and dst · d6 = (dst / drt) S62, respectively. Therefore, at the phase angle of 0 to 60 °, the length of the period in which the voltage vectors V4 and V6 are employed in one cycle of the carrier C3 (which is also one cycle of the carrier C1) depends on whether or not the zero voltage vectors V0 and V7 exist. Regardless, it is determined by the difference between signal waves S42 and S62.

  Now, since the signal waves Vu **, Vv **, and Vw ** are set as described above, the length drt · of the voltage vector obtained based on the signal wave differences S42 and S62 in one cycle of the carrier C3. It can be seen that d4 + dst · d4, drt · d6 + dst · d6 is equal to the length dst · d4 + drt · d4 + drt · d6 + drt · d6 of the voltage vector obtained based on the signal wave differences S41 and S61 in one cycle of the carrier C2. In other words, when the duty ratios d4 and d6 are given, as in the prior art shown in FIG. 3, the switching that is adopted by the voltage source inverter 4 to obtain the voltage vector represented by d4 · V4 + d6 · V6. It can be said that a pattern is obtained.

  When switching for commutation is executed in the current source converter 2, all the upper arm switches are turned on, so that zero current switching is realized.

  FIG. 7 is a graph showing the operation in the second example of the present embodiment of the direct AC power converter. Compared to the first example, the voltage source inverter 4 is different in that the carrier C2 is employed. Further, due to the difference, the signal waves to be used are also different.

  That is, in the second example, the switching signal Sup is activated when the carrier C2 takes a value between the signal wave drt + dst (d7 + d6 + d4) and the signal wave drt (1-d7-d6-d4). Here, since d4 + d6 + d7 = 1 is set, the switching signal Sup is activated in both the periods dst · T0 and drt · T0. When the carrier C2 takes a value between the signal wave (drt + dst (1-d4)) and the signal wave drt · d4, the switching signal Svp is activated, and the carrier C2 becomes the signal wave (drt + dst (1-d4-d6)). The case where the switching signal Swp is activated when taking a value between the signal wave drt (d4 + d6) is exemplified.

  Since the carrier C2 has the same shape and the same phase as the carrier C1, the timing at which the carrier C2 takes the value drt coincides with the timing at which the carrier C1 takes the value drt. By setting each signal wave for the carrier C2 as described above, the switching signals Sup, Svp, Swp are all inactive at the timing when the carrier C2 takes the value drt.

  As described above, the signal wave employed in the second example is obtained by exchanging the conduction ratios drt and dst with the signal wave employed in the first example. Therefore, in the second example, similarly to the first example, if the time ratios d4 and d6 are given, the voltage vector represented by d4 · V4 + d6 · V6 is obtained as in the conventional technique shown in FIG. It can be said that a switching pattern to be employed in the voltage source inverter 4 is obtained.

  Summarizing the first example and the second example, the following can be said. The ratio of the lengths of the first period and the second period is drt: dst (where dst = 1−drt). The length ratio in which the unit voltage vectors V4, V6, V7 are adopted is d4: d6: (1-d4-d6). The inverter carriers C2 and C3 exhibit a triangular wave, and their minimum and maximum values are 0 and 1, respectively. The inverter carriers C2 and C3 take the value dbc at the timing when the current source converter 2 commutates, that is, when the carrier C1, which is a triangular wave, takes the conduction ratio drt. However, the value dbc is either the flow ratio drt or dst. Since the inverter carrier is a triangular wave, it is uniquely determined that the inverter carriers C3 and C2 are adopted corresponding to the value dbc adopting the flow ratios drt and dst.

  The signal waves Vu **, Vv **, and Vw ** take values 1, dbc + dac (1-d4), dbc (1-d4-d6), respectively. Further, signal waves 0, dbc · d4, and dbc (d4 + d6) are set corresponding to the signal waves Vu **, Vv **, and Vw **, respectively.

  FIG. 8 is a block diagram illustrating a conceptual example of a specific internal configuration of the control unit 100 that performs the above-described control. The control unit 100 can be employed as the control device 6 in FIG. The control unit 100 includes an overcurrent protection unit 10, a converter control unit 20, an inverter control unit 30, a modulation factor calculation unit 40, and a sensorless vector control unit 50. A three-phase motor is assumed as the three-phase load 5 (see FIG. 1).

  The converter control unit 20 includes a power supply phase detection unit 21, a conduction ratio generation unit 22, a comparator 23, a current source gate logic conversion unit 24, and a carrier generation unit 25.

  The power supply phase detector 21 detects, for example, the line voltage Vrs, detects the phase angle θ of the three-phase AC voltage applied to the input terminals Pr, Ps, and Pt, and outputs the detected phase angle θ to the conduction ratio generator 22.

  The conduction ratio generation unit 22 generates the conduction ratios dac and dbc based on the received phase angle θ and the line current conduction ratio shown in the graph of FIG. 2 (for example, based on a predetermined table). In the above example, the flow ratios dac and dbc correspond to the flow ratios dst and drt, respectively.

  The carrier generation unit 25 generates a carrier C1. The comparator 23 outputs the result of comparing the carrier C1 with the current ratios dac and dbc, and based on this, the current source gate logic conversion unit 24 generates the switching signals Srp, Ssp, Stp, Srn, Ssn, Stn. To do.

  The inverter control unit 30 includes a duty ratio generation unit 32, a signal wave generation unit 34, a carrier generation unit 35, a comparator 36, and a logical operation unit 38.

  Based on the modulation rate ks received from the modulation rate calculation unit 40, the control phase angle φ, and the command phase angle φ ′ received from the sensorless vector control unit 50, the time ratio generation unit 32 The ratios dg1 and dg2 are generated. In the above example, the time ratios dg1 and dg2 correspond to the time ratios d4 and d6, respectively.

  The signal wave generator 34 generates a signal wave from the time ratios dg1 and dg2 and the flow ratios dac and dbc. In the first example, the signal waves dst + drt (d7 + d6 + d4), dst + drt (1-d4), dst + drt · (1-d4-d6), dst (1-d7-d6-d4), dst · d4, dst (d4 + d6) ) Is generated. Since these generations can be realized with the same level of technology as the conventional technology for generating signal waves, the details are omitted.

  The carrier generation unit 35 generates a carrier C3. The signal wave is compared with the carrier C3 in the comparator 36, and the result is calculated by the logic operation unit 38. By this operation, the logic operation unit 38 generates the upper arm side switching signals Sup, Svp, Swp.

  From the above, the inverter control unit 30 generates the upper arm side switching signals Sup, Svp, Swp based on the comparison between the signal wave for the voltage source inverter 4 and the carrier C3 for the voltage source inverter 4. It can be grasped as an arm-side switching signal generator.

  The modulation factor calculation unit 40 receives the d-axis voltage command Vd * and the q-axis voltage command Vq * from the sensorless vector control unit 50, calculates the modulation factor ks and the control phase angle φ, and outputs them as a time ratio generation unit. 32.

  The sensorless vector control unit 50 calculates the rotational angular velocity ω and the command phase angle φ ′ of the motor based on the line currents iu, iv, iw flowing from the connection points Pu, Pv, Pw to the three-phase load 5, and The d-axis voltage command Vd * and the q-axis voltage command Vq * are generated on the basis of the rotational angular velocity command ω * and the duty D input from.

  The overcurrent protection unit 10 includes a protection signal generation device 11 and a lower arm side switching signal generation unit 12.

  The protection signal generator 11 generates a protection signal M that is activated when the current Idc flowing through the DC buses LH and LL exceeds a threshold value. The fact that the current Idc has exceeded the threshold value is detected based on the shunt resistor 3 or the voltage drop CIN obtained from the shunt resistor 3 and the filter 9.

  According to the technique disclosed in Non-Patent Document 2, once the protection signal M is activated, it is not deactivated until the protection signal generator 11 is reset again. Alternatively, it may be deactivated when the current Idc does not exceed the threshold value.

  The lower arm side switching signal generator 12 generates the lower arm side switching signals Sun, Svn, Swn based on the protection signal M and the upper arm side switching signals Sup, Svp, Swp. When the protection signal M is inactive, signals complementary to the upper arm side switching signals Sup, Svp, Swp are adopted as the lower arm side switching signals Sun, Svn, Qwn, respectively. When the protection signal M is active, the lower arm side switching signals Sun, Svn, Swn are inactivated without depending on the upper arm side switching signals Sup, Svp, Swp.

  Specifically, the lower arm side switching signal generation unit 12 can be realized by, for example, three NOR gates. That is, the active / inactive is associated with the logical value “H” / “L”, and the logical value of the lower arm side switching signal Sun is obtained as the negation of the logical sum of the upper arm side switching signal Sup and the protection signal M. The logical value of the lower arm side switching signal Svn is obtained as the negation of the logical sum of the upper arm side switching signal Svp and the protection signal M, and the logical value of the lower arm side switching signal Swn is obtained from the upper arm side switching signal Swp and the protection signal. Obtained as negation of logical OR with M.

  From the above, the inverter control unit 30 outputs the upper arm side switching signals Sup, Svp, Swp and the lower arm side switching signals Sun, Svn, Swn in combination with the protection signal generation device 11 and the lower arm side switching signal generation unit 12. It can be grasped as an inverter control device that outputs.

  Of course, when the zero voltage vector V7 is employed, all the upper arm side switching signals Sup, Svp, Swp are activated without depending on the protection signal M, and all the lower arm side switching signals Sun, Svn, Swn is deactivated.

  Further, the upper arm side switching signal generation unit 30 and the lower arm side switching signal generation unit 12 may generate the switching signals Syp and Syn in consideration of dead time.

DESCRIPTION OF SYMBOLS 100 Control part 11 Protection signal production | generation apparatus 12 Lower arm side switching signal production | generation part 2 Current source converter 30 Upper arm side switching signal production | generation part 4 Voltage type inverter 6 Control apparatus LL, LH DC bus line d0, d4, d6, d7, dg1, dg2 Time constant dst, drt, dac, dbc Current ratio Dup, Dvp, Dwp Upper arm side diode Dun, Dvn, Dwn Lower arm side diode Sup, Svp, Swp Upper arm side switching signal Sun, Svn, Swn Lower arm side switching Signal Pr, Ps, Pt Input terminal Qup, Qvp, Qwp Upper arm side switch Qun, Qvn, Qwn Lower arm side switch T0 Period

Claims (4)

An apparatus for controlling a voltage source inverter (4) for converting a DC voltage (Vdc) into a three-phase AC voltage (Vu, Vv, Vw),
The voltage source inverter (4)
Comprising three current paths connected in parallel between the first and second DC buses (LH, LL) to which the DC voltage is applied;
The first DC bus (LH) is at a higher potential than the second DC bus (LL);
Each of the current paths is
Connection points (Pu, Pv, Pw);
Connected between the first DC bus and the connection point, and conductive / non-conductive according to the upper arm side switching signal (Sup, Svp, Swp), and when conducting, current flows from the first DC bus to the connection point. Upper arm side switch (Qup, Qvp, Qwp)
Connected between the connection point and the second DC bus, is turned on / off in accordance with a lower arm side switching signal (Sun, Svn, Swn), and when turned on, current flows from the connection point to the second DC bus. Lower arm switch (Qun, Qvn, Qwn)
Upper arm side diodes (Dup, Dvp, Dwp) connected in antiparallel to each of the upper arm side switches;
Lower arm side diodes (Dun, Dvn, Dwn) connected in antiparallel to each of the lower arm switches,
The device is
An upper arm side switching signal generating unit (30) for generating upper arm side switching signals (Sup, Svp, Swp) based on the comparison between the inverter signal wave and the inverter carriers (C2, C3);
A protection signal generator (11) that activates a protection signal (M) when a current flowing through the pair of DC buses exceeds a threshold;
When the protection signal is inactive, a signal complementary to the upper arm side switching signal is adopted as the lower arm side switching signal, and when the protection signal is active, the lower arm side switching signal is not dependent on the lower arm side switching signal. A lower arm side switching signal generation unit (12) for inactivating the arm side switching signal,
The said upper arm side switching signal generation part is an inverter control apparatus which always activates any one of the said upper arm side switching signals at the time of the drive of the said voltage source inverter.   When all the connection points (Pu, Pv, Pw) are connected to each other by the voltage source inverter (4), all the upper arm side switching signals (Sup, Svp, Swp) are activated, The inverter control device according to claim 1, wherein the lower arm side switching signals (Sun, Svn, Swn) are deactivated. Between the first DC bus (LH) and the second DC bus (LL), a current source converter that converts a multiphase AC voltage (Vr, Vs, Vt) into the DC voltage (Vdc) ( 2) is connected,
At least when the commutation occurs in the current converter, all the upper arm side switching signals (Sup, Svp, Swp) are activated and all the lower arm side switching signals (Sun, Svn, Swn) are not The inverter control device according to claim 2, which is activated. In the current source converter (2), the commutation is generated at a timing when one period (T0) of the converter carrier (C1) is divided into a first period (dst · T0) and a second period (drt · T0). And
The upper arm side switching signal (Sup) corresponding to the upper arm side switch (Qup) provided in the first current path corresponding to the maximum phase (Vu) of the three-phase AC voltage is the inverter carrier. Is activated when taking a value between the first signal wave for the inverter and the second signal wave for the inverter),
The upper arm side switching signal (Svp) corresponding to the upper arm side switch (Qvp) provided in the second current path corresponding to the intermediate phase (Vv) of the three-phase AC voltage is the inverter carrier. Is activated when taking a value between the third inverter signal wave and the fourth inverter signal wave,
The upper arm side switching signal (Swp) corresponding to the upper arm side switch (Qwp) provided in the third current path corresponding to the minimum phase (Vw) of the three-phase AC voltage is the inverter carrier. Is activated when taking a value between the fifth inverter signal wave and the sixth inverter signal wave,
The ratio of the length of the first period to the second period is dac: dbc (where dbc = 1-dac)
A first section (V4) in which only the upper arm switch (Qup) provided in the first current path is conductive; and the two upper paths provided in the first and second current paths. A second interval (V6) in which only the arm side switches (Qup, Qvp) are conducted, and a third interval (in which the three upper arm switches (Qup, Qvp, Qwp) provided in all the current paths are conducted) The ratio of length to V7) is dg1: dg2: dg3 (where dg1 + dg2 + dg3 = 1)
When the minimum and maximum values of the inverter carrier are 0 and 1, respectively,
The inverter carrier exhibits a triangular wave taking the value dbc at the timing,
The signal wave for the second inverter takes a value of 1,
The fourth inverter signal wave takes the value dbc + dac (1-dg1),
The sixth inverter signal wave takes the value dbc + dac (1-dg1-dg2),
The signal wave for the first inverter takes a value of 0,
The signal wave for the third inverter takes the value dbc · dg1,
4. The inverter control device according to claim 3, wherein the fifth inverter signal wave takes a value dbc (dg1 + dg2).

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