JP4600731B2 - Control device for AC / AC direct conversion device - Google Patents

Description

  The present invention relates to a control device for an AC / AC direct conversion device that performs direct conversion between ACs by supplying on / off of a plurality of AC switches capable of controlling current in both directions and supplies the load to a load, and in particular, a semiconductor that constitutes the AC switch. The present invention relates to a control technique that reduces switching loss and generated noise associated with on / off of a switching element.

FIG. 8 shows a control device for an AC / AC direct conversion device described in Japanese Patent Application No. 2003-404449, which is a prior application of the present applicant.
In FIG. 8, a matrix converter 20 as an AC / AC direct conversion device includes AC switches S1 to S9 that are capable of controlling bidirectional current by connecting semiconductor switching elements capable of controlling current in a single direction in antiparallel, for example. The AC input terminals R, S, T and the AC output terminals U, V, W are connected. Reference numeral 30 denotes a load such as an AC motor.

The matrix converter 20 performs PWM control on the AC switches S1 to S9 to directly cut out a three-phase AC voltage, obtains a three-phase AC voltage having an arbitrary magnitude and frequency, and supplies it to the load 30.
As a control method of the input current and output voltage of the matrix converter, a virtual PWM rectifier (hereinafter referred to as a virtual rectifier if necessary) and a virtual PWM inverter (also referred to as a virtual inverter) are assumed in the matrix converter. A virtual AC / DC / AC conversion system that performs PWM control is known (see Non-Patent Document 1 described later).

The control device of FIG. 8 is also based on the virtual AC / DC / AC conversion method, and controls an input current by a virtual rectifier and controls an output voltage by a virtual inverter.
That is, a trapezoidal wave input current command for switching only one phase is generated from the input current command by the trapezoidal wave command generating means 11. Then, the input current command and the carrier from the carrier generating means 12 are compared by the comparing means 13 to obtain a PWM pulse pattern on the virtual rectifier side.

On the other hand, for the virtual inverter side, the on / off ratio of the switching phase of the virtual rectifier output from the on / off ratio extracting means 16 and the R, S, T phases on the power source side (the maximum voltage phase, Based on the voltage of the intermediate voltage phase (intermediate voltage) among the intermediate voltage phase and the minimum voltage phase), the symmetric deformation carrier generating means 18 for reducing the number of switchings creates and outputs a symmetric deformation carrier.
This symmetrically deformed carrier is input to the comparison means 15 and compared with the output voltage command to obtain a PWM pulse pattern on the virtual inverter side.

Here, FIG. 9 shows a circuit for one phase (U phase) of the matrix converter 20. In the matrix converter 20, a switch that switches according to the above-described maximum / intermediate / minimum of the power supply voltage value is selected to control the output voltage.
9 shows a maximum voltage phase, an intermediate voltage phase, and a minimum voltage phase (hereinafter also simply referred to as a maximum phase, an intermediate phase, and a minimum phase) corresponding to the magnitudes of the R, S, and T phase voltages in FIG. The AC switches 21, 22, and 23 are respectively connected to the U phase on the side. For example, when the R phase is the maximum phase, the S phase is the intermediate phase, and the T phase is the minimum phase, the AC switches 21, 22, and 23 in FIG. 9 correspond to the AC switches S1, S4, and S7 in FIG.

In FIG. 9, the switches 21a and 23a with the reference symbol a added to the polarity of the applied voltage resulting from the connection relationship with the maximum phase, intermediate phase, and minimum phase are the switches that operate in the IGBT mode and the reference symbol b. Switches 21b and 23b are switches that operate in a freewheeling diode mode, respectively.
Here, the IGBT mode refers to an operation mode in which a forward voltage is applied between the collector and the emitter (the collector voltage is higher than the emitter voltage), and is an operation mode in which a current flows at the same time as the gate is turned on. The freewheeling diode mode is an operation mode in which a reverse voltage is applied between the collector and the emitter (the collector voltage is lower than the emitter voltage). In this case, the forward voltage is applied and the gate is not turned on. Since the current does not flow and the operation is almost the same as that of the freewheeling diode in the inverter, it is called the freewheeling diode mode.

As for the switches 22a / b and 22b / a of the switch 22 connected to the intermediate phase, when switching between the maximum phase and the intermediate phase (when the switch 22 operates as a lower arm), the intermediate phase and the minimum When switching between phases (when the switch 22 operates as an upper arm), both switches that are in the IGBT mode and the freewheeling diode mode are switched. For this reason, 2a / b and 2b / a are added to the reference symbols.
For example, when switching is performed by the switches 21 and 22 between the maximum phase and the intermediate phase in FIG. 9, the switch 22a / b is in the IGBT mode and 22b / a is in the freewheeling diode mode, and the switch between the intermediate phase and the minimum phase When switching is performed at 22, 23, the switch 22a / b is in the freewheeling diode mode, and 22b / a is in the IGBT mode.

In the virtual AC / DC / AC conversion method, there are “upper arm switching” and “lower arm switching” as basic concepts regarding the switching mode.
“Upper arm switching” is a mode in which the upper arm PWM pulse of the virtual inverter is distributed and switched by the PWM pulses of the maximum-phase and intermediate-phase AC switches, and “lower arm switching” is the lower arm of the virtual inverter. In this mode, the PWM pulse is distributed and switched by the PWM pulse of the AC switch of the intermediate phase and the minimum phase.
Here, “distribute” means that, for example, at the time of “upper arm switching”, the upper arm PWM pulse of the virtual inverter becomes the logical sum of the PWM pulses of the maximum-phase and intermediate-phase AC switches.

“Upper arm switching” or “lower arm switching” depends on the polarity of the intermediate voltage. When the intermediate voltage is positive, “upper arm switching”, and when the intermediate voltage is negative, “lower arm switching”. "
For example, when the intermediate voltage is positive (upper arm switching), the PWM pulse of the U-phase upper arm of the virtual inverter is distributed by the PWM pulses of the AC switches 21 and 22 (maximum phase and intermediate phase switches) in FIG. When the intermediate voltage is negative (lower arm switching), the PWM pulses of the U-phase lower arm of the virtual inverter are distributed by the PWM pulses of the AC switches 22 and 23 (intermediate phase and minimum phase switches) in FIG.

In FIG. 8, the intermediate voltage detected from the power supply voltage of each phase is input to the symmetric deformation carrier generation means 18 for reducing the number of switching times, and the generation means 18 generates a deformation carrier depending on the intermediate voltage to generate the PWM pulse of the virtual inverter. Have gained.
Here, FIG. 10 shows a symmetrical deformed triangular wave in which the Up / Down pattern is switched according to the Up / Down of the virtual rectifier carrier (output of the carrier generating means 12) as the virtual inverter carrier without considering the polarity of the intermediate voltage. The virtual rectifier PWM pulse, the PWM pulse of the upper and lower arms of the virtual inverter, the PWM pulse of the matrix converter 20, and the like are shown. Note that the peak value of the virtual inverter carrier is set (preset) at the time of the maximum value and the minimum value (mountain, valley) of the virtual rectifier carrier.

  When the ratio of Up and Down of the virtual inverter carrier is determined by the on / off ratio (duty ratio) of the virtual rectifier PWM pulse, the virtual inverter carrier is symmetric at the peaks and valleys of the virtual rectifier carrier as shown in FIG. As a result, the upper and lower arm PWM pulses of the virtual inverter are symmetric with respect to the peaks and valleys of the virtual rectifier carrier. In FIG. 10, a to d indicate timings at which the virtual rectifier PWM pulse changes.

In this case, as apparent from a to d in FIG. 10, when the upper arm is switched, the pulse change accompanying the PWM pulse change of the virtual rectifier appears in the PWM pulse of the matrix converter 20, so the number of times of switching is six. .
On the other hand, in the lower arm switching, the PWM pulse change of the virtual rectifier appears when the PWM pulse of the AC switch connected to the minimum phase of the matrix converter (lower arm of the virtual inverter) is off, and the PWM of the virtual rectifier The pulse change accompanying the pulse change does not appear in the PWM pulse of the matrix converter, and the number of times of switching is four.

That is, if the virtual rectifier is switched when the virtual inverter PWM pulse of the same arm as the switching arm (for example, the upper arm when the upper arm is switched or the lower arm when the lower arm is switched) is OFF, the PWM pulse change of the virtual rectifier is changed. It does not appear in the PWM pulse of the matrix converter, and the switching frequency can be reduced.
Therefore, as shown in FIG. 11, for example, when the upper arm is switched when the intermediate voltage is positive, zero is set in the Up / Down counter (to be described later) as the value of the virtual inverter carrier by the interrupt process at the timing of the peak and valley of the virtual rectifier carrier. At the same time, the Up / Down timing of the virtual inverter carrier is inverted with respect to FIG. 10 (the virtual inverter carrier is inverted 180 °). The inversion of the Up / Down timing is performed by switching the Up / Down count of the Up / Down counter.

As a result, as shown in FIG. 11, the fold-back point (top point) of the virtual inverter carrier and the PWM pulse change time of the virtual rectifier are synchronized. As a result, the PWM pulse change of the virtual rectifier occurs only when the upper arm AC switch connected to the maximum phase is off, and the pulse change of the virtual PWM rectifier appears in the PWM pulse of the matrix converter. Absent.
Therefore, the number of times of switching of the matrix converter 20 at the time of switching the upper arm can be set to 4 times per switching cycle.

Even if the phase of the virtual inverter carrier is reversed, if the carrier waveform is a straight line, the carrier comparison method uses an on / off ratio according to the output voltage command during one switching cycle (one cycle of the virtual rectifier carrier or virtual inverter carrier). Therefore, an output voltage corresponding to the output voltage command can be obtained.
Although not shown in the figure, when switching the lower arm where the intermediate voltage is negative, the virtual inverter carrier value is set according to the pulse width of the virtual rectifier PWM pulse as a value of the virtual inverter carrier by the interrupt processing of the peak and valley timings of the virtual rectifier carrier. The peak value is set in the Up / Down counter, and the virtual inverter carrier is inverted by 180 ° with respect to FIG.

FIG. 12 is a block diagram showing a hardware configuration of the symmetric deformation carrier generating means 18 for reducing the number of switching times in FIG.
In FIG. 12, reference numeral 181 denotes an intermediate voltage positive / negative discriminating circuit to which an intermediate voltage is inputted, 182 is an XOR (exclusive OR) circuit to which an up / down signal of the virtual rectifier carrier and a virtual rectifier PWM pulse are inputted, and 183 is an XOR circuit. A NOT circuit to which the output of 182 is added, 184 is a selector that switches the output of the XOR circuit 182 and the output of the NOT circuit 183 in accordance with the polarity of the intermediate voltage, and outputs either of them as a virtual inverter carrier Up / Down signal, Reference numeral 185 denotes an Up / Down counter which counts Up / Down according to the virtual inverter carrier Up / Down signal from the selector 184 and receives the peak value of the virtual rectifier carrier and zero, and the output of the counter 185 is Input to the comparison means 15 as a virtual inverter carrier There.
Reference numerals 186 and 187 denote voltage command registers that hold the output voltage command of the virtual inverter. Reference numeral 188 denotes a selector that selects the registers 186 and 187 in accordance with the virtual rectifier PWM pulse and outputs a predetermined voltage command to the comparison means 15. It is.

In this symmetrically deformed carrier generating means 18, in order to reduce the number of times of switching, the Up / Down of the inverter carrier is inverted according to the polarity of the intermediate voltage, and the Up / Down counter for each interrupt synchronized with the peak of the virtual rectifier carrier. For 185, the inverter carrier peak value is set to a peak value or zero according to the PWM pulse width of the virtual rectifier.
However, Up / Down is always switched at the peak time of the carrier so that the carrier does not jump when the virtual inverter carrier is inverted.

In the lower part of FIG. 11 described above, the virtual rectifier carrier Up / Down signal, the output of the XOR circuit 182 and the output of the NOT circuit 183 in FIG. 12 are shown together. The output of the illustrated XOR circuit 182 and the output of the NOT circuit 183 are selected by the selector 184 according to the polarity of the intermediate voltage, and the selected signal is used as the Up / Down signal of the virtual inverter carrier to generate the illustrated virtual inverter carrier. Is done. Here, the example of FIG. 11 is an example in which the selector 184 selects the output of the NOT circuit 183 and uses this output as the Up / Down signal of the virtual inverter carrier.
Although not shown, in the example of FIG. 11, the number of times of switching in one switching period is four even when the lower arm is switched, and the number of times of switching in one switching period can be four over all the operating periods.

Shinichi Ito and two others, “Improvement method of input / output waveform of matrix converter by virtual AC / DC / AC conversion method”, Institute of Electrical Engineers of Japan (Semiconductor power conversion / industrial power / electricity application joint study group), SPC-02 -77-96, IEA-02-18-37, November 14, 2002, p. 75-80

According to the invention described in the prior application described above, it is possible to reduce switching loss and noise by reducing the number of times of switching of the AC switch.
However, since the drive pulse (PWM pulse) for the AC switch cannot be output in an arbitrary order in this prior invention, the voltage supplied to the load via the AC switch by switching is changed from the minimum phase voltage to the maximum phase voltage (in FIG. 11). The number of times of switching is the second timing) or a state in which the maximum phase voltage is shifted to the minimum phase voltage (similarly, the number of switching times is the third timing). If the switching state directly shifts between the maximum phase and the minimum phase in this way, the intermediate phase is not passed, so the voltage applied to the AC switch changes suddenly, resulting in an increase in switching loss, and the cooling fins for cooling. This leads to an increase in capacity and volume.
Further, at the time of commutation, there is a problem that a large surge voltage is generated in the output voltage and switching noise is increased, and torque ripple is increased when controlling the electric motor.

  Therefore, the problem to be solved by the present invention is that the drive pulses of the AC switch are generated in a desired order, the sudden change of the voltage applied to the AC switch is prevented, switching loss and noise are reduced, It is an object of the present invention to provide a control device that can improve efficiency.

In order to solve the above-mentioned problem, the invention described in claim 1 is to turn on and off a plurality of AC switches capable of controlling currents in both directions, thereby changing a multiphase AC power supply voltage to an AC voltage having an arbitrary magnitude and frequency. In the AC / AC direct conversion device that directly converts to the load and supplies it to the load
Pulse generation means for comparing the input current command and output voltage command of the converter with the carrier and generating a drive pulse of the semiconductor switching element constituting the AC switch;
Order control means for controlling the order of the drive pulses in accordance with the magnitude relationship of each phase power supply voltage, and changing the order of each phase power supply voltage supplied to the load ,
Assuming the AC / AC direct conversion device by a combination of a virtual rectifier and a virtual inverter,
The pulse generation means includes
Means for comparing the input current command of the virtual rectifier and the first carrier to generate a PWM pulse of the virtual rectifier;
The second carrier having an Up period and a Down period corresponding to the on / off ratio of the PWM pulse of the virtual rectifier, and symmetrical with respect to the peak and peak of the first carrier and the output voltage of the virtual inverter Means for comparing the command and generating a PWM pulse of the virtual inverter,
The order control means includes
Using the PWM pulses of the virtual rectifier and the virtual inverter and the first carrier, the order is controlled according to the magnitude relationship of the phase power supply voltages so as to change the order of the phase power supply voltages supplied to the load. The generated PWM pulse is generated and output .

According to a second aspect of the present invention, in the first aspect, the sequence control means outputs a plurality of PWM pulses obtained by distributing the PWM pulses of the virtual inverter according to the magnitude relation of the phase power supply voltages at a certain sampling time. Time is measured, and at the next sampling time, the output order of the plurality of pulses having the output time is changed so as not to cause a sudden change in each phase power supply voltage supplied to the load .

In the invention described in claim 3, by turning on and off a plurality of AC switches capable of controlling currents in both directions, a multi-phase AC power supply voltage is directly converted into an AC voltage having an arbitrary magnitude and frequency, and is converted into a load. In the supplied AC / AC direct conversion device ,
Pulse generation means for comparing the input current command and output voltage command of the converter with the carrier and generating a drive pulse of the semiconductor switching element constituting the AC switch;
Order control means for controlling the order of the drive pulses in accordance with the magnitude relationship of each phase power supply voltage, and changing the order of each phase power supply voltage supplied to the load,
Assuming the AC / AC direct conversion device by a combination of a virtual rectifier and a virtual inverter,
The pulse generation means includes
A synthesis command generating means for generating a plurality of synthesized command values by synthesizing the input current command of the virtual rectifier and the output voltage command of the virtual inverter according to the polarity of the intermediate voltage of the three-phase power supply voltage,
The sequence control means includes
Based on the pulse obtained by comparing the combined command value and the carrier, a PWM pulse whose order is controlled in accordance with the magnitude relationship of each phase power supply voltage so as to change the order of each phase power supply voltage supplied to the load. Generate and output .

The invention described in claim 4 is, in claim 3 ,
The sequence control means generates a PWM pulse whose order is controlled based on the two synthesis command values output from the synthesis command generation means so as not to cause a sudden change in each phase power supply voltage supplied to the load. It is.

A fifth aspect of the present invention is the matrix converter according to any one of the first to fourth aspects, wherein the AC / AC direct conversion device performs a three-phase to three-phase conversion, and the sequence control means includes a three-phase converter. The order of pulses is controlled in accordance with the magnitude relationship among the maximum phase voltage, the intermediate phase voltage, and the minimum phase voltage .

In an AC / AC direct conversion apparatus such as a matrix converter, according to the inventions of claims 1 , 2 , and 5 , PWM pulses obtained from the control means of the virtual PWM rectifier and the virtual inverter are rearranged with one sampling delay. Switching from the maximum voltage phase to the minimum voltage phase or from the minimum voltage phase to the maximum voltage phase can be avoided, and the occurrence of switching loss and noise can be prevented.
Further, according to the inventions of claims 3 to 5 , without any sampling delay, for example, only two pieces of information of the combined command values of the maximum voltage phase, the intermediate voltage phase, or the minimum voltage phase are supplied to the load over the entire operation range. The order of power supply voltage phases can be changed. As a result, switching between the maximum voltage phase and the minimum voltage phase is avoided to prevent the occurrence of switching loss and noise as described above.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a first embodiment of the present invention corresponding to claims 1 , 2 , and 5. The same components as those in FIG. 8 are denoted by the same reference numerals.
In this embodiment, a maximum / intermediate / minimum order control means 40 is provided between the comparison means 13, 15 and the PWM pulse synthesizing means 17, and this order control means 40 is delayed by one switching cycle, and each phase The drive pulses (PWM pulses) of the AC switch that supplies the AC power supply voltage to the load are rearranged and output, and the PWM pulse synthesizing unit 17 uses these PWM pulses as drive pulses for the semiconductor switching elements of the AC switches S1 to S9. Decode.
1, the trapezoidal wave command generation means 11, the carrier generation means 12, the comparison means 13 and 15, the on / off ratio extraction means 16, and the switching frequency reduction symmetrical deformation carrier generation means 18 constitute the pulse generation means in the claims. The maximum / intermediate / minimum order control means 40 constitutes the order control means in the claims.

FIG. 2 shows the configuration of the maximum / intermediate / minimum order control means 40 in FIG.
2, reference numeral 41 denotes a maximum / intermediate / minimum detection unit to which the virtual rectifier PWM pulse output from the comparison unit 13 of FIG. 1 and the virtual inverter PWM pulse output from the comparison unit 15 are input. The detection means 41 detects whether the virtual inverter PWM pulse generates a PWM pulse of maximum phase, intermediate phase, or minimum phase based on the virtual inverter PWM pulse and the virtual rectifier PWM pulse.
That is, as apparent from FIG. 11, the PWM pulse is distributed by the AC switch of the maximum phase and the intermediate phase according to the state of the virtual rectifier PWM pulse and the virtual inverter PWM pulse, for example, when switching the upper arm, It is possible to detect whether the maximum phase or the intermediate phase is distributed depending on the on / off state.
Therefore, the maximum / intermediate / minimum detection means 41 can detect whether the virtual inverter PWM pulse generates the maximum phase, intermediate phase, or minimum phase PWM pulse based on the virtual inverter PWM pulse and the virtual rectifier PWM pulse. is there.

Further, reference numeral 42 in FIG. 2 denotes pulse edge detection means for detecting the edge of the virtual inverter PWM pulse, and its output is inputted to the counter 43 together with the timing of the peak of the virtual rectifier carrier. The counter 43 measures the output time of the maximum phase, intermediate phase, and minimum phase PWM pulses based on the virtual inverter PWM pulse.
The output of the counter 43 is added to the maximum / intermediate / minimum pulse output time storage means 44. In this storage means 44, based on the output of the counter 43, the maximum phase, intermediate phase, minimum phase assumed from the virtual inverter PWM pulse. The PWM pulse output time is stored.
The output of the storage means 44 is added to the maximum / intermediate / minimum pulse output means 45 together with the output information of the detection means 41, and the maximum phase, intermediate phase, and minimum phase determined by the output information of the detection means 41 are stored. The PWM pulses having the output time stored by means 44 are rearranged and output.

  2 will be further described with reference to the waveform diagram of FIG. FIG. 3 is a diagram for explaining the operation of the maximum / intermediate / minimum order control means 40. Virtual rectifier carrier, virtual inverter carrier, virtual inverter output voltage command, virtual inverter upper arm PWM pulse, PWM pulse of matrix converter 20 FIG. 5 is also an explanatory diagram of PWM pulses of the matrix converter 20 after rearrangement.

The pulse edge detection means 42 in FIG. 2 detects the edge of the virtual inverter PWM pulse, and the counter 43 performs a counting operation based on the peak timing of the virtual rectifier carrier, whereby the pulse output time ΔT1 of the maximum phase shown in FIG. (K) The intermediate phase pulse output time ΔT2 (k) and the minimum phase pulse output time ΔT3 (k) are measured at the sampling time (k), and the maximum / intermediate / minimum pulse output time storage means 44 measures these times. Remember.
In the maximum / intermediate / minimum pulse output means 45, the pulse of the output time ΔT1 (k) is the pulse of the maximum phase based on the information output from the maximum / intermediate / minimum detection means 41, and the pulse of the output time ΔT2 (k) Can be recognized that the pulse of the output phase ΔT3 (k) is the pulse of the minimum phase, and at the next sampling time (k + 1) delayed by one switching cycle, the maximum phase → the intermediate phase → Rearrange PWM pulses in the order of minimum phase → minimum phase → intermediate phase → maximum phase.
The PWM pulses after the rearrangement are output to the PWM pulse synthesizing unit 17 shown in FIG. 1, decoded as drive pulses for the semiconductor switching elements of the AC switches S1 to S9, and supplied to the matrix converter 20.

That is, before the PWM pulses are rearranged in FIG. 3, each phase power supply voltage is supplied to the load 30 via the AC switch in the order of intermediate phase → minimum phase → maximum phase → minimum phase → intermediate phase. According to the present embodiment, the power supply voltage is supplied to the load 30 in the order of maximum phase → intermediate phase → minimum phase → minimum phase → intermediate phase → maximum phase by PWM pulse sequence control (rearrangement). .
Therefore, as shown in FIG. 11, a switching state in which the transition from the minimum phase to the maximum phase or from the maximum phase to the minimum phase does not occur, and the intermediate phase is always passed between the maximum phase and the minimum phase. The amount of change in voltage applied to the switch is reduced, and switching loss and noise can be reduced.

Next, FIG. 4 is a block diagram showing a second embodiment of the present invention corresponding to claim 3-5.
In FIG. 4, 51 is an on / off ratio extracting means for extracting the on / off ratio of the AC switch of the virtual rectifier from the trapezoidal wave command, and 52 is an on / off ratio extracting means for extracting the on / off ratio of the AC switch of the virtual inverter from the output voltage command. The input current command of the virtual rectifier and the output voltage command of the virtual inverter standardized by the extraction means 51 and 52 are input to the rectifier / inverter synthesis command generation means 53 and synthesized.
4, the trapezoidal wave command generation means 11, the on / off ratio extraction means 51 and 52, the carrier generation means 54, the rectifier / inverter synthesis command generation means 53, and the comparison means 55 constitute the pulse generation means in the claims. In addition, the rectifier / inverter combination command generation means 53 constitutes the combination command generation means in the claims, and the maximum / intermediate / minimum order control means 56 constitutes the order control means in the claims.

  In this embodiment, the synthesis command values 534a and 534b, which will be described later, output from the synthesis command generation unit 53 and the carrier from the carrier generation unit 54 are compared by the comparison unit 55, and the PWM pulses of the maximum phase, intermediate phase, and minimum phase are compared. By controlling the order of these pulses by the maximum / intermediate / minimum order control means 56, each phase AC power supply voltage can be controlled in a predetermined order without delay of one sampling period as in the first embodiment. The load 30 is supplied.

That is, in FIG. 4, the carrier generation unit 54 generates a carrier whose amplitude is normalized to 0 to 1.0 and inputs the carrier to the comparison unit 55.
On the other hand, the on / off ratio extraction means 51 on the virtual rectifier side normalizes the input current command to 0 to 1.0, and the on / off ratio extraction means 52 on the virtual inverter side normalizes the output voltage command to 0 to 1.0. These standardized input current command and output voltage command are input to the rectifier / inverter composite command generation means 53.

An intermediate voltage phase intermediate voltage is input to the rectifier / inverter combination command generating means 53, and the polarity of the intermediate voltage is determined by the “upper arm switching” or “lower arm switching” in the rectifier / inverter combination command generating means 53. Used to select
As described above, the switching of the upper and lower arms depends on the polarity of the intermediate voltage, and is “upper arm switching” when the intermediate voltage is positive and “lower arm switching” when the intermediate voltage is negative.

FIG. 5 shows the configuration of the rectifier / inverter synthesis command generation means 53.
The intermediate voltage positive / negative discrimination means 531 selects upper arm switching or lower arm switching from the polarity of the intermediate voltage. When the upper arm switching is selected, the on / off ratio of the upper arm of the virtual inverter is distributed between the maximum phase and the intermediate phase by the operation of the selector 532. The on-off ratio of each of the maximum phase and the intermediate phase distributes the zero voltage vector on the virtual inverter side according to the on-off ratio of the input current command in order to avoid imbalance of the input current.

For example, when the maximum phase is selected when the input current command is on and the intermediate phase is selected when the input current command is off, the maximum / intermediate / minimum combined command value generation means 533 causes the maximum phase, intermediate phase, and minimum The phase synthesis command value is distributed according to the following equations 1-3.
[Equation 1]
Maximum phase synthesis command value DUTY _max = DUTY V _inv ^*・ DUTY I _rec ^*
[Equation 2]
Intermediate phase synthesis command value DUTY _mid = DUTY V _inv ^* · (1-DUTY I _rec ^* )
[Equation 3]
Minimum phase synthesis command value DUTY _min = 1.0- (DUTY _max + DUTY _mid )

In Equations 1 to 3, V _inv ^* is an output voltage command, I _rec ^* is an input current command, and DUTY V _inv ^* and DUTY I _rec ^* vary in the range of 0 to 1.0.
Further, the carrier from the carrier generating means 54 has a maximum value = 1.0 and a minimum value = 0.0.

In the synthesis command value selection means 534, any two of the synthesis command values of the maximum phase, the intermediate phase and the minimum phase obtained from the maximum / intermediate / minimum synthesis command value generation means 533 are selected, and the synthesis command values 534a and 534b are selected. To the comparison means 55.
The two combined command values 534a and 534b are compared with the carrier from the carrier generating means 54 in the comparing means 55 and are pulsed.
This output pulse is input to the maximum / intermediate / minimum order control means 56, and the order control means 56 describes the order of supplying each phase (maximum phase, intermediate phase and minimum phase) voltage of the AC power source to the load 30 as will be described later. And output as a PWM pulse. The PWM pulse synthesizing unit 17 decodes the PWM pulse obtained from the maximum / intermediate / minimum order control unit 56 as a drive pulse for each semiconductor switching element of the AC switch.

  Next, FIG. 6 shows the configuration of the comparison means 55 and the maximum / intermediate / minimum order control means 56 in FIG. In the comparator 55, the comparator 551 receives the combined command value 534a output from the rectifier / inverter combined command generator 53 and the carrier output from the carrier generator 54, and generates a PWM pulse 551a by comparing the two. Is done. Further, the comparator 552 receives the sum of the other combined command value 534b output from the rectifier / inverter combined command generating means 53 and the combined command value 534a and the carrier, and the PWM pulse is obtained by comparing the two. 552a is generated.

The maximum / intermediate / minimum order control means 56 distributes the two input PWM pulses 551a and 552a according to the following equations 4 to 6. Reference numeral 561 denotes an XOR (exclusive OR) circuit, and reference numeral 562 denotes a NOT (negative) circuit.
[Equation 4]
PWM pulse 56a = PWM pulse 551a
[Equation 5]
PWM pulse 56b = exclusive OR of PWM pulse 551a and PWM pulse 552a [Equation 6]
PWM pulse 56c = negative logic of PWM pulse 552a

FIG. 7 shows the comparison means 55 and the maximum / intermediate / minimum order control means 56 when the composite command value for the minimum voltage phase is input as the composite command value 534a and the composite command value for the intermediate voltage phase is input as the composite command value 534b. Shows the internal signal.
The PWM pulse 551a output from the comparator 551 becomes the PWM pulse 56a as it is as the minimum voltage phase pulse. The PWM pulse 56b is an exclusive OR of the PWM pulse 551a and the PWM pulse 552a output from the comparator 552, and is equally as an intermediate voltage phase pulse centered on the minimum voltage phase pulse (PWM pulse 56a). Is output.
Further, the PWM pulse 56c is a pulse obtained by inverting the PWM pulse 552a, and is a maximum voltage phase pulse positioned outside the intermediate voltage phase pulse (PWM pulse 56b) with the minimum voltage phase pulse (PWM pulse 56a) as the center.

  According to these maximum phase, intermediate phase, and minimum phase pulses, as in the first embodiment, there is no direct transition from the minimum phase to the maximum phase or from the maximum phase to the minimum phase. In this case, since the switching state always passes through the intermediate phase, the change in the voltage applied to the AC switch is reduced, and the switching loss and noise can be reduced.

As described above, in the second embodiment, the combined command value of the maximum phase, intermediate phase, or minimum phase is output from the rectifier / inverter combined command generating unit 53 without using the symmetrical deformation carrier generating unit 18 as in the first embodiment. To obtain the information of any two of them and compare the combined command value with the carrier to perform a predetermined logical operation, thereby changing the order of each phase power supply voltage connected to the load 30 over the entire operation cycle It is.
Thereby, the control of the virtual rectifier and the virtual inverter constituting the AC / AC direct converter can be realized without generating sampling delay, switching loss, and noise.

1 is a block diagram showing a first embodiment of the present invention. It is a block diagram of the maximum / intermediate / minimum order control means in FIG. FIG. 6 is a waveform diagram for explaining the operation of the maximum / intermediate / minimum order control means in FIG. 1. It is a block diagram which shows 2nd Embodiment of this invention. FIG. 5 is a configuration diagram of maximum / intermediate / minimum order control means in FIG. 4. FIG. 5 is a configuration diagram of a comparison unit and a maximum / intermediate / minimum order control unit in FIG. 4. It is a wave form diagram which shows the operation | movement of FIG. It is a block diagram which shows the control apparatus of a prior application. It is a circuit diagram for the output one phase of a matrix converter. It is explanatory drawing of the virtual rectifier PWM pulse in another prior art, a virtual inverter PWM pulse, etc. It is explanatory drawing of the virtual rectifier pulse in FIG. 8, a virtual inverter PWM pulse, etc. It is a block diagram of the switching frequency reduction symmetrical deformation | transformation carrier generation means in FIG.

Explanation of symbols

11: Trapezoidal wave command generating means 12: Carrier generating means 13, 15: Comparison means 16: On / off ratio extracting means 17: PWM pulse synthesizing means 18: Switching frequency reduction symmetrically deformed carrier generating means 20: Matrix converter 30: Load 40: Maximum / Intermediate / minimum order control means 41: maximum / intermediate / minimum detection means 42: pulse edge detection means 43: counter 44: maximum / intermediate / minimum pulse output time storage means 45: maximum / intermediate / minimum pulse output means 51,52 : ON / OFF ratio extraction means 53: Rectifier / inverter synthesis command generation means 531: Intermediate voltage positive / negative discrimination means 532: Selector 533: Maximum / intermediate / minimum synthesis command value generation means 534: Synthesis command value selection means 54: Carrier generation means 55: Comparison means 551, 552: Comparator 56: Maximum / intermediate / minimum order Control unit 561: XOR circuit 562: NOT circuit 181: intermediate voltage polarity judging circuit 182: XOR circuit 183: NOT circuits 184, 188: Selector 185: Up / Down counter 186 and 187: voltage command register S1-S9: AC switch

Claims (5)

In an AC / AC direct conversion device that directly converts a multi-phase AC power supply voltage to an AC voltage of arbitrary magnitude and frequency and supplies it to a load by turning on and off a plurality of AC switches capable of controlling current in both directions.
Pulse generation means for comparing the input current command and output voltage command of the converter with the carrier and generating a drive pulse of the semiconductor switching element constituting the AC switch;
Order control means for controlling the order of the drive pulses in accordance with the magnitude relationship between the phase power supply voltages and changing the order of the phase power supply voltages supplied to the load;
Equipped with a,
Assuming the AC / AC direct conversion device by a combination of a virtual rectifier and a virtual inverter,
The pulse generation means includes
Means for comparing the input current command of the virtual rectifier and the first carrier to generate a PWM pulse of the virtual rectifier;
The second carrier having an Up period and a Down period corresponding to the on / off ratio of the PWM pulse of the virtual rectifier, and symmetrical with respect to the peak and peak of the first carrier and the output voltage of the virtual inverter Means for comparing the command and generating a PWM pulse of the virtual inverter,
The sequence control means includes
Using the PWM pulses of the virtual rectifier and the virtual inverter and the first carrier, the order is controlled according to the magnitude relationship of the phase power supply voltages so as to change the order of the phase power supply voltages supplied to the load. A control device for an AC / AC direct conversion device , which generates and outputs a PWM pulse . In the control device for the AC / AC direct conversion device according to claim 1,
The sequence control means includes
At a certain sampling time, the output time of a plurality of PWM pulses obtained by distributing the PWM pulses of the virtual inverter according to the magnitude relationship of the power supply voltages of each phase is measured, and at the next sampling time, a plurality of pulses having the output time The control sequence of the AC / AC direct conversion device is characterized in that the output order is changed so as not to cause a sudden change in each phase power supply voltage supplied to the load . In an AC / AC direct conversion device that directly converts a multi-phase AC power supply voltage to an AC voltage of arbitrary magnitude and frequency and supplies it to a load by turning on and off a plurality of AC switches capable of controlling current in both directions .
Pulse generation means for comparing the input current command and output voltage command of the converter with the carrier and generating a drive pulse of the semiconductor switching element constituting the AC switch;
Order control means for controlling the order of the drive pulses in accordance with the magnitude relationship between the phase power supply voltages and changing the order of the phase power supply voltages supplied to the load;
With
Assuming the AC / AC direct conversion device by a combination of a virtual rectifier and a virtual inverter,
The pulse generation means includes
A synthesis command generating means for generating a plurality of synthesized command values by synthesizing the input current command of the virtual rectifier and the output voltage command of the virtual inverter according to the polarity of the intermediate voltage of the three-phase power supply voltage,
The order control means includes
Based on the pulse obtained by comparing the combined command value and the carrier, a PWM pulse whose order is controlled in accordance with the magnitude relationship of each phase power supply voltage so as to change the order of each phase power supply voltage supplied to the load. A control device for an AC / AC direct conversion device, characterized by generating and outputting . In the control device for an AC / AC direct conversion device according to claim 3 ,
The sequence control means includes
An alternating current alternating current characterized in that , based on the two combined command values output from the combined command generating means, generates a PWM pulse whose sequence is controlled so as not to cause a sudden change in each phase power supply voltage supplied to the load. Control device for direct conversion device. In a controller for an AC AC direct conversion device according to any one of claims 1-4,
AC / AC direct conversion device is a matrix converter that performs three-phase to three-phase conversion, and
The control apparatus for an AC / AC direct conversion apparatus, wherein the order control means controls the order of pulses in accordance with a magnitude relationship among a maximum phase voltage, an intermediate phase voltage, and a minimum phase voltage among three-phase power supply voltages .

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