WO2017034028A1 - Control method and control device for inverter, and inverter device - Google Patents

Control method and control device for inverter, and inverter device Download PDF

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Publication number
WO2017034028A1
WO2017034028A1 PCT/JP2016/075045 JP2016075045W WO2017034028A1 WO 2017034028 A1 WO2017034028 A1 WO 2017034028A1 JP 2016075045 W JP2016075045 W JP 2016075045W WO 2017034028 A1 WO2017034028 A1 WO 2017034028A1
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phase
inverter
semiconductor switching
voltage source
control method
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PCT/JP2016/075045
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French (fr)
Japanese (ja)
Inventor
小高 章弘
英俊 海田
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富士電機株式会社
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Priority to JP2017536493A priority Critical patent/JPWO2017034028A1/en
Publication of WO2017034028A1 publication Critical patent/WO2017034028A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to an inverter control method and control device for suppressing heat generation of a capacitor provided in a DC portion of the inverter, and an inverter device to which these control method or control device is applied.
  • FIG. 1 is a configuration diagram of a three-phase inverter.
  • the term “inverter” in the following description mainly indicates a main circuit having a DC voltage source and a plurality of semiconductor switching elements, and the entire apparatus including the “inverter” (main circuit) and a control device is referred to as “Inverter device ".
  • a capacitor C is connected in parallel to the DC voltage source B, and semiconductor switching elements U P , V P , W P , U N , such as IGBTs constituting a three-phase bridge circuit are connected to both ends of the capacitor C. V N and W N are connected.
  • a connection point between the switching elements of each phase is connected to a three-phase AC load M such as an electric motor via AC output terminals U, V, and W.
  • L is a reactor (a reactor that is intentionally connected or a floating reactor that is unintentionally present on the wiring), and P and N are a positive electrode and a negative electrode of the DC voltage source B.
  • E d is the voltage of the DC voltage source B
  • V c is the voltage of the capacitor C
  • I bat is the output current of the DC voltage source B
  • I c is the current flowing through the capacitor C
  • I dc is the current flowing through the DC portion of the inverter.
  • I u , I v , I w are the output currents of each phase.
  • the switching elements U P , V P , W P , U N , V N , and W N are turned on / off at a predetermined time ratio, so that the DC voltage has a desired frequency and magnitude. It is converted into phase AC voltage and supplied to the load M.
  • the switching elements U P, V P, W P , U N, V N, a method for turning on / off W N, the inverter control method in other words, a triangular wave and three-phase phase output voltage as a carrier switching elements U P is compared with the modulation signal corresponding to the command, V P, W P, U N, V N, a method of obtaining a drive signal (gate signal) W N are generally known.
  • This type of control method is disclosed as a PWM control method in Patent Literature 1 and Non-Patent Literature 1, for example.
  • FIG. 7 shows an example of an operation waveform when the switching elements U P to W N in FIG. 1 are turned on / off by a drive signal obtained by comparing a triangular wave as a carrier and a modulated signal of each phase. ing.
  • This operation waveform is obtained when the output currents I u , I v , and I w of each phase are sine waves and the power factor is 1.
  • the modulation signals V u , V v , and V w in FIG. 7 are based on so-called two-arm modulation or two-phase modulation, and this two-arm modulation is performed by turning on the switching element of one phase of the three phases over a certain period. This is well known as a modulation method for fixing the / off state and controlling the on / off of the remaining two-phase switching elements.
  • the detailed contents of the two-arm modulation are described in Non-Patent Document 1, for example, and thus the description thereof is omitted here.
  • the switching loss caused by switching on / off of the switching element can be suppressed while the three-phase output line voltage is maintained as a sine wave, and the voltage utilization rate of the inverter is reduced. Advantages such as improvement are obtained.
  • FIG. 8 shows an operation waveform when two-arm modulation is performed using a sawtooth wave for the carrier.
  • the operation in this case is basically the same as when a triangular wave is used for the carrier.
  • the current I dc flowing in the DC part of the inverter becomes a pulse train waveform with the switching elements U P to W N being turned on / off, and includes a DC component and an AC component.
  • a reactor L exists between the DC voltage source B and the capacitor C, and the current I dc flowing through the DC unit is supplied from the DC voltage source B and flows through the reactor L.
  • This is the sum of the current component I bat and the alternating current component I c supplied from the capacitor C. That is, the current I dc I bat + I c .
  • Non-Patent Document 2 discloses a technique for cooling the capacitor by thermally conducting the heat of the capacitor to a water-cooling jacket disposed around it as a cooling means for the capacitor in the inverter.
  • JP2013-183636A (FIG. 3 etc.)
  • the problem to be solved by the present invention is to reduce the current flowing in the capacitor of the DC part of the inverter and suppress the heat generation of the capacitor, and the inverter that enables downsizing and cost reduction of the entire apparatus including the main circuit and the cooling means. It is providing the control method and control apparatus of this, and an inverter apparatus.
  • a control method is provided with n (n is a plurality) series circuits of two semiconductor switching elements, and the n series circuits are all parallel to a DC voltage source.
  • An inverter control method comprising: connecting and connecting each of two semiconductor switching elements constituting the series circuit as a one-phase AC output terminal to each phase of an n-phase AC load; In a control method for outputting an n-phase AC voltage of a desired magnitude and frequency from the inverter by changing a time ratio of a DC voltage of the DC voltage source appearing at the AC output terminal by turning on / off a switching element.
  • An AC output terminal of at least one specific phase among n phases is maintained in a state where it is connected to a positive electrode or a negative electrode of the DC voltage source for a certain period, and an alternating current of another phase other than the specific phase among the n phases
  • the output terminal is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, and all the n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source within the predetermined period.
  • the semiconductor switching element of each phase is turned on / off so that the period of time to be shortened.
  • the control method according to claim 2 includes n (n is a plurality) series circuits of two semiconductor switching elements, the n series circuits are all connected in parallel to a DC voltage source, and the series circuit Is a control method for an inverter in which a connection point between two semiconductor switching elements constituting the circuit is connected to each phase of an n-phase AC load as a one-phase AC output terminal, and the semiconductor switching element is turned on / off.
  • An AC output terminal of at least one specific phase among the n phases is maintained in a state of being connected to the positive electrode or the negative electrode of the DC voltage source for a certain period within the operation period, and other than the specific phase among the n phases
  • the AC output terminal of the other phase is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, respectively
  • At least one cycle of the on / off cycle of the semiconductor switching element within the operation period is a cycle in which there is no state in which all n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source.
  • the semiconductor switching element of each phase is turned on / off.
  • the control method according to claim 3 is the inverter control method according to claim 1 or 2, Which phase of the AC output terminal is maintained in a state of being connected to the positive electrode or the negative electrode of the DC voltage source over a certain period, and whether the AC output terminal is connected to the positive electrode or the negative electrode of the DC voltage source, It is switched according to the phase or magnitude of the output voltage.
  • a control method is the inverter control method according to any one of claims 1 to 3,
  • a plurality of triangular waves are provided as a plurality of carriers having different phases, and each of n modulation signals corresponding to the n-phase output voltage command is converted into one carrier with a modulation signal corresponding to another phase other than the specific phase.
  • a control method is the inverter control method according to any one of claims 1 to 3,
  • a plurality of sawtooth waves are provided as a plurality of carriers having different waveforms, and each of n modulation signals corresponding to the n-phase output voltage command has one modulation signal corresponding to a phase other than the specific phase.
  • each of the n modulated signals is compared with the corresponding carrier, and the semiconductor switching element of the phase corresponding to each modulated signal is turned on / off The drive signal to be generated is generated.
  • the control method according to claim 6 is the inverter control method according to claim 4 or 5, Of the n modulated signals, the magnitude of at least one modulated signal selected according to the phase or magnitude of the output voltage is made equal to the maximum value or the minimum value of the carrier, and the magnitude of the modulated signal Whether the same value as the maximum value or the minimum value of the carrier is determined according to the phase or magnitude of the output voltage.
  • the control method according to claim 7 is the control method according to any one of claims 1 to 6 as a first control method
  • a control method for generating a drive signal for turning on / off an n-phase semiconductor switching element by comparing n modulation signals corresponding to the n-phase output voltage command with a single carrier is referred to as a second control method.
  • the first control method and the second control method are switched according to the phase or magnitude of the output voltage and the polarity or phase of the output current.
  • the control device includes n (n is a plurality) series circuits of two semiconductor switching elements, and the n series circuits are all connected in parallel to a DC voltage source, and the series circuit
  • the AC switching terminal is turned on / off by switching the semiconductor switching element of each inverter connected to each phase of the n-phase AC load using the connection point between the two semiconductor switching elements constituting the circuit as a one-phase AC output terminal.
  • the control device for outputting an n-phase AC voltage having a desired magnitude and frequency from the inverter by changing a time ratio of the DC voltage of the DC voltage source appearing in
  • An AC output terminal of at least one specific phase among n phases is maintained in a state where it is connected to a positive electrode or a negative electrode of the DC voltage source for a certain period, and an alternating current of another phase other than the specific phase among the n phases
  • the output terminal is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, and all the n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source within the predetermined period.
  • the semiconductor switching element of each phase is turned on / off so that the period of time to be shortened.
  • the control device includes n (n is a plurality) series circuits of two semiconductor switching elements, and the n series circuits are all connected in parallel to a DC voltage source, and the series circuit
  • the AC switching terminal is turned on / off by switching the semiconductor switching element of each inverter connected to each phase of the n-phase AC load using the connection point between the two semiconductor switching elements constituting the circuit as a one-phase AC output terminal.
  • At least one cycle of the on / off cycle of the semiconductor switching element within the operation period is a cycle in which there is no state in which all n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source.
  • the semiconductor switching element of each phase is turned on / off.
  • a control device is the control device for an inverter according to claim 8 or 9,
  • a carrier generating means for generating a plurality of triangular waves having different phases or a plurality of sawtooth waves having different waveforms as a plurality of carriers; According to the phase or magnitude of the output voltage, each of the n modulation signals corresponding to the n-phase output voltage command is not duplicated in one carrier with the modulation signal corresponding to the other phase other than the specific phase.
  • Modulation signal selection means corresponding to any of the plurality of carriers, Comparing means for comparing each of the n modulation signals selected by the modulation signal selection means with the corresponding carrier; The output signal of the comparison means is used to turn on / off the n-phase semiconductor switching element.
  • a control device is the control device for an inverter according to the tenth aspect, Of the plurality of carriers generated by the carrier generation means, further comprises a carrier selection means for giving the carrier selected according to the phase or magnitude of the output voltage and the polarity or phase of the output current to the comparison means, The comparison means turns on / off the n-phase semiconductor switching element using an output signal obtained by comparing the carrier selected by the carrier selection means and the n modulation signals.
  • the semiconductor switching element of each phase is turned on / off by the control method according to any one of the first to seventh aspects.
  • An inverter device according to claim 13 is one in which the semiconductor switching element of each phase is turned on / off by the control device according to any one of claims 8 to 11.
  • the current flowing through the capacitor in the DC part of the inverter is reduced to suppress the heat generation of the capacitor, thereby reducing the size and cost of the entire apparatus including the main circuit and the cooling means.
  • FIG. 5 is an operation waveform diagram at the time of two-arm modulation when a triangular wave is used for the first and second carriers in the first embodiment of the present invention. It is a wave form diagram which shows the computer simulation result of a prior art and 1st Embodiment. As a modification of the first embodiment, it is an operation waveform diagram during two-arm modulation when sawtooth waves are used for the first and second carriers.
  • FIG. It is a wave form diagram which shows the computer simulation result of prior art, 1st Embodiment, and 2nd Embodiment. It is a functional block diagram which shows the principal part of the control apparatus which concerns on embodiment of this invention.
  • An inverter to which each of the following embodiments is applied is, for example, a three-phase inverter as shown in FIG. 1, but as will be described later, the number of phases of the inverter to which the present invention is applied is particularly limited. is not.
  • FIG. 2 includes a triangular wave 1 and a triangular wave 2 as first and second carriers.
  • the triangular wave 1 and the triangular wave 2 are compared with a modulation signal corresponding to an output voltage command for each phase, and the inverter of FIG. It is an example of the operation waveform in the case of controlling.
  • the output currents I u , I v , I w of each phase flowing through the load M are sine waves and the power factor is 1.
  • the first embodiment is different from the prior art of FIG. 7 in that the present embodiment includes a triangular wave 1 and a triangular wave 2 having the same amplitude and different phases by 180 °, for example, period 1 (triangular wave 1, 2), the triangular wave 1 is compared with the two modulation signals V u and V v, and the triangular wave 2 and the modulation signal V w are compared, whereby the switching elements U P and V P shown in FIG. , W P , U N , V N , W N are determined on / off.
  • the switching element UP When the modulation signal V u ⁇ triangular wave 1, the switching element UP is turned on, and when the modulation signal V u ⁇ triangular wave 1, the switching element U N is turned on, When the modulation signal V v ⁇ triangular wave 1, the switching element VP is turned on. When the modulation signal V v ⁇ triangular wave 1, the switching element V N is turned on, For the modulation signal V w ⁇ triangular wave 2, turn on the switching elements W P, in the case of the modulation signal V w ⁇ triangular wave 2, the switching element W N ON, and.
  • the modulation signal whose magnitude is maintained at the maximum value or the minimum value of the triangular waves 1 and 2 is changed in accordance with the output voltage phase (or magnitude, the same applies hereinafter), and the modulation signal to be compared with the triangular wave 2 is also output. Change according to voltage phase. Specifically, as shown in FIG. 2, the modulation signal V u maintained at the maximum value of the triangular waves 1 and 2 ⁇ the modulation signal V w maintained at the minimum value of the triangular waves 1 and 2 ⁇ the maximum value of the triangular waves 1 and 2 is the modulated signal V v ⁇ ; varied as maintenance, modulation signal is also V w ⁇ V v ⁇ V u ⁇ ...... as the changing of comparing the triangular wave 2.
  • the magnitude of the modulation signal V u is maintained at the maximum value of the triangular wave 1, by turning on the switching elements U P, the output terminal U of the U-phase, the DC voltage source B Continue to be connected to the positive electrode P.
  • V-phase, W-phase output terminals V, W respectively, a triangular wave, 2 and the modulation signal V v, based on the magnitude relation between V w, on the switching elements V P or V N, the switching element W P or by turning on the W N, are alternately connected to the positive electrode P and a negative electrode N of the DC voltage source B.
  • the time ratios at which the V-phase and W-phase output terminals V and W are connected to the positive electrode P and the negative electrode N of the DC voltage source B within the period 1 respectively are as shown in FIG. This is the same as in the embodiment. That is, the U-phase, V-phase, and W-phase time average output voltages are the same in the conventional technique and the present embodiment.
  • the timing at which the output terminals V and W are connected to the positive electrode P or the negative electrode N of the DC voltage source B is different between the prior art of FIG. 7 and the present embodiment of FIG. What is more characteristic is that in the prior art of FIG. 7, there is a period in which all of the output terminals U, V, W are connected to the positive electrode P in the period 1, whereas in the present embodiment of FIG. There is no period in which all of U, V, and W are connected to the positive electrode P.
  • the direct current I dc when attention is paid to the direct current I dc , in the prior art of FIG. 7, the direct current I dc does not flow during the period in which all of the output terminals U, V, W are connected to the positive electrode P, and 0 Become.
  • FIG. 2 what was shown in FIG. 2 is an operation
  • the output terminals U, V, and W of all phases are simultaneously connected to the positive electrode P or the negative electrode N.
  • the output terminals U, V, and W are simultaneously connected.
  • the period is shorter than that of the prior art of FIG. 7, the same effect as in the case of FIG. 2 can be obtained.
  • At least one cycle of the on / off cycle of the semiconductor switching element within the operation period is a state in which all the n-phase AC output terminals U, V, W are simultaneously connected to the positive electrode P or the negative electrode N of the DC voltage source B. If the switching element of each phase is turned on / off so as to have a non-existing cycle, the direct current I dc does not become zero in the above-described at least one cycle, so that the amount of change in I dc becomes small and the current of the capacitor C I c is reduced, heat generation can be suppressed.
  • Table 1 summarizes an example of the control operation of the present embodiment.
  • the electrical angles described in the table are based on the U-phase modulation signal V u , and are based on the premise that the U-phase modulation signal V u is maximized when the electrical angle is 0 °.
  • FIG. 3 is a waveform diagram showing computer simulation results of the prior art and the present embodiment, where (a) is the prior art and (b) is the present embodiment.
  • the current delay angle 0 ° (load power factor: 1.0)
  • the symbols attached to the waveforms in the figure are the same as the current and voltage symbols described so far.
  • FIG. 3 also shows the result of calculating the effective value I dcacrms of the alternating current component I c of the direct current I dc with the period of the triangular wave as the basic period.
  • the effective value I dcacrms of the AC component I c of the DC current I dc is reduced, that is, flows to the capacitor C. it can be seen that the effective value of the current I c is decreased.
  • the modulation signal has been compared to the modulation signal V w and the triangular wave 2, to be compared of the triangular wave 2, the maximum value of the triangular wave 1 Alternatively, it may be other than the modulation signal maintained at the minimum value. Therefore, in the period of the electrical angle 0 ° ⁇ 30 °, the modulation signal V v compared with the triangular wave 2, the modulation signal V w may be compared with the triangular wave 1. The same applies to other electrical angle ranges.
  • FIG. 4 is an operation waveform diagram showing a modification of the first embodiment.
  • sawtooth waves 1 and 2 having the same amplitude and different waveforms are used as the first and second carriers instead of the triangular waves 1 and 2.
  • the sawtooth wave 1 is a sawtooth wave that increases with time
  • the sawtooth wave 2 is a sawtooth wave that decreases with time.
  • the amount of change in the direct current I dc in FIG. 4 is smaller than that in the prior art in FIG. 8, and the AC component included in the direct current I dc , that is, I c flowing through the capacitor C is reduced. Heat generation of the capacitor C can be suppressed.
  • FIG. 5 is an operation waveform diagram showing the computer simulation result of the second embodiment of the control method according to the present invention in comparison with the prior art and the first embodiment, (a) is the prior art, ( b) is the first embodiment, and (c) is the second embodiment.
  • the current delay angle is set to 45 ° (load power factor: 0.71), and the symbols attached to the waveforms in the figure are the same as the symbols of current and voltage described so far.
  • FIG. 5 also shows the result of calculating the effective value I dcacrms of the alternating current component I c of the direct current I dc with the period of the triangular wave as the basic period.
  • the effective value I dcacrms of the AC component I c of the DC current I dc is increased in FIG. 5B .
  • the load power factor is lower in the simulation condition of FIG. 5 (load power factor: 0.71) than the load power factor condition ((load power factor: 1.0) in the first embodiment described above.
  • the control method of the first embodiment has no meaning to be applied when the load power factor is bad.
  • a comparison is made with the first and second carriers (for example, triangular waves 1 and 2) according to the output voltage phase and output current polarity (or phase, the same applies hereinafter) of the inverter.
  • the phase of the modulated signal of each phase is changed, and the phase of the modulated signal of each phase that maintains the maximum or minimum value of the first and second carriers is changed I decided to change it.
  • the two carriers and the modulation signal of each phase are not compared, but a single carrier and all of them are compared as in the prior art of FIG.
  • the phase modulation signals V u , V v , and V w are respectively compared.
  • Table 2 below shows the modulation signal to be compared with the triangular waves 1 and 2 according to the output voltage phase and output current polarity, the modulation signal whose magnitude is maintained at the maximum value or the minimum value of the triangular wave, and the modulation It shows whether the magnitude of the signal is maintained at the maximum value or the minimum value of the triangular wave.
  • the electrical angle described in the table is based on the U-phase modulation signal V u , and is a premise that the U-phase modulation signal V u becomes maximum when the electrical angle is 0 °.
  • the output current polarity described in Table 2 is “+” when current flows from the inverter toward the load M.
  • the mode described as “conventional” in the remarks column of Table 2 is a mode for comparing a single triangular wave with all-phase modulation signals V u , V v , and V w .
  • FIG. 5C shows a simulation result when the on / off state of the switching element is determined by selecting the modulation signals V u , V v , V w and the triangular waves 1, 2 according to Table 2.
  • FIG. 5C is compared with the prior art of FIG. 5A, it can be seen that the effective value I dcacrms of the AC component I c of the DC current I dc is reduced.
  • 5A and 5C are different in the waveforms of the modulation signals V u , V v , and V w , this is because the modulation signal of a predetermined phase is corrected as described above. The same value is obtained for the output line voltage between the UV phase, the VW phase, and the WU phase.
  • the second embodiment even when the load power factor is low, the current flowing through the capacitor can be reduced while obtaining the same output line voltage, and the heat generation can be suppressed.
  • the second embodiment is also applicable to the case where sawtooth waves 1 and 2 are used instead of triangular waves 1 and 2.
  • FIG. 6 is a functional block diagram showing a main part of the control device for realizing the first and second embodiments of the control method described above.
  • This control device is for a three-phase inverter and uses two triangular waves for the carrier.
  • the modulation signal selection means 10 includes modulation signals V u , V v , V w for each phase, an output voltage phase (or magnitude) based on a certain phase (for example, U phase), and each phase. Output current polarity (or phase).
  • triangular wave 1 and triangular wave 2 having the same amplitude and different 180 ° phase are output from the carrier generating means 20, and these triangular wave 1 and triangular wave 2 are carrier-selected together with the output voltage phase and output current polarity. Input to means 30.
  • the triangular wave 1 and the triangular wave 2 are output to the comparison means 41 and the comparison means 42, respectively.
  • the comparison means 41 the two phases selected by the modulation signal selection means 10 are output.
  • the modulation signal is compared with the triangular wave 1
  • the comparison means 42 compares the remaining one phase modulation signal selected by the modulation signal selection means 10 with the triangular wave 2 (or triangular wave 1).
  • the drive signal based on the output of the comparison means 41, comparison means 42, the switching elements U P of the inverter Figure 1, V P, W P, so as to be respectively distributed to the U N, V N, W N Yes.
  • the carrier selection unit 30 outputs the triangular wave 1 to the comparison unit 41 and the triangular wave 2 to the comparison unit 42.
  • the modulation signal selection means 10 outputs a predetermined two-phase modulation signal and a predetermined one-phase modulation signal to the comparison means 41 and 42, respectively, according to the output voltage phase based on Table 1.
  • the comparison means 41 and 42 compare the inputted modulation signal of each phase with the triangular wave 1 or the triangular wave 2 to generate driving signals for the switching elements U P to W N.
  • the triangular wave maximum value / minimum value maintaining modulation signal in Table 1 is one of the two modulation signals input to the comparison means 41.
  • the carrier selecting means 30 is based on Table 2 and the triangular wave 1 is compared to the comparing means 41 and the triangular wave 2 (or triangular wave 1) is compared according to the output voltage phase and output current polarity. 42 respectively.
  • the mode in which the triangular wave 1 is output to the comparison means 42 is the case where the output current polarity is “other than the above” in Table 2 and “conventional” is described in the remarks column.
  • a single triangular wave that is, a triangular wave 1 is supplied to the comparison means 41 and 42, whereby the modulation signals V u , V v and V w of all phases are compared with the single triangular wave 1.
  • the modulation signal selection unit 10 outputs a predetermined two-phase modulation signal and a predetermined one-phase modulation signal to the comparison units 41 and 42 according to the output voltage phase and the output current polarity, respectively.
  • the comparison means 41 and 42 compare the input modulation signal of a predetermined phase with the triangular wave 1 and the triangular wave 2 or when only the single triangular wave 1 is compared when performing the same control method as the conventional one, Drive signals for the switching elements U P to W N are generated.
  • each function of the control device shown in FIG. 6 can be realized by an arithmetic processing device such as a microcomputer and a program mounted thereon.
  • the semiconductor elements (switching elements and diodes) of the inverter to which the above embodiments are applied include not only conventional semiconductor elements made of silicon but also SiC (silicon carbide) that can be used in a high temperature environment.
  • SiC silicon carbide
  • a wide band gap semiconductor element using may be used. In this case, the response to the high temperature environment remains as a problem for the peripheral parts of the wide band gap semiconductor element.
  • the present invention since the heat generation of the capacitor in the DC part of the inverter is suppressed, Sometimes it can be used.
  • the present invention can be used for a control method and a control device for a single-phase inverter, a multi-phase inverter other than a three-phase inverter, and an inverter device controlled using these control methods or control devices.
  • B direct-current voltage source
  • C Capacitor L: Reactor U P, V P, W P , U N, V N, W N: semiconductor switching element M: the three-phase AC load P: positive N: negative U, V, W: AC output terminal 10: modulation signal selection means 20: carrier generation means 30: carrier selection means 41, 42: comparison means

Abstract

Provided are a control method, a control device and an inverter device that can suppress the heat generated by a capacitor of a direct-current part of an inverter, reduce the overall size of a device and reduce costs. The control method causes an n phase (for example, three phase) alternating-current voltage of a desired size and frequency to be output from an inverter by changing a direct-current voltage time ratio of a direct-current voltage source B that appears at alternating-current output terminals U, V, W by switching semiconductor switching elements UP-WN on and off. The switching elements UP-WN are switched on/off so that a state in which an alternating-current output terminal of one phase is connected to the positive terminal or negative terminal of the direct-current voltage source B is maintained for a fixed period of time, so that an alternating-current output terminal of another phase is connected to the negative terminal or positive terminal of the direct-current voltage source B for a period of time shorter than the fixed period of time, and so that a period of time in which all of the alternating-current output terminals U, V, W are simultaneously connected to the positive terminal or negative terminal of the direct-current voltage source B is minimized in the fixed period of time.

Description

インバータの制御方法及び制御装置、並びにインバータ装置INVERTER CONTROL METHOD AND CONTROL DEVICE, AND INVERTER DEVICE
 本発明は、インバータの直流部に設けられるコンデンサの発熱を抑制するためのインバータの制御方法及び制御装置、並びに、これらの制御方法または制御装置が適用されるインバータ装置に関するものである。 The present invention relates to an inverter control method and control device for suppressing heat generation of a capacitor provided in a DC portion of the inverter, and an inverter device to which these control method or control device is applied.
 図1は、三相インバータの構成図である。なお、以下の説明における用語「インバータ」は、主に直流電圧源と複数の半導体スイッチング素子とを有する主回路を示し、この「インバータ」(主回路)と制御装置とを備えた装置全体を「インバータ装置」というものとする。
 図1において、直流電圧源BにはコンデンサCが並列に接続され、コンデンサCの両端には、三相ブリッジ回路を構成するIGBT等の半導体スイッチング素子U,V,W,U,V,Wが接続されている。各相のスイッチング素子同士の接続点は、交流出力端子U,V,Wを介して電動機等の三相交流負荷Mに接続されている。
FIG. 1 is a configuration diagram of a three-phase inverter. The term “inverter” in the following description mainly indicates a main circuit having a DC voltage source and a plurality of semiconductor switching elements, and the entire apparatus including the “inverter” (main circuit) and a control device is referred to as “ Inverter device ".
In FIG. 1, a capacitor C is connected in parallel to the DC voltage source B, and semiconductor switching elements U P , V P , W P , U N , such as IGBTs constituting a three-phase bridge circuit are connected to both ends of the capacitor C. V N and W N are connected. A connection point between the switching elements of each phase is connected to a three-phase AC load M such as an electric motor via AC output terminals U, V, and W.
 図1において、Lはリアクトル(意図的に接続したリアクトル、または、意図せずに配線上に存在する浮遊リアクトル)、P,Nは直流電圧源Bの正極,負極である。また、Eは直流電圧源Bの電圧、VはコンデンサCの電圧、Ibatは直流電圧源Bの出力電流、IはコンデンサCを流れる電流、Idcはインバータの直流部を流れる電流、I,I,Iは各相の出力電流である。 In FIG. 1, L is a reactor (a reactor that is intentionally connected or a floating reactor that is unintentionally present on the wiring), and P and N are a positive electrode and a negative electrode of the DC voltage source B. E d is the voltage of the DC voltage source B, V c is the voltage of the capacitor C, I bat is the output current of the DC voltage source B, I c is the current flowing through the capacitor C, and I dc is the current flowing through the DC portion of the inverter. , I u , I v , I w are the output currents of each phase.
 この三相インバータでは、スイッチング素子U,V,W,U,V,Wを所定の時間比率でオン/オフさせることにより、直流電圧を所望の周波数及び大きさを有する三相交流電圧に変換し、負荷Mに供給している。
 ここで、スイッチング素子U,V,W,U,V,Wをオン/オフさせる方法、言い換えればインバータの制御方法としては、キャリアとしての三角波と三相各相の出力電圧指令に相当する変調信号とを比較してスイッチング素子U,V,W,U,V,Wの駆動信号(ゲート信号)を得る方法が一般に知られている。この種の制御方法は、例えば特許文献1や非特許文献1にPWM制御方法として開示されている。
In this three-phase inverter, the switching elements U P , V P , W P , U N , V N , and W N are turned on / off at a predetermined time ratio, so that the DC voltage has a desired frequency and magnitude. It is converted into phase AC voltage and supplied to the load M.
Here, the switching elements U P, V P, W P , U N, V N, a method for turning on / off W N, the inverter control method in other words, a triangular wave and three-phase phase output voltage as a carrier switching elements U P is compared with the modulation signal corresponding to the command, V P, W P, U N, V N, a method of obtaining a drive signal (gate signal) W N are generally known. This type of control method is disclosed as a PWM control method in Patent Literature 1 and Non-Patent Literature 1, for example.
 なお、図7は、キャリアとしての三角波と各相の変調信号とを比較して得た駆動信号により図1のスイッチング素子U~Wをオン/オフさせた場合の動作波形の一例を示している。この動作波形は、各相の出力電流I,I,Iが正弦波であり、力率を1とした場合のものである。 FIG. 7 shows an example of an operation waveform when the switching elements U P to W N in FIG. 1 are turned on / off by a drive signal obtained by comparing a triangular wave as a carrier and a modulated signal of each phase. ing. This operation waveform is obtained when the output currents I u , I v , and I w of each phase are sine waves and the power factor is 1.
 図7の変調信号V,V,Vは、いわゆる2アーム変調または二相変調によるものであり、この2アーム変調は、一定期間にわたり、三相のうちの一相のスイッチング素子のオン/オフ状態を固定して残り二相のスイッチング素子のオン/オフを制御する変調方式として良く知られている。2アーム変調の詳細な内容については、例えば非特許文献1に記載されているため、ここでは説明を省略する。
 インバータを2アーム変調により制御すると、三相の出力線間電圧を正弦波に維持しつつ、スイッチング素子のオン/オフに伴って生じるスイッチング損失を抑制することができ、しかもインバータの電圧利用率が向上する等の利点が得られる。
The modulation signals V u , V v , and V w in FIG. 7 are based on so-called two-arm modulation or two-phase modulation, and this two-arm modulation is performed by turning on the switching element of one phase of the three phases over a certain period. This is well known as a modulation method for fixing the / off state and controlling the on / off of the remaining two-phase switching elements. The detailed contents of the two-arm modulation are described in Non-Patent Document 1, for example, and thus the description thereof is omitted here.
When the inverter is controlled by two-arm modulation, the switching loss caused by switching on / off of the switching element can be suppressed while the three-phase output line voltage is maintained as a sine wave, and the voltage utilization rate of the inverter is reduced. Advantages such as improvement are obtained.
 また、図8は、キャリアに鋸歯状波を用いて2アーム変調を行った時の動作波形である。この場合の動作は、キャリアに三角波を用いた場合と基本的に同一である。 FIG. 8 shows an operation waveform when two-arm modulation is performed using a sawtooth wave for the carrier. The operation in this case is basically the same as when a triangular wave is used for the carrier.
 図7,図8によれば、スイッチング素子U~Wのオン/オフに伴って、インバータの直流部に流れる電流Idcはパルス列状の波形となり、直流成分と交流成分とが含まれていることが判る。
 図1に示したように、直流電圧源BとコンデンサCとの間にはリアクトルLが存在しており、直流部に流れる電流Idcは、直流電圧源Bから供給されてリアクトルLを流れる直流電流成分Ibatと、コンデンサCから供給される交流電流成分Iとの和になる。すなわち、電流Idc=Ibat+Iである。
According to FIG. 7 and FIG. 8, the current I dc flowing in the DC part of the inverter becomes a pulse train waveform with the switching elements U P to W N being turned on / off, and includes a DC component and an AC component. I know that.
As shown in FIG. 1, a reactor L exists between the DC voltage source B and the capacitor C, and the current I dc flowing through the DC unit is supplied from the DC voltage source B and flows through the reactor L. This is the sum of the current component I bat and the alternating current component I c supplied from the capacitor C. That is, the current I dc = I bat + I c .
 この時、コンデンサCは、上記の交流電流成分Iが流れることに伴う自己発熱によって温度が上昇する。一般にコンデンサは、温度が高くなると寿命が短くなることから、温度の上昇を抑制するためには、必要以上に大型(大容量)のコンデンサを使用する、または、コンデンサを積極的に冷却するための冷却手段を備える等の対策が必要となる。
 なお、非特許文献2には、インバータ内のコンデンサの冷却手段として、コンデンサの熱をその周囲に配置された水冷ジャケットに熱伝導させて冷却する技術が開示されている。
At this time, the capacitor C, the temperature rises due to self-heating due to the above-mentioned alternating current component I c flows. Capacitors generally have a shorter life as the temperature rises. Therefore, to suppress the rise in temperature, use a capacitor that is larger (larger capacity) than necessary, or actively cool the capacitor. It is necessary to take measures such as providing cooling means.
Note that Non-Patent Document 2 discloses a technique for cooling the capacitor by thermally conducting the heat of the capacitor to a water-cooling jacket disposed around it as a cooling means for the capacitor in the inverter.
特開2013-183636号公報(図3等)JP2013-183636A (FIG. 3 etc.)
 上記のように、従来においては、インバータの直流部に設けられたコンデンサの発熱を抑制し、または冷却するための対策が必要であり、これが装置の小型化や低コスト化の妨げとなっていた。
 そこで、本発明の解決課題は、インバータの直流部のコンデンサに流れる電流を減少させてコンデンサの発熱を抑制し、主回路や冷却手段を含む装置全体の小型化、低コスト化を可能にしたインバータの制御方法及び制御装置、並びにインバータ装置を提供することにある。
As described above, conventionally, it is necessary to take measures for suppressing or cooling the heat generation of the capacitor provided in the DC portion of the inverter, which hinders downsizing and cost reduction of the device. .
Therefore, the problem to be solved by the present invention is to reduce the current flowing in the capacitor of the DC part of the inverter and suppress the heat generation of the capacitor, and the inverter that enables downsizing and cost reduction of the entire apparatus including the main circuit and the cooling means. It is providing the control method and control apparatus of this, and an inverter apparatus.
 上記課題を解決するため、請求項1に係る制御方法は、二つの半導体スイッチング素子の直列回路をn(nは複数)個備え、前記n個の直列回路を直流電圧源に対して全て並列に接続すると共に、前記直列回路を構成する二つの半導体スイッチング素子同士の接続点を一相の交流出力端子としてn相交流負荷の各相にそれぞれ接続してなるインバータの制御方法であって、前記半導体スイッチング素子をオン/オフさせて前記交流出力端子に現れる前記直流電圧源の直流電圧の時間比率を変化させることにより、前記インバータから所望の大きさ及び周波数のn相交流電圧を出力させる制御方法において、
 n相のうち少なくとも特定の一相の交流出力端子が一定期間にわたって前記直流電圧源の正極または負極に接続される状態を維持し、かつ、n相のうち前記特定の相以外の他相の交流出力端子が前記一定期間より短い期間にわたって前記直流電圧源の負極または正極にそれぞれ接続されると共に、前記一定期間内で、n相全ての交流出力端子が前記直流電圧源の正極または負極に同時に接続される期間が短くなるように、各相の前記半導体スイッチング素子をオン/オフさせるものである。
In order to solve the above-mentioned problem, a control method according to claim 1 is provided with n (n is a plurality) series circuits of two semiconductor switching elements, and the n series circuits are all parallel to a DC voltage source. An inverter control method comprising: connecting and connecting each of two semiconductor switching elements constituting the series circuit as a one-phase AC output terminal to each phase of an n-phase AC load; In a control method for outputting an n-phase AC voltage of a desired magnitude and frequency from the inverter by changing a time ratio of a DC voltage of the DC voltage source appearing at the AC output terminal by turning on / off a switching element. ,
An AC output terminal of at least one specific phase among n phases is maintained in a state where it is connected to a positive electrode or a negative electrode of the DC voltage source for a certain period, and an alternating current of another phase other than the specific phase among the n phases The output terminal is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, and all the n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source within the predetermined period. The semiconductor switching element of each phase is turned on / off so that the period of time to be shortened.
 請求項2に係る制御方法は、二つの半導体スイッチング素子の直列回路をn(nは複数)個備え、前記n個の直列回路を直流電圧源に対して全て並列に接続すると共に、前記直列回路を構成する二つの半導体スイッチング素子同士の接続点を一相の交流出力端子としてn相交流負荷の各相にそれぞれ接続してなるインバータの制御方法であって、前記半導体スイッチング素子をオン/オフさせて前記交流出力端子に現れる前記直流電圧源の直流電圧の時間比率を変化させることにより、前記インバータから所望の大きさ及び周波数のn相交流電圧を出力させる制御方法において、
 n相のうち少なくとも特定の一相の交流出力端子が動作期間内の一定期間にわたって前記直流電圧源の正極または負極に接続される状態を維持し、かつ、n相のうち前記特定の相以外の他相の交流出力端子が前記一定期間より短い期間にわたって前記直流電圧源の負極または正極にそれぞれ接続されると共に、
 前記動作期間内における前記半導体スイッチング素子のオン/オフ周期の少なくとも1周期が、n相全ての交流出力端子が前記直流電圧源の正極または負極に同時に接続される状態が存在しない周期となるように、各相の前記半導体スイッチング素子をオン/オフさせるものである。
The control method according to claim 2 includes n (n is a plurality) series circuits of two semiconductor switching elements, the n series circuits are all connected in parallel to a DC voltage source, and the series circuit Is a control method for an inverter in which a connection point between two semiconductor switching elements constituting the circuit is connected to each phase of an n-phase AC load as a one-phase AC output terminal, and the semiconductor switching element is turned on / off. In the control method of outputting an n-phase AC voltage having a desired magnitude and frequency from the inverter by changing a time ratio of the DC voltage of the DC voltage source appearing at the AC output terminal.
An AC output terminal of at least one specific phase among the n phases is maintained in a state of being connected to the positive electrode or the negative electrode of the DC voltage source for a certain period within the operation period, and other than the specific phase among the n phases The AC output terminal of the other phase is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, respectively,
At least one cycle of the on / off cycle of the semiconductor switching element within the operation period is a cycle in which there is no state in which all n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source. The semiconductor switching element of each phase is turned on / off.
 請求項3に係る制御方法は、請求項1または2に記載したインバータの制御方法において、
 どの相の交流出力端子を一定期間にわたって前記直流電圧源の正極または負極に接続した状態に維持するか、及び、当該交流出力端子を前記直流電圧源の正極または負極の何れに接続するかを、出力電圧の位相または大きさに応じて切り替えるものである。
The control method according to claim 3 is the inverter control method according to claim 1 or 2,
Which phase of the AC output terminal is maintained in a state of being connected to the positive electrode or the negative electrode of the DC voltage source over a certain period, and whether the AC output terminal is connected to the positive electrode or the negative electrode of the DC voltage source, It is switched according to the phase or magnitude of the output voltage.
 請求項4に係る制御方法は、請求項1~3の何れか1項に記載したインバータの制御方法において、
 位相が異なる複数のキャリアとして複数の三角波を備え、前記n相の出力電圧指令に相当するn個の変調信号のそれぞれを、前記特定の相以外の他相に相当する変調信号が一つのキャリアに重複しないように前記複数のキャリアの何れかに対応させ、前記n個の変調信号のそれぞれを前記対応させたキャリアと比較してそれぞれが相当する相の半導体スイッチング素子をオン/オフさせる駆動信号を生成するものである。
A control method according to claim 4 is the inverter control method according to any one of claims 1 to 3,
A plurality of triangular waves are provided as a plurality of carriers having different phases, and each of n modulation signals corresponding to the n-phase output voltage command is converted into one carrier with a modulation signal corresponding to another phase other than the specific phase. A drive signal that corresponds to any of the plurality of carriers so as not to overlap, compares each of the n modulated signals with the corresponding carrier, and turns on / off the semiconductor switching element of the corresponding phase. Is to be generated.
 請求項5に係る制御方法は、請求項1~3の何れか1項に記載したインバータの制御方法において、
 波形が異なる複数のキャリアとして複数の鋸歯状波を備え、前記n相の出力電圧指令に相当するn個の変調信号のそれぞれを、前記特定の相以外の他相に相当する変調信号が一つのキャリアに重複しないように前記複数のキャリアの何れかに対応させ、前記n個の変調信号のそれぞれを前記対応させたキャリアと比較して各変調信号に相当する相の半導体スイッチング素子をオン/オフさせる駆動信号を生成するものである。
A control method according to claim 5 is the inverter control method according to any one of claims 1 to 3,
A plurality of sawtooth waves are provided as a plurality of carriers having different waveforms, and each of n modulation signals corresponding to the n-phase output voltage command has one modulation signal corresponding to a phase other than the specific phase. Corresponding to one of the plurality of carriers so as not to overlap the carrier, each of the n modulated signals is compared with the corresponding carrier, and the semiconductor switching element of the phase corresponding to each modulated signal is turned on / off The drive signal to be generated is generated.
 請求項6に係る制御方法は、請求項4または5に記載したインバータの制御方法において、
 n個の変調信号のうち、出力電圧の位相または大きさに応じて選択された少なくとも1個の変調信号の大きさを前記キャリアの最大値または最小値と同一にし、かつ、当該変調信号の大きさを前記キャリアの最大値または最小値の何れと同一にするかも、出力電圧の位相または大きさに応じて決定するものである。
The control method according to claim 6 is the inverter control method according to claim 4 or 5,
Of the n modulated signals, the magnitude of at least one modulated signal selected according to the phase or magnitude of the output voltage is made equal to the maximum value or the minimum value of the carrier, and the magnitude of the modulated signal Whether the same value as the maximum value or the minimum value of the carrier is determined according to the phase or magnitude of the output voltage.
 請求項7に係る制御方法は、請求項1~6の何れか1項に記載した制御方法を第1の制御方法とし、
 前記n相の出力電圧指令に相当するn個の変調信号を単一のキャリアとそれぞれ比較してn相の半導体スイッチング素子をオン/オフさせる駆動信号を生成する制御方法を第2の制御方法とし、
 出力電圧の位相または大きさ、及び、出力電流の極性または位相に応じて、前記第1の制御方法と前記第2の制御方法とを切り替えるものである。
The control method according to claim 7 is the control method according to any one of claims 1 to 6 as a first control method,
A control method for generating a drive signal for turning on / off an n-phase semiconductor switching element by comparing n modulation signals corresponding to the n-phase output voltage command with a single carrier is referred to as a second control method. ,
The first control method and the second control method are switched according to the phase or magnitude of the output voltage and the polarity or phase of the output current.
 請求項8に係る制御装置は、二つの半導体スイッチング素子の直列回路をn(nは複数)個備え、前記n個の直列回路を直流電圧源に対して全て並列に接続すると共に、前記直列回路を構成する二つの半導体スイッチング素子同士の接続点を一相の交流出力端子としてn相交流負荷の各相にそれぞれ接続してなるインバータの、前記半導体スイッチング素子をオン/オフさせて前記交流出力端子に現れる前記直流電圧源の直流電圧の時間比率を変化させることにより、所望の大きさ及び周波数のn相交流電圧を前記インバータから出力させるための制御装置において、
 n相のうち少なくとも特定の一相の交流出力端子が一定期間にわたって前記直流電圧源の正極または負極に接続される状態を維持し、かつ、n相のうち前記特定の相以外の他相の交流出力端子が前記一定期間より短い期間にわたって前記直流電圧源の負極または正極にそれぞれ接続されると共に、前記一定期間内で、n相全ての交流出力端子が前記直流電圧源の正極または負極に同時に接続される期間が短くなるように、各相の前記半導体スイッチング素子をオン/オフさせるものである。
The control device according to claim 8 includes n (n is a plurality) series circuits of two semiconductor switching elements, and the n series circuits are all connected in parallel to a DC voltage source, and the series circuit The AC switching terminal is turned on / off by switching the semiconductor switching element of each inverter connected to each phase of the n-phase AC load using the connection point between the two semiconductor switching elements constituting the circuit as a one-phase AC output terminal. In the control device for outputting an n-phase AC voltage having a desired magnitude and frequency from the inverter by changing a time ratio of the DC voltage of the DC voltage source appearing in
An AC output terminal of at least one specific phase among n phases is maintained in a state where it is connected to a positive electrode or a negative electrode of the DC voltage source for a certain period, and an alternating current of another phase other than the specific phase among the n phases The output terminal is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, and all the n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source within the predetermined period. The semiconductor switching element of each phase is turned on / off so that the period of time to be shortened.
 請求項9に係る制御装置は、二つの半導体スイッチング素子の直列回路をn(nは複数)個備え、前記n個の直列回路を直流電圧源に対して全て並列に接続すると共に、前記直列回路を構成する二つの半導体スイッチング素子同士の接続点を一相の交流出力端子としてn相交流負荷の各相にそれぞれ接続してなるインバータの、前記半導体スイッチング素子をオン/オフさせて前記交流出力端子に現れる前記直流電圧源の直流電圧の時間比率を変化させることにより、所望の大きさ及び周波数のn相交流電圧を前記インバータから出力させるための制御装置において、
 n相のうち少なくとも特定の一相の交流出力端子が動作期間内の一定期間にわたって前記直流電圧源の正極または負極に接続される状態を維持し、かつ、n相のうち前記特定の相以外の他相の交流出力端子が前記一定期間より短い期間にわたって前記直流電圧源の負極または正極にそれぞれ接続されると共に、
 前記動作期間内における前記半導体スイッチング素子のオン/オフ周期の少なくとも1周期が、n相全ての交流出力端子が前記直流電圧源の正極または負極に同時に接続される状態が存在しない周期となるように、各相の前記半導体スイッチング素子をオン/オフさせるものである。
The control device according to claim 9 includes n (n is a plurality) series circuits of two semiconductor switching elements, and the n series circuits are all connected in parallel to a DC voltage source, and the series circuit The AC switching terminal is turned on / off by switching the semiconductor switching element of each inverter connected to each phase of the n-phase AC load using the connection point between the two semiconductor switching elements constituting the circuit as a one-phase AC output terminal. In the control device for outputting an n-phase AC voltage having a desired magnitude and frequency from the inverter by changing a time ratio of the DC voltage of the DC voltage source appearing in
An AC output terminal of at least one specific phase among the n phases is maintained in a state of being connected to the positive electrode or the negative electrode of the DC voltage source for a certain period within the operation period, and other than the specific phase among the n phases The AC output terminal of the other phase is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, respectively,
At least one cycle of the on / off cycle of the semiconductor switching element within the operation period is a cycle in which there is no state in which all n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source. The semiconductor switching element of each phase is turned on / off.
 請求項10に係る制御装置は、請求項8または9に記載したインバータの制御装置において、
 位相が異なる複数の三角波または波形が異なる複数の鋸歯状波を複数のキャリアとして発生するキャリア発生手段と、
 出力電圧の位相または大きさに応じて、前記n相の出力電圧指令に相当するn個の変調信号のそれぞれを、前記特定の相以外の他相に相当する変調信号が一つのキャリアに重複しないように前記複数のキャリアの何れかに対応させる変調信号選択手段と、
 前記変調信号選択手段により選択された前記n個の変調信号のそれぞれを前記対応させたキャリアと比較する比較手段と、を備え、
 前記比較手段の出力信号を用いて、前記n相の半導体スイッチング素子をオン/オフさせるものである。
A control device according to claim 10 is the control device for an inverter according to claim 8 or 9,
A carrier generating means for generating a plurality of triangular waves having different phases or a plurality of sawtooth waves having different waveforms as a plurality of carriers;
According to the phase or magnitude of the output voltage, each of the n modulation signals corresponding to the n-phase output voltage command is not duplicated in one carrier with the modulation signal corresponding to the other phase other than the specific phase. Modulation signal selection means corresponding to any of the plurality of carriers,
Comparing means for comparing each of the n modulation signals selected by the modulation signal selection means with the corresponding carrier;
The output signal of the comparison means is used to turn on / off the n-phase semiconductor switching element.
 請求項11に係る制御装置は、請求項10に記載したインバータの制御装置において、
 前記キャリア発生手段により発生させた複数のキャリアのうち、出力電圧の位相または大きさ、及び、出力電流の極性または位相に応じて選択したキャリアを前記比較手段に与えるキャリア選択手段を更に備え、
 前記比較手段が、前記キャリア選択手段により選択されたキャリアと前記n個の変調信号とを比較して得た出力信号を用いて、前記n相の半導体スイッチング素子をオン/オフさせるものである。
A control device according to an eleventh aspect is the control device for an inverter according to the tenth aspect,
Of the plurality of carriers generated by the carrier generation means, further comprises a carrier selection means for giving the carrier selected according to the phase or magnitude of the output voltage and the polarity or phase of the output current to the comparison means,
The comparison means turns on / off the n-phase semiconductor switching element using an output signal obtained by comparing the carrier selected by the carrier selection means and the n modulation signals.
 請求項12に係るインバータ装置は、請求項1~7の何れか1項に記載した制御方法により、各相の前記半導体スイッチング素子がオン/オフされるものである。
 また、請求項13に係るインバータ装置は、請求項8~11の何れか1項に記載した制御装置により、各相の前記半導体スイッチング素子がオン/オフされるものである。
According to a twelfth aspect of the invention, the semiconductor switching element of each phase is turned on / off by the control method according to any one of the first to seventh aspects.
An inverter device according to claim 13 is one in which the semiconductor switching element of each phase is turned on / off by the control device according to any one of claims 8 to 11.
 本発明によれば、インバータの直流部のコンデンサに流れる電流を減少させてコンデンサの発熱を抑制し、これによって主回路や冷却手段を含む装置全体の小型化、低コスト化を図ることができる。 According to the present invention, the current flowing through the capacitor in the DC part of the inverter is reduced to suppress the heat generation of the capacitor, thereby reducing the size and cost of the entire apparatus including the main circuit and the cooling means.
三相インバータ(主回路)の構成図である。It is a block diagram of a three-phase inverter (main circuit). 本発明の第1実施形態において、第1,第2のキャリアに三角波を用いた場合の2アーム変調時の動作波形図である。FIG. 5 is an operation waveform diagram at the time of two-arm modulation when a triangular wave is used for the first and second carriers in the first embodiment of the present invention. 従来技術及び第1実施形態のコンピュータシミュレーション結果を示す波形図である。It is a wave form diagram which shows the computer simulation result of a prior art and 1st Embodiment. 第1実施形態の変形例として、第1,第2のキャリアに鋸歯状波を用いた場合の2アーム変調時の動作波形図である。As a modification of the first embodiment, it is an operation waveform diagram during two-arm modulation when sawtooth waves are used for the first and second carriers. FIG. 従来技術、第1実施形態及び第2実施形態のコンピュータシミュレーション結果を示す波形図である。It is a wave form diagram which shows the computer simulation result of prior art, 1st Embodiment, and 2nd Embodiment. 本発明の実施形態に係る制御装置の主要部を示す機能ブロック図である。It is a functional block diagram which shows the principal part of the control apparatus which concerns on embodiment of this invention. 従来技術において、キャリアに三角波を用いた場合の2アーム変調時の動作波形図である。In the prior art, it is an operation waveform diagram at the time of two-arm modulation when using a triangular wave as a carrier. 従来技術において、キャリアに鋸歯状波を用いた場合の2アーム変調時の動作波形図である。In the prior art, it is an operation waveform diagram at the time of two-arm modulation when a sawtooth wave is used for a carrier.
 以下、図に沿って本発明の実施形態を説明する。
 なお、以下の各実施形態が適用されるインバータは、例えば図1に示したような三相インバータであるが、後述するように、本発明が適用されるインバータの相数は特に限定されるものではない。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
An inverter to which each of the following embodiments is applied is, for example, a three-phase inverter as shown in FIG. 1, but as will be described later, the number of phases of the inverter to which the present invention is applied is particularly limited. is not.
 始めに、図2に基づいて本発明に係る制御方法の第1実施形態を説明する。
 図2は、第1,第2のキャリアとしての三角波1,三角波2を備え、これらの三角波1,三角波2と各相の出力電圧指令に相当する変調信号とを比較して図1のインバータを制御する場合の動作波形の一例である。図7と同様に、負荷Mに流れる各相の出力電流I,I,Iは正弦波であり、力率は1であるものとする。
First, a first embodiment of the control method according to the present invention will be described with reference to FIG.
2 includes a triangular wave 1 and a triangular wave 2 as first and second carriers. The triangular wave 1 and the triangular wave 2 are compared with a modulation signal corresponding to an output voltage command for each phase, and the inverter of FIG. It is an example of the operation waveform in the case of controlling. As in FIG. 7, it is assumed that the output currents I u , I v , I w of each phase flowing through the load M are sine waves and the power factor is 1.
 第1実施形態が図7の従来技術と異なる点は、本実施形態では、振幅が同一であって180°位相の異なる三角波1,三角波2を備え、例えば、図2の期間1(三角波1,2の一周期間)では、三角波1と二つの変調信号V,Vとを比較し、三角波2と変調信号Vとを比較することで、図1に示したスイッチング素子U,V,W,U,V,Wのオン/オフを決定している点である。 The first embodiment is different from the prior art of FIG. 7 in that the present embodiment includes a triangular wave 1 and a triangular wave 2 having the same amplitude and different phases by 180 °, for example, period 1 (triangular wave 1, 2), the triangular wave 1 is compared with the two modulation signals V u and V v, and the triangular wave 2 and the modulation signal V w are compared, whereby the switching elements U P and V P shown in FIG. , W P , U N , V N , W N are determined on / off.
 例えば、図2の期間1において、
 変調信号V≧三角波1の場合は、スイッチング素子Uをオン、変調信号V<三角波1の場合は、スイッチング素子Uをオン、
 変調信号V≧三角波1の場合は、スイッチング素子Vをオン、変調信号V<三角波1の場合は、スイッチング素子Vをオン、
 変調信号V≧三角波2の場合は、スイッチング素子Wをオン、変調信号V<三角波2の場合は、スイッチング素子Wをオン、とする。
For example, in period 1 of FIG.
When the modulation signal V utriangular wave 1, the switching element UP is turned on, and when the modulation signal V u <triangular wave 1, the switching element U N is turned on,
When the modulation signal V vtriangular wave 1, the switching element VP is turned on. When the modulation signal V v <triangular wave 1, the switching element V N is turned on,
For the modulation signal V wtriangular wave 2, turn on the switching elements W P, in the case of the modulation signal V w <triangular wave 2, the switching element W N ON, and.
 また、大きさが三角波1,2の最大値または最小値に維持される変調信号は、出力電圧位相(または大きさ、以下同じ)に応じて変化させると共に、三角波2と比較する変調信号も出力電圧位相に応じて変化させる。
 具体的には、図2に示すごとく、三角波1,2の最大値に維持される変調信号V→三角波1,2の最小値に維持される変調信号V→三角波1,2の最大値に維持される変調信号V→ ……のごとく変化させ、三角波2と比較する変調信号もV→V→V→ ……のごとく変化させる。
Further, the modulation signal whose magnitude is maintained at the maximum value or the minimum value of the triangular waves 1 and 2 is changed in accordance with the output voltage phase (or magnitude, the same applies hereinafter), and the modulation signal to be compared with the triangular wave 2 is also output. Change according to voltage phase.
Specifically, as shown in FIG. 2, the modulation signal V u maintained at the maximum value of the triangular waves 1 and 2 → the modulation signal V w maintained at the minimum value of the triangular waves 1 and 2 → the maximum value of the triangular waves 1 and 2 is the modulated signal V v → ...... varied as maintenance, modulation signal is also V w → V v → V u → ...... as the changing of comparing the triangular wave 2.
 図2の期間1では、変調信号Vの大きさが三角波1,2の最大値に維持されているので、スイッチング素子Uのオンにより、U相の出力端子Uは、直流電圧源Bの正極Pに接続され続ける。
 一方、V相,W相の出力端子V,Wは、それぞれ、三角波1,2と変調信号V,Vとの大小関係に基づき、スイッチング素子VまたはVのオン、スイッチング素子WまたはWのオンにより、直流電圧源Bの正極Pと負極Nとに交互に接続される。
In the period 1 of FIG. 2, the magnitude of the modulation signal V u is maintained at the maximum value of the triangular wave 1, by turning on the switching elements U P, the output terminal U of the U-phase, the DC voltage source B Continue to be connected to the positive electrode P.
On the other hand, V-phase, W-phase output terminals V, W, respectively, a triangular wave, 2 and the modulation signal V v, based on the magnitude relation between V w, on the switching elements V P or V N, the switching element W P or by turning on the W N, are alternately connected to the positive electrode P and a negative electrode N of the DC voltage source B.
 この時、V相,W相の出力端子V,Wが、それぞれ、期間1内で直流電圧源Bの正極P,負極Nに接続される時間比率は、図7の従来技術と図2の本実施形態とで同じである。すなわち、U相,V相,W相の時間平均的な出力電圧は、従来技術と本実施形態とで同一である。 At this time, the time ratios at which the V-phase and W-phase output terminals V and W are connected to the positive electrode P and the negative electrode N of the DC voltage source B within the period 1 respectively are as shown in FIG. This is the same as in the embodiment. That is, the U-phase, V-phase, and W-phase time average output voltages are the same in the conventional technique and the present embodiment.
 一方、出力端子V,Wが、それぞれ直流電圧源Bの正極Pまたは負極Nに接続されるタイミングは、図7の従来技術と図2の本実施形態とで異なっている。
 更に特徴的なのは、図7の従来技術では、期間1において、出力端子U,V,Wの全てが正極Pに接続される期間が存在するのに対し、図2の本実施形態では、出力端子U,V,Wの全てが正極Pに接続される期間が存在していない。このことに関連して、直流電流Idcに着目すると、図7の従来技術では、出力端子U,V,Wの全てが正極Pに接続される期間は直流電流Idcが流れずに0となる。これに対し、図2の本実施形態では、出力端子U,V,Wの全てが正極Pに接続される期間が存在しないため、直流電流Idcが0となる期間が存在しない。
 つまり、本実施形態によれば、直流電流Idcの変化量が図7の従来技術と比べて少なくなる結果、直流電流Idcに含まれる交流成分、換言すれば、コンデンサCに流れるIが小さくなるため、コンデンサCの発熱が抑制されることになる。
On the other hand, the timing at which the output terminals V and W are connected to the positive electrode P or the negative electrode N of the DC voltage source B is different between the prior art of FIG. 7 and the present embodiment of FIG.
What is more characteristic is that in the prior art of FIG. 7, there is a period in which all of the output terminals U, V, W are connected to the positive electrode P in the period 1, whereas in the present embodiment of FIG. There is no period in which all of U, V, and W are connected to the positive electrode P. In this regard, when attention is paid to the direct current I dc , in the prior art of FIG. 7, the direct current I dc does not flow during the period in which all of the output terminals U, V, W are connected to the positive electrode P, and 0 Become. On the other hand, in the present embodiment of FIG. 2, there is no period in which all of the output terminals U, V, W are connected to the positive electrode P, so there is no period in which the DC current I dc is zero.
That is, according to the present embodiment, the amount of change in the direct current I dc is smaller than that in the prior art of FIG. 7, and as a result, the alternating current component included in the direct current I dc , in other words, I c flowing through the capacitor C is Therefore, the heat generation of the capacitor C is suppressed.
 なお、図2に示したのは、一例として、ある出力電圧の大きさを想定した場合の動作波形である。この例では、全ての相の出力端子U,V,Wが正極Pまたは負極Nに同時に接続される期間が存在しないが、例えば、出力電圧が低くなってくると、出力端子U,V,Wが正極Pまたは負極Nに同時に接続される期間が発生する。しかし、その期間は、図7の従来技術と比べて短くなるので、図2の場合と同様の効果を得ることができる。
 すなわち、動作期間内における半導体スイッチング素子のオン/オフ周期の少なくとも1周期が、n相全ての交流出力端子U,V,Wが直流電圧源Bの正極Pまたは負極Nに同時に接続される状態が存在しない周期となるように、各相のスイッチング素子をオン/オフさせれば、上記の少なくとも1周期では直流電流Idcが0にならないため、Idcの変化量が小さくなってコンデンサCの電流Iが減少し、発熱を抑制することができる。
In addition, what was shown in FIG. 2 is an operation | movement waveform at the time of assuming the magnitude | size of a certain output voltage as an example. In this example, there is no period in which the output terminals U, V, and W of all phases are simultaneously connected to the positive electrode P or the negative electrode N. For example, when the output voltage decreases, the output terminals U, V, and W During which the positive electrode P or the negative electrode N are simultaneously connected. However, since the period is shorter than that of the prior art of FIG. 7, the same effect as in the case of FIG. 2 can be obtained.
That is, at least one cycle of the on / off cycle of the semiconductor switching element within the operation period is a state in which all the n-phase AC output terminals U, V, W are simultaneously connected to the positive electrode P or the negative electrode N of the DC voltage source B. If the switching element of each phase is turned on / off so as to have a non-existing cycle, the direct current I dc does not become zero in the above-described at least one cycle, so that the amount of change in I dc becomes small and the current of the capacitor C I c is reduced, heat generation can be suppressed.
 表1は、本実施形態の制御動作の一例をまとめたものであり、出力電圧位相に応じて、三角波1,2との比較対象になる変調信号と、大きさが三角波1,2の最大値または最小値に維持される変調信号と、変調信号の大きさが三角波1,2の最大値または最小値のどちらに維持されるかを示している。表中に記載した電気角は、U相の変調信号Vを基準としており、電気角が0°の時にU相の変調信号Vが最大になる前提である。 Table 1 summarizes an example of the control operation of the present embodiment. The modulation signal to be compared with the triangular waves 1 and 2 and the maximum value of the triangular waves 1 and 2 according to the output voltage phase. Or it shows whether the modulation signal is maintained at the minimum value, and whether the magnitude of the modulation signal is maintained at the maximum value or the minimum value of the triangular waves 1 and 2. The electrical angles described in the table are based on the U-phase modulation signal V u , and are based on the premise that the U-phase modulation signal V u is maximized when the electrical angle is 0 °.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
 図3は、従来技術と本実施形態のコンピュータシミュレーション結果を示す波形図であり、(a)が従来技術、(b)が本実施形態である。このシミュレーション結果において、電流の遅れ角=0°(負荷力率:1.0)であり、図中の波形に付した記号は、これまでに説明した電流、電圧の記号と同一である。また、図3には、直流電流Idcの交流成分Iの実効値Idcacrmsを、三角波の周期を基本周期として計算した結果も併せて記載してある。 FIG. 3 is a waveform diagram showing computer simulation results of the prior art and the present embodiment, where (a) is the prior art and (b) is the present embodiment. In this simulation result, the current delay angle = 0 ° (load power factor: 1.0), and the symbols attached to the waveforms in the figure are the same as the current and voltage symbols described so far. FIG. 3 also shows the result of calculating the effective value I dcacrms of the alternating current component I c of the direct current I dc with the period of the triangular wave as the basic period.
 図3(a),(b)の比較から明らかなように、本実施形態によれば、直流電流Idcの交流成分Iの実効値Idcacrmsが減少している、すなわち、コンデンサCに流れる電流Iの実効値が減少していることが判る。
 なお、表1では、例えば電気角0°~30°の期間において、変調信号Vを三角波2と比較しているが、三角波2の比較対象となる変調信号は、三角波1,2の最大値または最小値に維持する変調信号以外であれば良い。よって、電気角0°~30°の期間では、変調信号Vを三角波2と比較し、変調信号Vは三角波1と比較しても良い。このことは、他の電気角の範囲においても同様である。
As apparent from the comparison between FIGS. 3A and 3B, according to the present embodiment, the effective value I dcacrms of the AC component I c of the DC current I dc is reduced, that is, flows to the capacitor C. it can be seen that the effective value of the current I c is decreased.
In Table 1, for example, in the period of the electrical angle 0 ° ~ 30 °, the modulation signal has been compared to the modulation signal V w and the triangular wave 2, to be compared of the triangular wave 2, the maximum value of the triangular wave 1 Alternatively, it may be other than the modulation signal maintained at the minimum value. Therefore, in the period of the electrical angle 0 ° ~ 30 °, the modulation signal V v compared with the triangular wave 2, the modulation signal V w may be compared with the triangular wave 1. The same applies to other electrical angle ranges.
 次に、図4は、第1実施形態の変形例を示す動作波形図である。
 この変形例では、第1,第2のキャリアとして、三角波1,2の代わりに、振幅が同一であって互いに波形の異なる鋸歯状波1,2を用いている。ここで、鋸歯状波1は時間に対して増加する鋸歯状波であり、鋸歯状波2は時間に対して減少する鋸歯状波である。
 この変形例においても、図4における直流電流Idcの変化量が図8の従来技術と比べて少なくなり、直流電流Idcに含まれる交流成分、すなわちコンデンサCに流れるIが減少するため、コンデンサCの発熱を抑制することができる。
Next, FIG. 4 is an operation waveform diagram showing a modification of the first embodiment.
In this modified example, sawtooth waves 1 and 2 having the same amplitude and different waveforms are used as the first and second carriers instead of the triangular waves 1 and 2. Here, the sawtooth wave 1 is a sawtooth wave that increases with time, and the sawtooth wave 2 is a sawtooth wave that decreases with time.
Also in this modified example, the amount of change in the direct current I dc in FIG. 4 is smaller than that in the prior art in FIG. 8, and the AC component included in the direct current I dc , that is, I c flowing through the capacitor C is reduced. Heat generation of the capacitor C can be suppressed.
 次いで、図5は、本発明に係る制御方法の第2実施形態のコンピュータシミュレーション結果を、従来技術及び第1実施形態と対比して示した動作波形図であり、(a)は従来技術、(b)は第1実施形態、(c)は第2実施形態である。ここでは、電流の遅れ角=45°(負荷力率:0.71)に設定してあり、図中の波形に付した記号は、これまでに説明した電流、電圧の記号と同一である。また、図5には、直流電流Idcの交流成分Iの実効値Idcacrmsを、三角波の周期を基本周期として計算した結果も併せて記載してある。 Next, FIG. 5 is an operation waveform diagram showing the computer simulation result of the second embodiment of the control method according to the present invention in comparison with the prior art and the first embodiment, (a) is the prior art, ( b) is the first embodiment, and (c) is the second embodiment. Here, the current delay angle is set to 45 ° (load power factor: 0.71), and the symbols attached to the waveforms in the figure are the same as the symbols of current and voltage described so far. FIG. 5 also shows the result of calculating the effective value I dcacrms of the alternating current component I c of the direct current I dc with the period of the triangular wave as the basic period.
 図5(a)の従来技術と図5(b)の第1実施形態とを比較すると、図5(b)では、直流電流Idcの交流成分Iの実効値Idcacrmsが増加していることが判る。これは、前述した第1実施形態における負荷力率の条件((負荷力率:1.0)に対して、図5のシミュレーション条件では負荷力率が低い(負荷力率:0.71)ためであり、換言すれば、第1実施形態の制御方法は、負荷力率が悪い場合には適用する意味がないことになる。 When comparing the prior art of FIG. 5A with the first embodiment of FIG. 5B, the effective value I dcacrms of the AC component I c of the DC current I dc is increased in FIG. 5B . I understand that. This is because the load power factor is lower in the simulation condition of FIG. 5 (load power factor: 0.71) than the load power factor condition ((load power factor: 1.0) in the first embodiment described above. In other words, the control method of the first embodiment has no meaning to be applied when the load power factor is bad.
 この問題を解決するために、第2実施形態では、インバータの出力電圧位相や出力電流極性(または位相、以下同じ)に応じて、第1,第2のキャリア(例えば三角波1,2)と比較される各相の変調信号をどの相のものとするかを変更すると共に、第1,第2のキャリアの最大値または最小値に値を維持する各相の変調信号をどの相のものとするかも変更することとした。
 更に、第2実施形態では、出力電圧位相及び電流極性次第では、二つのキャリアと各相の変調信号とを比較するのではなく、図7等の従来技術と同様に、単一のキャリアと全ての相の変調信号V,V,Vとをそれぞれ比較するようにした。
In order to solve this problem, in the second embodiment, a comparison is made with the first and second carriers (for example, triangular waves 1 and 2) according to the output voltage phase and output current polarity (or phase, the same applies hereinafter) of the inverter. The phase of the modulated signal of each phase is changed, and the phase of the modulated signal of each phase that maintains the maximum or minimum value of the first and second carriers is changed I decided to change it.
Further, in the second embodiment, depending on the output voltage phase and the current polarity, the two carriers and the modulation signal of each phase are not compared, but a single carrier and all of them are compared as in the prior art of FIG. The phase modulation signals V u , V v , and V w are respectively compared.
 以下の表2は、出力電圧位相及び出力電流極性に応じた、三角波1,2との比較対象になる変調信号と、大きさが三角波の最大値または最小値に維持される変調信号と、変調信号の大きさが三角波の最大値または最小値のどちらに維持されるかを示している。表中に記載した電気角は、U相の変調信号Vを基準としており、電気角が0°の時に、U相の変調信号Vが最大となる前提である。なお、表2に記載した出力電流極性は、インバータから負荷Mに向かって電流が流れる場合を「+」としている。
 また、表2の備考欄に「従来」と記載したモードは、単一の三角波と全相の変調信号V,V,Vとをそれぞれ比較するモードである。
Table 2 below shows the modulation signal to be compared with the triangular waves 1 and 2 according to the output voltage phase and output current polarity, the modulation signal whose magnitude is maintained at the maximum value or the minimum value of the triangular wave, and the modulation It shows whether the magnitude of the signal is maintained at the maximum value or the minimum value of the triangular wave. The electrical angle described in the table is based on the U-phase modulation signal V u , and is a premise that the U-phase modulation signal V u becomes maximum when the electrical angle is 0 °. In addition, the output current polarity described in Table 2 is “+” when current flows from the inverter toward the load M.
The mode described as “conventional” in the remarks column of Table 2 is a mode for comparing a single triangular wave with all-phase modulation signals V u , V v , and V w .
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
 例えば、表2において、出力電圧位相が0°~60°の範囲にあり、出力電流極性として、U相が「+」、V相が「-」、W相が「-」であった場合には、変調信号V,Vを三角波1と比較し、変調信号Vを三角波2と比較する。
 この時、変調信号Vは、三角波1の最大値に維持し、他の変調信号V,Vは、Vが三角波1の最大値に維持されることを考慮して、所望の出力線間電圧が得られるように補正される。
 一方、出力電圧位相が0~60°の範囲にあっても、出力電流極性が表2に記載した条件を満たさなければ、従来と同様に、単一の三角波と各相の変調信号V,V,Vとをそれぞれ比較する。
For example, in Table 2, when the output voltage phase is in the range of 0 ° to 60 °, and the output current polarity is “+” for the U phase, “−” for the V phase, and “−” for the W phase. Compares the modulation signals V u and V w with the triangular wave 1 and the modulation signal V v with the triangular wave 2.
At this time, the modulation signal V u is maintained at the maximum value of the triangular wave 1, and the other modulation signals V v and V w are set to a desired output in consideration that V u is maintained at the maximum value of the triangular wave 1. Correction is made so that a line voltage is obtained.
On the other hand, even if the output voltage phase is in the range of 0 to 60 °, as long as the output current polarity does not satisfy the conditions described in Table 2, a single triangular wave and the modulation signals V u , V v and V w are respectively compared.
 図5(c)は、表2に従って変調信号V,V,V及び三角波1,2を選択することによりスイッチング素子のオン/オフを決定した場合のシミュレーション結果である。
 この図5(c)を図5(a)の従来技術と比較すると、直流電流Idcの交流成分Iの実効値Idcacrmsが減少していることが判る。なお、図5(a)と図5(c)とでは変調信号V,V,Vの波形が異なっているが、これは、前述したように所定の相の変調信号を補正したことによるものであり、UV相間,VW相間,WU相間の出力線間電圧については、同一の値が得られている。
FIG. 5C shows a simulation result when the on / off state of the switching element is determined by selecting the modulation signals V u , V v , V w and the triangular waves 1, 2 according to Table 2.
When FIG. 5C is compared with the prior art of FIG. 5A, it can be seen that the effective value I dcacrms of the AC component I c of the DC current I dc is reduced. 5A and 5C are different in the waveforms of the modulation signals V u , V v , and V w , this is because the modulation signal of a predetermined phase is corrected as described above. The same value is obtained for the output line voltage between the UV phase, the VW phase, and the WU phase.
 つまり、第2実施形態によれば、負荷力率が低い場合でも、同一の出力線間電圧を得ながらコンデンサに流れる電流を減少させてその発熱を抑制することができる。
 なお、この第2実施形態は、三角波1,2の代わりに鋸歯状波1,2を用いた場合にも適用可能である。
That is, according to the second embodiment, even when the load power factor is low, the current flowing through the capacitor can be reduced while obtaining the same output line voltage, and the heat generation can be suppressed.
The second embodiment is also applicable to the case where sawtooth waves 1 and 2 are used instead of triangular waves 1 and 2.
 ここで、図6は、上述した制御方法の第1,第2実施形態を実現するための制御装置の主要部を示す機能ブロック図である。なお、この制御装置は、三相インバータを対象とし、キャリアに二つの三角波を用いる場合のものである。
 図6において、変調信号選択手段10には、各相の変調信号V,V,Vと、ある相(例えばU相)を基準とした出力電圧位相(または大きさ)と、各相の出力電流極性(または位相)と、が入力されている。また、キャリア発生手段20から、例えば、振幅が同一であって180°位相の異なる三角波1,三角波2が出力され、これらの三角波1,三角波2は、前記出力電圧位相及び出力電流極性と共にキャリア選択手段30に入力されている。
Here, FIG. 6 is a functional block diagram showing a main part of the control device for realizing the first and second embodiments of the control method described above. This control device is for a three-phase inverter and uses two triangular waves for the carrier.
In FIG. 6, the modulation signal selection means 10 includes modulation signals V u , V v , V w for each phase, an output voltage phase (or magnitude) based on a certain phase (for example, U phase), and each phase. Output current polarity (or phase). Further, for example, triangular wave 1 and triangular wave 2 having the same amplitude and different 180 ° phase are output from the carrier generating means 20, and these triangular wave 1 and triangular wave 2 are carrier-selected together with the output voltage phase and output current polarity. Input to means 30.
 キャリア選択手段30からは、三角波1、及び、三角波2(または三角波1)がそれぞれ比較手段41,比較手段42に出力され、比較手段41では、変調信号選択手段10により選択された二つの相の変調信号が三角波1と比較されると共に、比較手段42では、変調信号選択手段10により選択された残り一つの相の変調信号が三角波2(または三角波1)と比較される。
 そして、比較手段41,比較手段42の出力に基づく駆動信号が、図1のインバータのスイッチング素子U,V,W,U,V,Wにそれぞれ分配されるようになっている。
From the carrier selection means 30, the triangular wave 1 and the triangular wave 2 (or triangular wave 1) are output to the comparison means 41 and the comparison means 42, respectively. In the comparison means 41, the two phases selected by the modulation signal selection means 10 are output. The modulation signal is compared with the triangular wave 1, and the comparison means 42 compares the remaining one phase modulation signal selected by the modulation signal selection means 10 with the triangular wave 2 (or triangular wave 1).
Then, the drive signal based on the output of the comparison means 41, comparison means 42, the switching elements U P of the inverter Figure 1, V P, W P, so as to be respectively distributed to the U N, V N, W N Yes.
 ここで、前述した第1実施形態では、キャリア選択手段30が三角波1を比較手段41に、三角波2を比較手段42にそれぞれ出力する。また、変調信号選択手段10は、表1に基づき、出力電圧位相に応じて所定の二相の変調信号と所定の一相の変調信号を比較手段41,42にそれぞれ出力する。
 比較手段41,42は、入力された各相の変調信号を三角波1または三角波2と比較することにより、スイッチング素子U~Wの駆動信号を生成する。この場合、表1における三角波最大値/最小値維持変調信号は、比較手段41に入力された二つの変調信号のうちの何れかとなる。
Here, in the first embodiment described above, the carrier selection unit 30 outputs the triangular wave 1 to the comparison unit 41 and the triangular wave 2 to the comparison unit 42. Also, the modulation signal selection means 10 outputs a predetermined two-phase modulation signal and a predetermined one-phase modulation signal to the comparison means 41 and 42, respectively, according to the output voltage phase based on Table 1.
The comparison means 41 and 42 compare the inputted modulation signal of each phase with the triangular wave 1 or the triangular wave 2 to generate driving signals for the switching elements U P to W N. In this case, the triangular wave maximum value / minimum value maintaining modulation signal in Table 1 is one of the two modulation signals input to the comparison means 41.
 また、前述した第2実施形態では、キャリア選択手段30が、表2に基づき、出力電圧位相及び出力電流極性に応じて、三角波1を比較手段41に、三角波2(または三角波1)を比較手段42にそれぞれ出力する。
 ここで、三角波1を比較手段42に出力するモードは、表2において出力電流極性が「上記以外」であって備考欄に「従来」と記載されている場合である。このモードでは、単一の三角波すなわち三角波1を比較手段41,42に与えることにより、全ての相の変調信号V,V,Vを単一の三角波1と比較することになる。
Further, in the second embodiment described above, the carrier selecting means 30 is based on Table 2 and the triangular wave 1 is compared to the comparing means 41 and the triangular wave 2 (or triangular wave 1) is compared according to the output voltage phase and output current polarity. 42 respectively.
Here, the mode in which the triangular wave 1 is output to the comparison means 42 is the case where the output current polarity is “other than the above” in Table 2 and “conventional” is described in the remarks column. In this mode, a single triangular wave, that is, a triangular wave 1 is supplied to the comparison means 41 and 42, whereby the modulation signals V u , V v and V w of all phases are compared with the single triangular wave 1.
 第2実施形態では、変調信号選択手段10が、出力電圧位相及び出力電流極性に応じて所定の二相の変調信号と所定の一相の変調信号を比較手段41,42にそれぞれ出力する。比較手段41,42は、入力された所定相の変調信号を三角波1,三角波2と比較するか、従来と同様の制御方法を実施する場合には単一の三角波1のみと比較することにより、スイッチング素子U~Wの駆動信号を生成する。
 ここで、図6に示した制御装置の各機能は、マイクロコンピュータ等の演算処理装置と、これに実装されるプログラムとによって実現可能である。
In the second embodiment, the modulation signal selection unit 10 outputs a predetermined two-phase modulation signal and a predetermined one-phase modulation signal to the comparison units 41 and 42 according to the output voltage phase and the output current polarity, respectively. The comparison means 41 and 42 compare the input modulation signal of a predetermined phase with the triangular wave 1 and the triangular wave 2 or when only the single triangular wave 1 is compared when performing the same control method as the conventional one, Drive signals for the switching elements U P to W N are generated.
Here, each function of the control device shown in FIG. 6 can be realized by an arithmetic processing device such as a microcomputer and a program mounted thereon.
 なお、上記の各実施形態が適用されるインバータの半導体素子(スイッチング素子やダイオード)には、シリコンを材料とする従来の半導体素子だけでなく、高温環境下でも使用可能なSiC(炭化珪素)等を用いたワイドバンドギャップ半導体素子を用いても良い。
 この場合、ワイドバンドギャップ半導体素子の周辺部品について高温環境への対応が課題として残ることになるが、本発明によれば、インバータの直流部のコンデンサの発熱が抑制されるので、既存のコンデンサを使用できることがある。
The semiconductor elements (switching elements and diodes) of the inverter to which the above embodiments are applied include not only conventional semiconductor elements made of silicon but also SiC (silicon carbide) that can be used in a high temperature environment. A wide band gap semiconductor element using may be used.
In this case, the response to the high temperature environment remains as a problem for the peripheral parts of the wide band gap semiconductor element. However, according to the present invention, since the heat generation of the capacitor in the DC part of the inverter is suppressed, Sometimes it can be used.
 本発明は、単相インバータや、三相以外の多相インバータを対象とする制御方法及び制御装置、並びにこれらの制御方法または制御装置を用いて制御されるインバータ装置に利用することができる。 The present invention can be used for a control method and a control device for a single-phase inverter, a multi-phase inverter other than a three-phase inverter, and an inverter device controlled using these control methods or control devices.
B:直流電圧源
C:コンデンサ
L:リアクトル
,V,W,U,V,W:半導体スイッチング素子
M:三相交流負荷
P:正極
N:負極
U,V,W:交流出力端子
10:変調信号選択手段
20:キャリア発生手段
30:キャリア選択手段
41,42:比較手段
B: direct-current voltage source C: Capacitor L: Reactor U P, V P, W P , U N, V N, W N: semiconductor switching element M: the three-phase AC load P: positive N: negative U, V, W: AC output terminal 10: modulation signal selection means 20: carrier generation means 30: carrier selection means 41, 42: comparison means

Claims (13)

  1.  二つの半導体スイッチング素子の直列回路をn(nは複数)個備え、前記n個の直列回路を直流電圧源に対して全て並列に接続すると共に、前記直列回路を構成する二つの半導体スイッチング素子同士の接続点を一相の交流出力端子としてn相交流負荷の各相にそれぞれ接続してなるインバータの制御方法であって、前記半導体スイッチング素子をオン/オフさせて前記交流出力端子に現れる前記直流電圧源の直流電圧の時間比率を変化させることにより、前記インバータから所望の大きさ及び周波数のn相交流電圧を出力させる制御方法において、
     n相のうち少なくとも特定の一相の交流出力端子が一定期間にわたって前記直流電圧源の正極または負極に接続される状態を維持し、かつ、n相のうち前記特定の相以外の他相の交流出力端子が前記一定期間より短い期間にわたって前記直流電圧源の負極または正極にそれぞれ接続されると共に、前記一定期間内で、n相全ての交流出力端子が前記直流電圧源の正極または負極に同時に接続される期間が短くなるように、各相の前記半導体スイッチング素子をオン/オフさせることを特徴とするインバータの制御方法。
    N series circuits of two semiconductor switching elements are provided (n is a plurality), the n series circuits are all connected in parallel to a DC voltage source, and two semiconductor switching elements constituting the series circuit are connected to each other. Is an inverter control method in which each connection point is connected to each phase of an n-phase AC load as a one-phase AC output terminal, and the DC that appears at the AC output terminal by turning on and off the semiconductor switching element. In a control method for outputting an n-phase AC voltage having a desired magnitude and frequency from the inverter by changing the time ratio of the DC voltage of the voltage source,
    An AC output terminal of at least one specific phase among n phases is maintained in a state where it is connected to a positive electrode or a negative electrode of the DC voltage source for a certain period, and an alternating current of another phase other than the specific phase among the n phases The output terminal is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, and all the n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source within the predetermined period. A method for controlling an inverter, comprising: turning on / off the semiconductor switching element of each phase so that a period of time to be shortened is shortened.
  2.  二つの半導体スイッチング素子の直列回路をn(nは複数)個備え、前記n個の直列回路を直流電圧源に対して全て並列に接続すると共に、前記直列回路を構成する二つの半導体スイッチング素子同士の接続点を一相の交流出力端子としてn相交流負荷の各相にそれぞれ接続してなるインバータの制御方法であって、前記半導体スイッチング素子をオン/オフさせて前記交流出力端子に現れる前記直流電圧源の直流電圧の時間比率を変化させることにより、前記インバータから所望の大きさ及び周波数のn相交流電圧を出力させる制御方法において、
     n相のうち少なくとも特定の一相の交流出力端子が動作期間内の一定期間にわたって前記直流電圧源の正極または負極に接続される状態を維持し、かつ、n相のうち前記特定の相以外の他相の交流出力端子が前記一定期間より短い期間にわたって前記直流電圧源の負極または正極にそれぞれ接続されると共に、
     前記動作期間内における前記半導体スイッチング素子のオン/オフ周期の少なくとも1周期が、n相全ての交流出力端子が前記直流電圧源の正極または負極に同時に接続される状態が存在しない周期となるように、各相の前記半導体スイッチング素子をオン/オフさせることを特徴とするインバータの制御方法。
    N series circuits of two semiconductor switching elements are provided (n is a plurality), the n series circuits are all connected in parallel to a DC voltage source, and two semiconductor switching elements constituting the series circuit are connected to each other. Is an inverter control method in which each connection point is connected to each phase of an n-phase AC load as a one-phase AC output terminal, and the DC that appears at the AC output terminal by turning on and off the semiconductor switching element. In a control method for outputting an n-phase AC voltage having a desired magnitude and frequency from the inverter by changing the time ratio of the DC voltage of the voltage source,
    An AC output terminal of at least one specific phase among the n phases is maintained in a state of being connected to the positive electrode or the negative electrode of the DC voltage source for a certain period within the operation period, and other than the specific phase among the n phases The AC output terminal of the other phase is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, respectively,
    At least one cycle of the on / off cycle of the semiconductor switching element within the operation period is a cycle in which there is no state in which all n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source. A method for controlling an inverter, wherein the semiconductor switching element of each phase is turned on / off.
  3.  請求項1または2に記載したインバータの制御方法において、
     どの相の交流出力端子を一定期間にわたって前記直流電圧源の正極または負極に接続した状態に維持するか、及び、当該交流出力端子を前記直流電圧源の正極または負極の何れに接続するかを、出力電圧の位相または大きさに応じて切り替えることを特徴とするインバータの制御方法。
    In the inverter control method according to claim 1 or 2,
    Which phase of the AC output terminal is maintained in a state of being connected to the positive electrode or the negative electrode of the DC voltage source over a certain period, and whether the AC output terminal is connected to the positive electrode or the negative electrode of the DC voltage source, A method for controlling an inverter, wherein switching is performed according to the phase or magnitude of the output voltage.
  4.  請求項1~3の何れか1項に記載したインバータの制御方法において、
     位相が異なる複数のキャリアとして複数の三角波を備え、前記n相の出力電圧指令に相当するn個の変調信号のそれぞれを、前記特定の相以外の他相に相当する変調信号が一つのキャリアに重複しないように前記複数のキャリアの何れかに対応させ、前記n個の変調信号のそれぞれを前記対応させたキャリアと比較してそれぞれが相当する相の半導体スイッチング素子をオン/オフさせる駆動信号を生成することを特徴とするインバータの制御方法。
    The inverter control method according to any one of claims 1 to 3,
    A plurality of triangular waves are provided as a plurality of carriers having different phases, and each of n modulation signals corresponding to the n-phase output voltage command is converted into one carrier with a modulation signal corresponding to another phase other than the specific phase. A drive signal that corresponds to any of the plurality of carriers so as not to overlap, compares each of the n modulated signals with the corresponding carrier, and turns on / off the semiconductor switching element of the corresponding phase. An inverter control method comprising: generating an inverter;
  5.  請求項1~3の何れか1項に記載したインバータの制御方法において、
     波形が異なる複数のキャリアとして複数の鋸歯状波を備え、前記n相の出力電圧指令に相当するn個の変調信号のそれぞれを、前記特定の相以外の他相に相当する変調信号が一つのキャリアに重複しないように前記複数のキャリアの何れかに対応させ、前記n個の変調信号のそれぞれを前記対応させたキャリアと比較して各変調信号に相当する相の半導体スイッチング素子をオン/オフさせる駆動信号を生成することを特徴とするインバータの制御方法。
    The inverter control method according to any one of claims 1 to 3,
    A plurality of sawtooth waves are provided as a plurality of carriers having different waveforms, and each of n modulation signals corresponding to the n-phase output voltage command has one modulation signal corresponding to a phase other than the specific phase. Corresponding to one of the plurality of carriers so as not to overlap the carrier, each of the n modulated signals is compared with the corresponding carrier, and the semiconductor switching element of the phase corresponding to each modulated signal is turned on / off A control method for an inverter, characterized in that a drive signal to be generated is generated.
  6.  請求項4または5に記載したインバータの制御方法において、
     n個の変調信号のうち、出力電圧の位相または大きさに応じて選択された少なくとも1個の変調信号の大きさを前記キャリアの最大値または最小値と同一にし、かつ、当該変調信号の大きさを前記キャリアの最大値または最小値の何れと同一にするかも、出力電圧の位相または大きさに応じて決定することを特徴とするインバータの制御方法。
    In the inverter control method according to claim 4 or 5,
    Of the n modulated signals, the magnitude of at least one modulated signal selected according to the phase or magnitude of the output voltage is made equal to the maximum value or the minimum value of the carrier, and the magnitude of the modulated signal A method for controlling an inverter, wherein whether the same value as the maximum value or the minimum value of the carrier is determined according to the phase or magnitude of the output voltage.
  7.  請求項1~6の何れか1項に記載した制御方法を第1の制御方法とし、
     前記n相の出力電圧指令に相当するn個の変調信号を単一のキャリアとそれぞれ比較してn相の半導体スイッチング素子をオン/オフさせる駆動信号を生成する制御方法を第2の制御方法とし、
     出力電圧の位相または大きさ、及び、出力電流の極性または位相に応じて、前記第1の制御方法と前記第2の制御方法とを切り替えることを特徴とするインバータの制御方法。
    The control method according to any one of claims 1 to 6 is a first control method,
    A control method for generating a drive signal for turning on / off an n-phase semiconductor switching element by comparing n modulation signals corresponding to the n-phase output voltage command with a single carrier is referred to as a second control method. ,
    An inverter control method, wherein the first control method and the second control method are switched according to the phase or magnitude of the output voltage and the polarity or phase of the output current.
  8.  二つの半導体スイッチング素子の直列回路をn(nは複数)個備え、前記n個の直列回路を直流電圧源に対して全て並列に接続すると共に、前記直列回路を構成する二つの半導体スイッチング素子同士の接続点を一相の交流出力端子としてn相交流負荷の各相にそれぞれ接続してなるインバータの、前記半導体スイッチング素子をオン/オフさせて前記交流出力端子に現れる前記直流電圧源の直流電圧の時間比率を変化させることにより、所望の大きさ及び周波数のn相交流電圧を前記インバータから出力させるための制御装置において、
     n相のうち少なくとも特定の一相の交流出力端子が一定期間にわたって前記直流電圧源の正極または負極に接続される状態を維持し、かつ、n相のうち前記特定の相以外の他相の交流出力端子が前記一定期間より短い期間にわたって前記直流電圧源の負極または正極にそれぞれ接続されると共に、前記一定期間内で、n相全ての交流出力端子が前記直流電圧源の正極または負極に同時に接続される期間が短くなるように、各相の前記半導体スイッチング素子をオン/オフさせることを特徴とするインバータの制御装置。
    N series circuits of two semiconductor switching elements are provided (n is a plurality), the n series circuits are all connected in parallel to a DC voltage source, and two semiconductor switching elements constituting the series circuit are connected to each other. A DC voltage of the DC voltage source that appears at the AC output terminal when the semiconductor switching element of the inverter is connected to each phase of the n-phase AC load using the connection point as a one-phase AC output terminal. In the control device for outputting the n-phase AC voltage having a desired magnitude and frequency from the inverter by changing the time ratio of
    An AC output terminal of at least one specific phase among n phases is maintained in a state where it is connected to a positive electrode or a negative electrode of the DC voltage source for a certain period, and an alternating current of another phase other than the specific phase among the n phases The output terminal is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, and all the n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source within the predetermined period. A control device for an inverter, wherein the semiconductor switching element of each phase is turned on / off so that a period of time to be shortened.
  9.  二つの半導体スイッチング素子の直列回路をn(nは複数)個備え、前記n個の直列回路を直流電圧源に対して全て並列に接続すると共に、前記直列回路を構成する二つの半導体スイッチング素子同士の接続点を一相の交流出力端子としてn相交流負荷の各相にそれぞれ接続してなるインバータの、前記半導体スイッチング素子をオン/オフさせて前記交流出力端子に現れる前記直流電圧源の直流電圧の時間比率を変化させることにより、所望の大きさ及び周波数のn相交流電圧を前記インバータから出力させるための制御装置において、
     n相のうち少なくとも特定の一相の交流出力端子が動作期間内の一定期間にわたって前記直流電圧源の正極または負極に接続される状態を維持し、かつ、n相のうち前記特定の相以外の他相の交流出力端子が前記一定期間より短い期間にわたって前記直流電圧源の負極または正極にそれぞれ接続されると共に、
     前記動作期間内における前記半導体スイッチング素子のオン/オフ周期の少なくとも1周期が、n相全ての交流出力端子が前記直流電圧源の正極または負極に同時に接続される状態が存在しない周期となるように、各相の前記半導体スイッチング素子をオン/オフさせることを特徴とするインバータの制御装置。
    N series circuits of two semiconductor switching elements are provided (n is a plurality), the n series circuits are all connected in parallel to a DC voltage source, and two semiconductor switching elements constituting the series circuit are connected to each other. A DC voltage of the DC voltage source that appears at the AC output terminal when the semiconductor switching element of the inverter is connected to each phase of the n-phase AC load using the connection point as a one-phase AC output terminal. In the control device for outputting the n-phase AC voltage having a desired magnitude and frequency from the inverter by changing the time ratio of
    An AC output terminal of at least one specific phase among the n phases is maintained in a state of being connected to the positive electrode or the negative electrode of the DC voltage source for a certain period within the operation period, and other than the specific phase among the n phases The AC output terminal of the other phase is connected to the negative electrode or the positive electrode of the DC voltage source for a period shorter than the predetermined period, respectively,
    At least one cycle of the on / off cycle of the semiconductor switching element within the operation period is a cycle in which there is no state in which all n-phase AC output terminals are simultaneously connected to the positive electrode or the negative electrode of the DC voltage source. An inverter control device that turns on / off the semiconductor switching element of each phase.
  10.  請求項8または9に記載したインバータの制御装置において、
     位相が異なる複数の三角波または波形が異なる複数の鋸歯状波を複数のキャリアとして発生するキャリア発生手段と、
     出力電圧の位相または大きさに応じて、前記n相の出力電圧指令に相当するn個の変調信号のそれぞれを、前記特定の相以外の他相に相当する変調信号が一つのキャリアに重複しないように前記複数のキャリアの何れかに対応させる変調信号選択手段と、
     前記変調信号選択手段により選択された前記n個の変調信号のそれぞれを前記対応させたキャリアと比較する比較手段と、
     を備え、
     前記比較手段の出力信号を用いて、前記n相の半導体スイッチング素子をオン/オフさせることを特徴とするインバータの制御装置。
    In the inverter control device according to claim 8 or 9,
    A carrier generating means for generating a plurality of triangular waves having different phases or a plurality of sawtooth waves having different waveforms as a plurality of carriers;
    According to the phase or magnitude of the output voltage, each of the n modulation signals corresponding to the n-phase output voltage command is not duplicated in one carrier with the modulation signal corresponding to the other phase other than the specific phase. Modulation signal selection means corresponding to any of the plurality of carriers,
    Comparing means for comparing each of the n modulated signals selected by the modulated signal selecting means with the corresponding carrier;
    With
    An inverter control device that turns on / off the n-phase semiconductor switching element using an output signal of the comparison means.
  11.  請求項10に記載したインバータの制御装置において、
     前記キャリア発生手段により発生させた複数のキャリアのうち、出力電圧の位相または大きさ、及び、出力電流の極性または位相に応じて選択したキャリアを前記比較手段に与えるキャリア選択手段を更に備え、
     前記比較手段が、前記キャリア選択手段により選択されたキャリアと前記n個の変調信号とを比較して得た出力信号を用いて、前記n相の半導体スイッチング素子をオン/オフさせることを特徴とするインバータの制御装置。
    In the control apparatus of the inverter according to claim 10,
    Of the plurality of carriers generated by the carrier generation means, further comprises a carrier selection means for giving the carrier selected according to the phase or magnitude of the output voltage and the polarity or phase of the output current to the comparison means,
    The comparison means turns on / off the n-phase semiconductor switching element using an output signal obtained by comparing the carrier selected by the carrier selection means and the n modulation signals. Inverter control device.
  12.  請求項1~7の何れか1項に記載した制御方法により、各相の前記半導体スイッチング素子がオン/オフされることを特徴とするインバータ装置。 An inverter device, wherein the semiconductor switching element of each phase is turned on / off by the control method according to any one of claims 1 to 7.
  13.  請求項8~11の何れか1項に記載した制御装置により、各相の前記半導体スイッチング素子がオン/オフされることを特徴とするインバータ装置。 12. An inverter device, wherein the semiconductor switching element of each phase is turned on / off by the control device according to any one of claims 8 to 11.
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