JP4707111B2 - AC-AC direct power converter controller - Google Patents

Description

  The present invention provides an AC-AC direct power converter that directly converts a multi-phase AC voltage into a multi-phase AC voltage having an arbitrary magnitude and frequency using a semiconductor switching element without using a large energy buffer such as a capacitor. In particular, the present invention relates to a control device for an AC-AC direct power converter that reduces switching frequency, switching loss, and generated noise.

FIG. 13 is a simplified model of a matrix converter 20 that is an example of an AC-AC direct power converter, where 10 indicates a three-phase AC power source and 30 indicates a load. In an actual matrix converter, an LC filter for suppressing harmonic current associated with switching is required on the input side. However, in order to facilitate the explanation, this LC filter is ignored in FIG. Simulated by three-phase current sources i _uv , i _vw , i _wu . Note that S _ru , S _su , S _tu , S _rv , S _sv , S _tv , S _rw , S _sw , and S _tw in the matrix converter 20 are AC switches that can pass current bidirectionally.
Now, assuming that the power supply 10 is a symmetrical three-phase power supply, the line voltage effective value is E, the power supply angular frequency is ω, and the power supply phase angle is θ, the phase voltages _er , _es , and _et are given by Equations 1 and 2. It is done.

Here, it is assumed to approximate the power supply voltage _e r in the switching period _2T, e s, _{e t} and the load current _{i uv, i vw, i wu} as constant values, respectively. The power supply voltage is _er >0> _es > _et (0 ≦ θ ≦ π / 6), and the output phase voltage command value is v _u ^* > v _v ^* > v _w ^* (line voltage command value v _uv ^* , V _vw ^* , v _wu ^* ).
The number of commutations during the switching half cycle T is 6 times when all nine AC switches are provided with a conduction period, but the number of commutations is reduced to 4 times and the power factor is controlled to 1. , a conventional technique for controlling the voltage command value as the output voltage as an average value of the switching half-period T, explaining the method of determining the on-duty D _ru to D _tw of nine AC switch S _ru to S _tw below.

As the conventional method 1, there is a method in which the r-phase having the maximum power supply voltage absolute value and the u-phase having the maximum output voltage continue to be conducted over the switching half cycle T. Each on-duty _D ru _{to D tw} at this time is given by Equation 3.

FIG. 14A shows the on-duty (switching pattern) and the output line voltage showing the operation of the conventional method 1. In all line voltage waveforms, zero voltage and the maximum line voltage of the power source e are shown. _tr exists.
A switching method corresponding to the conventional method 1 is described in Non-Patent Document 1.

In the conventional system 1, the conventional system 2 described in Non-Patent Document 2 is known as a system that does not use the e _tr that is the maximum line voltage of the power supply when the output voltage command value is low.
The maximum value of the output voltage of the conventional method 2 is ½ of the power supply voltage. In the conventional method 2, the duties D _{A to} D _E for the combinations of the pulse patterns are defined by using the phase voltage effective value E _m = E / √3, and are given by Equation 4, respectively.

FIG. 14B shows the on-duty and the output line voltage showing the operation of the conventional method 2, and does not use the maximum line voltage e _tr of the power supply.

  In the conventional method 1, the maximum line voltage of the power supply voltage and the zero voltage are used regardless of the magnitude of the output voltage command value, so that the voltage ripple in the switching cycle increases. As the voltage ripple increases, the noise generated by the converter increases, which may cause malfunction of other devices, which is not preferable. Moreover, there is a problem in that a new filter for removing noise causes an increase in cost and an increase in volume.

  According to the conventional method 2, the voltage ripple can be reduced, but the voltage in the range in which PWM control is possible is as low as ½ of the power supply voltage. Therefore, in order to obtain a high output voltage, it is necessary to switch the control. However, when the control is switched, sequence processing increases, which may complicate the arithmetic device. Further, when the control is not switched, the output voltage is out of the range in which PWM control is possible, and the output voltage is distorted. When the electric motor is connected to the load, distortion of the output voltage causes torque pulsation, which is not preferable because it causes an increase in loss of the electric motor or overheating.

  Further, both conventional methods 1 and 2 are control methods when the power source power factor is 1. When the power source power factor 1 control is performed in this way, the current advances from the AC power source by the LC filter on the input side of the converter, and the power source power factor actually advances and becomes the power factor. Due to the increase in current and loss due to the advance current, there is a problem that the input reactor is increased in size and cost.

In view of the above points, the present applicant reduces the output voltage ripple in the switching cycle of the AC-AC direct power converter, reduces the generated noise, and does not require complicated control switching or the like. We have already filed a control device for the power converter.
The prior invention will be described below.

FIG. 15 is a block diagram showing the configuration of the invention of the prior application. In the main circuit, 10 is a three-phase AC power source, 20 is a matrix converter, 21 is an input filter comprising a reactor L and a capacitor C, and 30 is a load. Respectively.
The control device 40 calculates the on-duty of the AC switch of the matrix converter 20 from the input voltage detection means 41 connected to the three-phase AC power supply 10, the output voltage command calculation means 42, the input voltage and the output voltage command value, Drive pulses (PWM pulses) G _ru , G _su , G _tu , G _rv , G _sv , G _tv , G _rw , G _sw , G _tw for the AC switches S _{ru to} S _tw of the matrix converter 20 according to this on-duty. Drive pulse calculation means 400.

The input voltage detector 41, for example, a three-phase input terminals r, s, divided by the resistance or the like of the phase voltage and star connection input from t, the phase voltages e _r of the power supply _10, e _s, e _t Is detected.
FIG. 16 is a block diagram of the output voltage command calculation means 42 in FIG. 15, in which the induction motor as the load 30 is subjected to variable speed control. 16, the derived primary angular frequency command value corresponding to the speed command value of the motor ω _L ^*, V / by f table 421 a line voltage command value V _L ^* corresponding to the primary angular frequency command value omega _L ^* obtain. Further, the primary angular frequency command value ω _L ^* is input to the integrator 422, and the electrical angle θ _L ^* of the induction motor is obtained by time integration. Based on the line voltage command value V _L ^* and the electrical angle θ _L ^* , the three-phase oscillator 423 gives the output phase voltage command values v _u ^* , v _v ^* , and v _w ^* according to Equation 5.

FIG. 17 is a block diagram showing the configuration of the drive pulse calculation means 400 in FIG.
First, for the AC switch of the phase that outputs the maximum voltage, the switching pattern is determined so as to be connected to the maximum voltage phase and the intermediate voltage phase on the power supply side, and for the AC switch of the phase that outputs the minimum voltage The operation of determining the switching pattern so as to be connected to the intermediate voltage phase and the minimum voltage phase on the power supply side will be described.

When controlling the matrix converter 20 of FIG. 15, in order to control the output line voltages v _uv , v _vw , v _wu and the power source power factor cos _ψ according to the specified values, respectively, in the switching half cycle T according to Equation 6, and determines the switch _S ru _{to S tw} on-duty _D ru _{to D tw} and switching time _T tu _{through T tw.}

  As an on-duty condition, Equation 7 must be established from the continuity of the load current of the matrix converter 20.

For example, in the u phase, only one of the switches S _ru , S _su , S _tu must always be turned on. In considering the switching pattern, the switching frequency is sufficiently higher than the frequency of the power supply and the load voltage, and on the premise of the inductive load, the input voltages _er , _es , _et and the load current i in the switching period 2T. _uv , i _vw , and i _wu are approximated as constant values, respectively. In addition, the input voltage is _{e r> e s> e t} , the output voltage command value ^{_{v u *> v v *>}} v described under the condition that ^{w *.}

FIG. 18 shows the on-duty (switching pattern) and the output line voltage in the prior invention. Respectively the conduction period of each phase switch by on-duty D _ru to D _tw, the half period of the second half and the first half period of which a pattern of folding.
This switching pattern indicates that, for the u-phase AC switch of the maximum output voltage command v _u ^* , the maximum voltage e _r (r phase that is the maximum voltage phase) and the intermediate voltage e _s (s phase that is the intermediate voltage phase). Only for the minimum voltage e _t (t phase which is the minimum voltage phase), and for the w-phase AC switch of the minimum output voltage command value v _w ^* , the intermediate voltage e _{s of the} power source and a PWM pattern not connected to the maximum voltage e _r connected only to the minimum voltage e _t, the use of such a PWM pattern, when a high output voltage of FIG. (a), low in FIG (b) There is no change in the output voltage. That is, regardless of the magnitude of the output voltage, the switching pattern is determined so that the AC switch of the phase that outputs the maximum voltage is connected to the maximum voltage phase and the intermediate voltage phase on the power supply side, and the minimum voltage is output. The switching pattern is determined so that the AC switch of the phase to be connected is connected to the intermediate voltage phase and the minimum voltage phase on the power supply side.
The number of commutations in the switching half cycle T can be reduced to four times as in the conventional methods 1 and 2 because the switches S _tu and S _rw are not conducted (D _tu = 0, D _rw = 0). In addition, since there is no direct switching between the maximum voltage and the minimum voltage, switching loss and noise can be reduced, and an intermediate voltage is used in all phases, thus suppressing potential changes at the load neutral point. it can.

In the prior invention, as shown in FIG. 18, the line voltage can always be constituted by voltage pulses having the same sign as the line voltage command value (for example, for the line voltage v _uv , the command value v _uv ^* the same polarity voltage pulse _e rs of _constructed line voltages _{v uv} by _{e st),} further, the line voltage waveform _{v wu} absolute value of the command value is maximized is shown in the diagram (a) Thus, when the output voltage is high, zero voltage is not output, and when the output voltage is low as shown in FIG. 5B, the maximum voltage pulse e _tr is not output, so that output voltage harmonics are suppressed. be able to.

Next, the on-duty calculation means 400 in FIG. 15 will be described.
FIG. 19 shows a connection relationship in consideration of only the load current i _wu between the u phase having the maximum output voltage command value and the w phase having the minimum value. At this time, as shown in FIG. 19, the u-phase switches S _ru and S _su and the w-phase switches S _sw and S _tw are respectively conducted to generate a pattern of the switching half cycle T.
In FIG. 19, when the load-side impedance viewed from the power source is considered as the resistance R _wu in order to realize the power source power factor 1, the average input currents i _rwu , i _swu , i _thu in the switching half cycle T are obtained by Equation 8. (Because the symbol “-” cannot be added in the specification text, the symbol “-” is added above the current i and power P in each equation to indicate the average value).

Thus, the average power P _wu of the power source in the switching half cycle T is given by Equation 9.

Since the average P _{wu in} Equation 9 is equal to the power consumption of the load, the current source i _wu between w and u is expressed by Equation 10.

  The u phase, which is the maximum output voltage phase, is connected only to the r phase of the maximum voltage phase and the s phase of the intermediate voltage phase, and is not connected to the t phase of the minimum voltage phase.

Further, r-phase current _{i RWU} Since only _{-i wu} flows when turning on the switch _{S ru,} from Equation 8 and 10, the on-duty _{D ru} is as Equation 12.

From Equation 7, the on-duty D _su is obtained by Equation 13.

The w-phase, the r-phase of the maximum voltage phase is not connected, also, t-phase current _{i tWU,} since the flow is only _{i wu} when turning on the switch _{S tw,} the on-duty _{D rw, D} tw, D _sw is obtained by Expression 14 to Expression 16, respectively.

Next, consider the v-phase switching pattern of the intermediate voltage phase.
FIG. 20 shows a connection relationship in consideration of only the load current i _uv between the u-phase having the maximum output voltage command value and the v-phase having the intermediate value. In FIG. 20, when the load-side impedance viewed from the power source is considered as the resistance R _uv in order to realize the power source power factor 1, the input currents i _rub , i _suv , i _tuv are expressed by Expression 17.

Further, since the power source average power P _uv in the switching half cycle T is equal to the load power, the current source i _uv is given by Equation 18.

In FIG. 20, since the −i _uv flows only when the switch S _tv is turned on, the on-duty D _tv can be obtained from Equation 19 as the t-phase current i _tub .

FIG. 21 shows a connection relationship in consideration of only the load current _ivw between the v-phase whose output voltage command value is an intermediate value and the w-phase of the minimum phase. In FIG. 21, when the load-side impedance viewed from the power source is considered as the resistance R _vw in order to realize the power source power factor 1, the input currents i _rvw , i _svw , i _tvw are expressed by Equation 20.

Further, since the power source average power P _vw in the switching half cycle T is equal to the load power, the current source i _vw is given by Equation 21.

In Figure 21, r-phase current _{i rvw} Since only _{i vw} flows when turning on the switch _{S rv,} on-duty _{D rv} is obtained by equation 22.

From the equations 7, 19, and 22, the on-duty D _sv is obtained by the equation 23.

In the above, the input voltage to derive the _{e r> e s> e t} , the output voltage command value ^{_{v u *> v v *>}} v w * on-duty of each switch in the case of.
The operation of the on-duty calculation means 400 when a switching pattern is generated in an arbitrary magnitude relationship between input and output voltages will be described below.

In the on-duty calculation means 406 shown in FIG. 17, in order to obtain information on the magnitude relation of the input voltage, the input voltage phase / line conversion means 401 converts the input voltage _er , _es , _et to the line voltage. e _rs , e _st , and e _tr are obtained by Expression 24.

In accordance with Table 1, the input magnitude discrimination means 402 discriminates the input voltage mode m _s (1 to 6) from the sign of the input voltage, and the maximum voltage e ₁ , intermediate voltage e ₂ , and minimum voltage e of the input voltage (power supply voltage). _{Get 3} . Here, the subscripts 1, 2, and 3 mean the maximum, middle, and minimum of the input voltage, respectively.

The output of the input magnitude determination means 402 is a maximum voltage e ₁ , an intermediate voltage e ₂ , a minimum voltage e _3, and 3-bit signals r ₁ , s ₁ , r ₂ s ₃ representing the magnitude relationship. Signal _r 1, _{s 1,} respectively _e r, becomes "1" only when _{e s} is the maximum voltage, the signal _r 2 _{s 3} are _{e r} only when the intermediate voltage or _{e s} is the minimum voltage " This is a signal that becomes 1 ″.

The output voltage phase / line conversion means 403 in FIG. 17 obtains the line voltage command values v _uv ^* , v _vw ^* , v _wu ^* from the output voltage command values v _u ^* , v _v ^* , v _w ^{* according} to Equation 25. Ask.

The output level decision means 404, according to Table 2, to determine the output from the sign of the line voltage command value voltage mode _m L (1 to 6), the maximum voltage _v ^a of the output phase voltage command value ^*, the intermediate voltage _v ^{b *} To obtain the minimum voltage v _c ^* . Here, the subscripts a, b, and c mean the maximum, middle, and minimum of the output voltage, respectively.

Further, the voltage command phase / line conversion means 405 calculates line voltage command values v _ab ^* , v _bc ^* , and v _ca ^{* according} to Equation 26.

The on-duty calculation means 406 uses the input maximum voltage e ₁ , intermediate voltage e ₂ , minimum voltage e _3, and line voltage command values v _ab ^* , v _bc ^* , v _ca ^* to maximize the output voltage command value. On-duty D _{1a to} D of a switch in which the voltage phase a phase, intermediate voltage phase b phase, and minimum voltage phase c phase are connected to the maximum voltage phase 1 phase, intermediate voltage phase 2 phase, and minimum voltage phase 3 phase of the input voltage, respectively. Equation ₃ is calculated for _3c .

The phase discriminating means 407, in accordance with Table 3, the maximum voltage phase a phase of the output voltage instruction value from the output voltage mode m _L received from output level decision means 404, the intermediate voltage phase b phase, the minimum voltage phase c phase is u-phase, respectively, It is determined whether it corresponds to the v phase or the w phase, and the on-duty of Expression 27 is output to the PWM generation unit of the corresponding phase.
For example, when m _L = 1, since the output intermediate voltage phase b phase is v phase according to Table 3, D _1v = D _1b and D _12v = D _12b and D _1v and D _12v are compared with the v phase. Output to the circuit 410.

  In FIG. 17, the phase comparison circuits 409 to 411 and the PWM generation means 412 to 414 for generating the PWM pulse are the same circuits for the three phases, and a specific PWM generation principle diagram is shown in FIG.

FIG. 22 is a principle diagram of PWM generation for the v phase, and is when the output phase voltage command is an intermediate voltage (v _b ^* = v _v ^* ).
In FIG. _6A , the triangular wave carrier changing between 0 and 1 is compared with the on-duty D _1v , D _12v (= D _1v + D _2v ), and signals Q _1v , Q _12v are obtained. The switching circuit G _1v , G _2v , G _3v is obtained from the signals Q _1v , Q _12v by the logic circuit shown in FIG. 5B, and further _divided into r, s, t phases to generate the PWM pulse G _rv. , G _sv , G _tv are generated. In this distribution, the signal r ₁ (e ₁ = _er signal), the signal s ₁ (e ₁ = _es signal), the signal r ₂ s ₃ (e ₂ = _er or e ₃ = e) obtained from Table 1 are used. _{Using the s} signal), it is determined whether the r and s phases on the power source side are the maximum voltage phase, the intermediate voltage phase, and the minimum voltage phase, respectively, and PWM pulses G _rv and G _sv are created. The t-phase PWM pulse G _tv on the power supply side is obtained as logic that turns on when both G _rv and G _sv are in the off state.

  The input voltage detection means 41 or the output voltage command calculation means 42 described above is merely an example, and the input voltage detection means 41 may detect a line voltage in addition to detecting the phase voltage of the power supply 10, This can also be realized by assuming that the amplitude of the voltage is constant and detecting the positive / negative of the input voltage. Further, the output voltage command calculation means 42 can be realized by vector control in addition to V / f control.

Incidentally, in the case of controlling the power factor of the power supply 1, the input voltage _{e r,} e s, the input current command value proportional to the ^{_{e t i r *, i s}} *, calculates the _i ^{t *,} the on-duty operation You may output to the means 400. FIG. In this case, the input current command values i _r ^* , i _s ^* , and i _t ^* are given by Equation 28 when the proportionality constant is 1 / R _s . Here, R _s is the impedance (resistance) of the matrix converter as viewed from the power source.

In the matrix converter simplified model shown in FIG. 15, the input voltage _{e r> e s> e t} , the output voltage command value and ^{_{v u *> v v *>}} v w *, the input voltage _{e r} in the switching period 2T , _e s, approximating _{e t} and the load current _{i uv, i vw, i wu} as constant values, respectively. Then, to derive a calculation formula for the on-duty _D ru _{to D tw} of the switches _S ru _{to S tw.}

From Equation 28, the input voltage _{e r, e s, e t} is the input current command value ^{_i r} _{*, i} s _*, represented by equation 29 using _i ^{t *.}

By substituting Equation 29 into Equation 11～16,19,22,23, each on-duty _D ru _{to D tw} can be obtained by equation 30.

As described above, the on-duties D _{ru to} D _tw of the nine AC switches S _{ru to} S _tw of the matrix converter 20 are determined. These on-duty calculation formulas do not include the proportionality constant 1 / R _s in Formula 28 and do not depend on R _s . Thus, the actual input current _{i r, i s, i t} is the input current command value ^{_{i r *, i s *,}} i t * each become proportional to the current in the phase (input power factor) of the input current command value as Therefore, the magnitude of the input current is determined by the load current.

Akio Ishiguro, Takeshi Furuhashi, Muneaki Ishida, Shigeru Okuma, "Output Voltage Control Method of PWM Controlled Cycloconverter Based on Instantaneous Input Line Voltage", IEEJ Transactions D, Vol. 111, 1991, pp. 201-207 Hidenori Hara, Eiji Yamamoto, Mitsuhiko Zenya, Toshikazu Tsuji, Tsuneo Kume, “One Way to Improve Voltage of Matrix Converter in Low Voltage Region”, 2004 IEEJ Conference on Industrial Applications, I-48, pp.313- 316

  In the switching pattern of FIG. 18 described above, the switch of the u phase is switched twice (r-phase and s-phase input voltages appear) and the v-phase is four times at both high output voltage and low output voltage. The switch is switched (r-phase, s-phase, and t-phase input voltages appear), and the w-phase switch is switched twice (s-phase and t-phase input voltages appear). That is, since the number of times of switching in one switching cycle (carrier cycle) is 8 in total for the three phases, the average number of times per output phase is 2.6 times obtained by dividing 8 times by 3 phases.

  As described above, in the invention of the prior application, the average number of times of switching per output phase in one switching cycle is as large as 2.6 times, so that the loss of the switching element increases, and the radiating fins and fans for cooling the switching element, etc. There is a problem that the cooling device becomes large and costs increase. In addition, the large number of switching operations causes an increase in noise generated by switching, which causes malfunction of other devices, and it is unavoidable to add a filter for noise suppression. There is a problem from the viewpoint of improving reliability.

  Therefore, the problem to be solved by the present invention is that the number of times of switching is reduced as compared with the invention of the prior application, and the effects of switching loss and noise are reduced to reduce the size and cost of the entire system, and also increase the efficiency and reliability. It is to provide a control device.

In order to solve the above-mentioned problem, the invention described in claim 1 is characterized in that each phase on the input side connected to the AC power source and each phase on the output side are directly connected by a bidirectional AC switch. In an AC-AC direct power converter that directly converts AC voltage to AC voltage of any magnitude and frequency by on / off operation,
Means for detecting an input voltage of the power converter; means for detecting an output current of the power converter; an output voltage command value of the power converter; input voltage information and output current information; and the output voltage command Drive pulse calculation means for determining a switching pattern of the AC switch using a magnitude relationship of each phase of the value and the input voltage information, and generating a driving pulse of the AC switch according to the switching pattern. It is a thing.

According to a second aspect of the present invention, there is provided an AC-AC direct power converter control device according to the first aspect of the present invention.
The drive pulse calculation means includes
Means for calculating output power from the output voltage command value and output current detection value; means for calculating input current command value from the input voltage command value, input current phase command value and output power of the power converter; On-duty calculation means for calculating the switching pattern of the AC switch as an on-duty from the input voltage detection value, the input current command value, the output current detection value, and the output voltage command value.

According to a third aspect of the present invention, there is provided an AC-AC direct power converter control device according to the second aspect of the present invention.
The on-duty calculation means is
The output voltage maximum phase and the output voltage intermediate phase of the power converter are connected to the input voltage maximum phase or the input voltage intermediate phase, and the output voltage minimum phase of the power converter is set to the input voltage intermediate phase or the input voltage minimum phase. A first on-duty calculation unit for calculating a switching pattern to be connected; and an output voltage maximum phase of the power converter is connected to an input voltage maximum phase or an input voltage intermediate phase; and the output voltage intermediate phase of the power converter And a second on-duty calculation unit for calculating a switching pattern for connecting the output voltage minimum phase to the input voltage intermediate phase or the input voltage minimum phase.

According to a fourth aspect of the present invention, there is provided an AC-AC direct power converter control device according to the third aspect,
The on-duty calculation means further includes:
Connecting the output voltage maximum phase of the power converter to the input voltage maximum phase, connecting the output voltage intermediate phase of the power converter to the input voltage maximum phase, the input voltage intermediate phase or the input voltage minimum phase, and the power A third on-duty calculation unit for calculating a switching pattern for connecting the output voltage minimum phase of the converter to the input voltage intermediate phase or the input voltage minimum phase; and the output voltage maximum phase of the power converter as the input voltage maximum phase or input. Connect to the voltage intermediate phase, connect the output voltage intermediate phase of the power converter to the input voltage maximum phase, input voltage intermediate phase or input voltage minimum phase, and the power converter output voltage minimum phase to the input voltage minimum And a fourth on-duty calculation unit for calculating a switching pattern connected to the phase.

The invention described in claim 5 is the control device for an AC-AC direct power converter described in claim 3 or 4,
Means for selecting and outputting the switching pattern calculated by any of the on-duty calculation units is provided.

The invention described in claim 6 is the control device for an AC-AC direct power converter described in any one of claims 1 to 5,
The switching pattern is determined so that the average number of times of switching per output phase in one switching cycle is 2 or less.

According to the present invention, by using the input voltage information, the output current information, and the output voltage command value of the power converter, the on-duty is calculated based on the switching connection condition for connecting the input phase and the output phase. Compared to the claimed invention, the number of times of switching can be reduced to 3/4.
As a result, switching loss can be reduced, the entire system can be reduced in size and cost, and efficiency and reliability can be improved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. The greatest feature of the control device 40A according to this embodiment is that a drive pulse calculation means 400A that detects the output current of the matrix converter 20 and calculates a pulse pattern that reduces the number of switching times from information on the input voltage and output current is provided. That is. In FIG. 1, the same components as those in FIG. 15 are denoted by the same reference numerals.

In FIG. 1, input voltage detection means 41 detects the r, s, and t phase voltages of the three-phase AC power supply 10. The detection position of the input voltage detection means 41 may be between the reactor L and the filter capacitor C in addition to the one shown in FIG. 1, and the two-phase voltage is detected without detecting all three phases. Another phase may be obtained by calculation.
The resulting input voltage e _r, e _s, with e _t is input to the drive pulse calculating means 400A, is input to the input voltage phase calculation means 43, the phase θ of the input voltage is detected by the PLL and the like. Input current phase calculating means 44, from the input voltage phase θ input current power factor command value [psi ^* and each phase of the input current reference command value ^{_u r} _{*, u} s _*, is calculated by Equation 31 _u ^{t *.}

The output voltage command calculation means 42 is, for example, an output voltage value V _L ^* corresponding to the frequency command value ω _L ^* and a frequency command value in V / f constant control widely used when an electric motor is connected as the load 30. The output voltage command values v _u ^* , v _v ^* , and v _w ^* of each phase are calculated from Equation 32 using the output voltage phase command value θ _L ^* obtained by time integration of ω _L ^* .

In this embodiment, the output voltage command calculation means 42 is not limited to V / f constant control, and vector control and various other control methods can be applied.
The output current detection means 45 detects each phase output current i _u , i _v , i _w of the matrix converter 20 using a hall sensor, a shunt resistor, or the like. In FIG. 1, two-phase currents of u phase and v phase are detected, and the remaining w phase is obtained from these detected currents by calculation.

Hereinafter, the drive pulse calculation means 400A, which is a main part of the present embodiment, will be described.
FIG. 2 is a block diagram showing the configuration of the drive pulse calculation means 400A. 2, the input voltage phase / the line converter 461, the input voltage _{e r, e s, e t} a line voltage _e rs by Equation _33, e _st, converted to _{e tr.}

Input current amplitude command operation unit 462, the input voltage _{e r,} e s, and _{e t,} the output voltage command value ^{_v u} _{*, v v *,} and _v ^{w *,} the output current _{i u,} i v, and _{i w,} The input current amplitude command value I ^* is calculated using the input current reference command values u _r ^* , u _s ^* , and u _t ^* . First, the output voltage command value ^{_{v u *, v v *,}} v w * and the output current _{i u,} i v, from _{i w,} the average output power _{P out} between the control cycle is calculated by Equation 34.

Then, the input voltage _{e r, e s, e t,} and an input current reference command value ^{_u r} _{*, u} s _*, from _u ^{t *,} the average input reference power _{P u} between the control cycle is calculated by Equation 35.

The average input reference power P _u is calculated from the input current reference command values u _r ^* , u _s ^* , and u _t ^*, and therefore does not have amplitude information of the input current. The relationship between the average input power P _in and the average input reference power P _u during the control period is expressed by Equation 36, where the amplitude of the input current is I ^* .

Since the matrix converter has no energy storage component is equal to the average input power P _in and the output power P _out. Therefore, the input current amplitude I ^* is obtained by Expression 37.

The input current command value calculation means 463 uses the input current amplitude I ^* obtained by Expression 37 and the input current reference command values u _r ^* , u _s ^* , u _t ^* to input current command values i _r ^* , i _s ^* and i _t ^* are calculated by Equation 38.

The output voltage phase / line conversion means 464 converts the output voltage command values v _u ^* , v _v ^* , and v _w ^* into the output line voltage command values v _uv ^* , v _vw ^* , and v _wu ^{* using} Equation 39. .

As shown in Table 4, the input magnitude discrimination means 465 discriminates the input mode m _S (1-6) from the signs of the input line voltages e _rs , e _st , e _tr , and the maximum, intermediate, and minimum phases of the input voltage. Voltages e _α , e _β , e _γ , input current command values i _α ^* , i _β ^* , i _γ ^*, and magnitude relationship signals r _α , s _α , r _β s _γ as pulse pattern discrimination signals are obtained. .
Here, subscripts α, β, and λ mean maximum, middle, and minimum, respectively, and correspond to subscripts 1, 2, and 3 in Table 1 described above. Therefore, Table 4 is substantially the same as Table 1.

Further, as shown in Table 5, the output magnitude discrimination means 466 discriminates the output mode m _L (1-6) from the sign of the output line voltage command values v _uv ^* , v _vw ^* , v _wu ^* , and outputs the output line. The maximum, intermediate, and minimum phase voltage command values v _a ^* , v _b ^* , v _c ^* , and output currents i _a , i _b , and _ic of the inter-voltage command values v _uv ^* , v _vw ^* , and v _wu ^* are obtained. Here, the subscripts a, b, and c mean maximum, middle, and minimum, respectively.

The voltage command phase / line-to-line conversion means 467 obtains output line voltage command values v _ab ^* , v _bc ^* , and v _ca ^* by Equation 40.

Further, the first on-duty calculation means 468 includes the maximum, intermediate, and minimum phase voltages e _α , e _β , and e _γ of the input voltage, and the maximum, intermediate, and minimum input current command values i _α ^* , i _β ^* , From the i _γ ^* , the output line voltage command values v _ab ^* , v _bc ^* , v _ca ^* and the maximum, middle and minimum output currents i _a , i _b , _ic , the maximum phase α of the input voltage, The on-duties D _{1αa to} D _1αβc of the respective switches connecting the intermediate phase β, the minimum phase γ, and the maximum phase a, the intermediate phase b, and the minimum phase c of the output voltage command value are _obtained by Equation 41.

Similarly to the first on-duty calculation means 468, the second on-duty calculation means 469 is e _α , e _β , e _γ and i _α ^* , i _β ^* , i _γ ^* and v _ab ^* , v _bc ^*. , _{v ca} ^* and _{i a, i b,} and a _{i c,} determining the on-duty _{D 2αa} ~D _2αβc the respective switch using equation 42.

Here, Formula 41 will be described.
FIG. 3 is a circuit diagram showing a connection configuration of a matrix converter, a three-phase AC power source, and a load in which a non-conductive switch is omitted, and is for explaining an example of connection of switches by the first on-duty calculation means 468. . Note that the input filter is not shown for ease of explanation.

In FIG. 3, the magnitude relationship of the input voltage is the maximum for r phase, the middle of s phase, and the minimum of t phase, and the magnitude relationship of output voltage is the maximum for u phase, the middle of v phase, and the smallest of w phase. is there. As shown in FIG. 3, the u phase of the maximum output voltage phase and the v phase of the intermediate phase are not connected to the t phase of the minimum input voltage phase, and the w phase of the minimum output voltage phase is connected to the r phase of the maximum input voltage phase. The on-duty of each switch is calculated so that it does not.
Since the minimum output voltage phase (c phase) is not connected to the maximum input voltage phase (α phase), D _1αc is _expressed by Equation 43.

Current of the input voltage minimum phase (gamma-phase), since the flow output minimum phase current i _c at a ratio of D _1Ganmashi, the formula 44.

From the continuity of the output current of the matrix converter, the sum of the on-duties of the output single phase must be 1. Therefore, D _1βc is _expressed by Equation 45.

Since the maximum output voltage phase (a phase) is not connected to the minimum input voltage phase (γ phase), D _1γa is _expressed by Equation 46.

The relationship between the output voltage command value v _ca ^* and Equations 44 and 45 is Equation 47.

When D _1αa is _obtained from Equation 47, Equation 48 is obtained.

D _1βa is _expressed by Equation 49 based on the on-duty condition.

Next, since the output voltage intermediate phase (b phase) is not connected to the minimum input voltage phase (γ phase), D _1γb is _expressed by Equation 50.

Relationship between the output voltage command _{v bc} ^* and formulas 44 and 45 becomes Equation 51.

When D _1αb is _obtained from Equation 51, Equation 52 is obtained.

D _1βb is _expressed by Equation 53 based on the on-duty condition.

  As described above, Formula 41 can be derived from Formula 43 to Formula 53 as switch connection conditions.

FIG. 4 shows a switching pattern, an input current, and an output line voltage when switching is performed with the duty calculated by Formula 41. In both the high output voltage of FIG. 4 (a) and the low output voltage of FIG. 4 (b), the u-phase is switched twice (r-phase and s-phase input voltages appear), and the v-phase is The switch is switched twice (r-phase and s-phase input voltages appear), and the w-phase switch is switched twice (s-phase and t-phase input voltages appear). That is, the total number of times of switching during one switching period is six times in total for three phases, and the average per output phase is two times obtained by dividing six times by three phases. Therefore, the number of times of switching can be reduced to 3/4 of the prior invention, and the switching loss can also be reduced.
However, there may be a case where only the first on-duty calculation means 468 cannot be realized depending on the load power factor and the output current. For example, when the load power factor is 1 and the voltages of the maximum input voltage phase and the intermediate phase are positive, it is impossible to flow a negative current through the positive intermediate phase as long as the positive input voltage is used. Accordingly, the first on-duty calculation means 468 alone is insufficient for realization.

  Therefore, in the second on-duty calculation means 469 shown in FIG. 2, the output voltage maximum phase (a phase) is not connected to the input voltage minimum phase (γ phase), and the output voltage intermediate phase (b phase) and the output voltage are connected. The on-duty is calculated by Equation 42 so that the minimum phase (c phase) is not connected to the maximum input voltage phase (α phase). Since the derivation of the formula 42 may be performed in the same way as the derivation of the formula 41, a detailed description thereof is omitted.

  FIG. 5 is a circuit when switching is performed with the duty calculated by Formula 42, and is for explaining an example of connection of switches by the second on-duty calculation means 469. As can be seen from FIG. 5, the output voltage maximum phase u phase is not connected to the input voltage minimum phase t phase, and the output voltage intermediate phase v phase and the output voltage minimum phase w phase are not connected to the input voltage maximum phase r phase. .

FIG. 6 shows a switching pattern, an input current, and an output line voltage when switching is performed with the duty calculated by Equation 42.
Similar to FIG. 4, the total number of times of switching during one switching period is 6 times, and the average per output phase is 2 times.

Returning to FIG. 2, on-duty selection means 470 is provided for selecting one of the outputs of the first and second on-duty calculation means 468 and 469. The on-duty selection means 470 determines that the condition does not hold when the on-duty does not exist between 0 and 1 in Expressions 41 and 42, and outputs the output of the on-duty calculation means 468 or 469 corresponding to the other expression. Operate to select.
The phase discriminating means 471 determines the duty _D αu ~D αβw comparing with output voltage mode _{m L} obtained in Table 5 Output u according to Table 6, v, a triangular wave carrier and w-phase.

FIG. 7 is a PWM generation principle diagram for the v-phase, where the output phase voltage command value is an intermediate voltage (v _b ^* = v _v ^* ).
In FIG. (A), the triangular wave carrier and the on-duty D _.alpha.v varying between 0,1 compares the _{D αβv = D αv + D βv} ), the signal _{Q αv,} Q αβv is obtained. The logic circuit shown in FIG. (B), the signal _Q αv, Q αβv from the switching signal _{G αv,} G βv, with obtaining a G _.gamma.V, these are magnitude relationship signals and logical operations in Table 4 r, s, t By assigning the phases, PWM pulses G _rv , G _sv , and G _tv are generated to switch each switch of the matrix converter.

  In the present embodiment, the configuration of the on-duty calculation means is not limited to the above-described example, and various configurations can be considered. Therefore, the input voltage and output current of the matrix converter are detected, the on-duty is calculated by a predetermined arithmetic expression according to the condition of the connected switch, and the average number of times of switching per output phase in one switching cycle is within two times. Is included in the present invention.

Next, FIG. 8 is a block diagram showing a configuration of the second embodiment of the present invention, and shows another configuration example of the drive pulse calculation means 400A in FIG.
In this embodiment, a third on-duty calculation means 479 and a fourth on-duty calculation means 480 are provided in addition to the configuration of the first embodiment shown in FIG. The on-duty calculation means 479 and 480 will be described below.

FIG. 9 is a diagram for explaining an example of connection of switches by the third on-duty calculation means 479. FIG.
In FIG. 9, the magnitude relationship of the input voltage is that the r phase is maximum, the s phase is intermediate, and the t phase is minimum, and the output voltage is that the u phase is maximum, the v phase is intermediate, and the w phase is minimum. In the third on-duty calculation means 479, the output voltage maximum phase is connected to the input voltage maximum phase, the output voltage intermediate phase is connected to the input voltage maximum phase, the intermediate phase and the minimum phase, and the output voltage minimum phase is connected to the input voltage. The on-duty is calculated so as to connect to the intermediate phase and the minimum phase.
Hereinafter, similarly to the first on-duty calculation means 468 in the first embodiment, an equation for calculating the duty is derived.

Since the maximum output voltage phase (a phase) is connected to the maximum input voltage phase (α phase), D _{3αa to} D _3γa are _expressed by Equation 54.

Since the output voltage minimum phase (c phase) is not connected to the input voltage maximum phase (α phase), D _3αc is _expressed by Equation 55.

The relationship between the output voltage command value v _ca ^* and Formula 54 is expressed by Formula 56.

When D _3γc is _obtained from Expression 56, Expression 57 is obtained.

Further, D _3βc is _expressed by Equation 58 from the on-duty condition.

Next, the output voltage intermediate phase (b phase) will be considered. Since the current of the maximum output voltage phase (a phase) continues to flow in the maximum input voltage phase (α phase) and the current of the output voltage intermediate phase (b phase) is superimposed on this at a rate of _D3αb , Become a relationship.

From Equation 59, D _3αb becomes Equation 60.

The relationship between the output voltage command value v _ab ^* and Equations 54 and 60 is Equation 61.

From Equation 61, D _3βb becomes Equation 62.

D _3γb is _expressed by Equation 63 from the on-duty condition.

  From the above, the calculation content by the third on-duty calculation means 479 is expressed by Expression 64.

FIG. 10 is a diagram illustrating a switching pattern, an input current, and an output line voltage when switching is performed with a duty calculated by Formula 64. From the switching pattern of FIG. 10, the u phase of the maximum output voltage phase is connected to the r phase of the maximum input voltage phase without switching, and the v phase of the output voltage intermediate phase is switched four times to The r phase, the intermediate phase s phase and the minimum phase t phase are connected, and the output voltage minimum phase w phase is connected to the s phase and t phase by switching twice.
That is, the number of times of switching during one switching cycle is 6 times in total for the three phases because the u phase, which is the maximum phase of the output voltage, does not perform switching, and the average per output phase is divided by 6 times for the three phases. 2 times.

On the other hand, as described in the first embodiment, there is a case where only the mathematical formula 64 does not satisfy the duty condition, so the fourth on-duty calculation means 480 is provided.
FIG. 11 is a circuit diagram showing an example of connection of switches by the fourth on-duty calculation means 480. The on-duty calculation means 480 connects the output voltage maximum phase to the input voltage maximum phase and the intermediate phase, connects the output voltage intermediate phase to the input voltage maximum phase, the intermediate phase and the minimum phase, and sets the output voltage minimum phase to the input voltage. Calculate the on-duty to connect to the minimum phase.
The on-duty in this case can be derived based on the same concept as the third on-duty calculation means 479, and is given by Expression 65.

FIG. 12 is a diagram showing a switching pattern, an input current, and an output line voltage when switching is performed with the duty calculated by Expression 65.
According to the switching pattern of FIG. 12, the u phase of the maximum output voltage phase is switched twice and connected to the r phase of the maximum input voltage phase and the s phase of the input voltage intermediate phase. The v phase of the output voltage intermediate phase is connected to the r phase, the s phase and the t phase of the minimum input voltage phase by switching four times, and the w phase of the minimum output voltage phase is connected to the t phase without switching. The
That is, the number of times of switching during one carrier cycle is 6 times in total for the three phases because the w phase of the output voltage minimum phase does not perform switching, and the average per output phase is divided by 6 times for the three phases. 2 times.

  The on-duty selection means 470 in FIG. 8 includes all the switches of the formulas 41, 42, 64, and 65 corresponding to the first to fourth on-duty calculation means 468, 469, 479, and 480, respectively. Those having an on-duty between 0 and 1 are selected, and the on-duty is output to the phase discrimination means 471. In the two patterns of Formula 64 and Formula 65, there are cases where the output voltage is not satisfied depending on the phase of the output voltage. Therefore, in order to realize output voltages according to all output voltage command values, Formula 41 and Formula 42 are combined. There are four patterns to choose from.

  As described above, the on-duty calculation means according to the present invention allows the average number of times of switching per output phase in one switching cycle to be two times, which can be reduced to 3/4 compared to the prior invention. The influence of noise can be reduced, and the entire system can be reduced in size and cost, and high efficiency and high reliability can be realized.

It is a block diagram which shows the structure of 1st Embodiment of this invention. It is a block diagram which shows the structure of the drive pulse calculating means in FIG. It is a circuit diagram which shows the example of a connection of the switch by the 1st on-duty calculating means in FIG. It is a figure which shows the switching pattern at the time of switching by the duty calculated by Numerical formula 41, an input current, and an output line voltage. It is a circuit diagram which shows the example of a connection of the switch by the 2nd on-duty calculating means in FIG. It is a figure which shows the switching pattern at the time of switching by the duty calculated by Numerical formula 42, an input current, and an output line voltage. FIG. 7A is a principle diagram of PWM pattern generation for the v phase, FIG. 7A is a waveform diagram of a triangular wave carrier and a switching signal, and FIG. 7B is a circuit diagram of a switching signal and a PWM pulse generation circuit. It is a block diagram which shows the structure of the drive pulse calculating means in 2nd Embodiment of this invention. It is a circuit diagram which shows the example of a connection of the switch by the 3rd on-duty calculating means in FIG. It is a figure which shows the switching pattern at the time of switching by the duty calculated by Numerical formula 64, an input current, and an output line voltage. It is a circuit diagram which shows the example of a connection of the switch by the 4th on-duty calculating means in FIG. It is a figure which shows the switching pattern at the time of switching by the duty calculated by Numerical formula 65, an input current, and an output line voltage. It is a figure which shows the simple model of a matrix converter. It is a figure which shows the on-duty and output line voltage in a prior art, FIG. 14 (a) is the operation example of the conventional system 1, FIG. It is a block diagram which shows the structure of prior invention. It is a block diagram which shows the structure of the output voltage calculating means in FIG. It is a block diagram which shows the structure of the drive pulse calculating means in FIG. It is a figure which shows the on-duty and output line voltage in prior invention, FIG. 18 (a) is an operation example at the time of a high output voltage, FIG.18 (b) is an operation example at the time of a low output voltage. It is a connection diagram of the maximum and minimum output voltage phases. It is a connection diagram of the maximum / intermediate output voltage phase. It is a connection diagram of an intermediate and minimum output voltage phase. FIG. 22A is a waveform diagram of a PWM pattern generation principle, FIG. 22A is a waveform diagram of a triangular wave carrier and a switching signal, and FIG. 22B is a circuit diagram of a switching signal and a PWM pulse generation circuit.

Explanation of symbols

10: Three-phase AC power supply 20: Matrix converter 21: Input filter 30: Load 40A: Control device 41: Input voltage detection means 42: Output voltage command calculation means 43: Input voltage phase calculation means 44: Input current phase calculation means 45: Output current detection means 400A: Drive pulse calculation means 461: Input voltage phase / line conversion means 462: Input current amplitude command calculation means 463: Input current command value calculation means
464: Output voltage phase / line conversion means 465: Input magnitude discrimination means 466: Input magnitude discrimination means 467: Voltage command phase / line conversion means 468: First on-duty calculation means 469: Second on-duty calculation means 470: On-duty selection means 471: Phase discrimination means 472: u-phase comparison circuit 473: v-phase comparison circuit 474: w-phase comparison circuit 475: triangular wave carrier generation circuit 476: u-phase PWM generation means 477: v-phase PWM generation means 478 : W-phase PWM generation means 479: third on-duty calculation means 480: fourth on-duty calculation means

Claims (6)

Each phase on the input side connected to the AC power source and each phase on the output side are directly connected by a bidirectional AC switch, and the AC voltage is changed to an AC voltage of an arbitrary magnitude and frequency by the on / off operation of the AC switch. In the AC-AC direct power converter that converts directly into
Means for detecting an input voltage of the power converter;
Means for detecting an output current of the power converter;
The switching pattern of the AC switch is determined using the output voltage command value, input voltage information and output current information of the power converter, and the magnitude relationship of each phase of the output voltage command value and the input voltage information. Driving pulse calculating means for generating a driving pulse of the AC switch according to the switching pattern;
A control apparatus for an AC-AC direct power converter, comprising: In the control apparatus of the AC-AC direct power converter according to claim 1,
The drive pulse calculation means includes
Means for calculating output power from the output voltage command value and output current detection value;
Means for calculating an input current command value from an input voltage command value, an input current phase command value and the output power of the power converter;
On-duty calculation means for calculating a switching pattern of the AC switch as an on-duty from the input voltage detection value, input current command value, output current detection value and output voltage command value;
A control apparatus for an AC-AC direct power converter, comprising: In the control apparatus for an AC-AC direct power converter according to claim 2,
The on-duty calculation means is
The output voltage maximum phase and the output voltage intermediate phase of the power converter are connected to the input voltage maximum phase or the input voltage intermediate phase, and the output voltage minimum phase of the power converter is set to the input voltage intermediate phase or the input voltage minimum phase. A first on-duty calculation unit for calculating a switching pattern to be connected;
The output voltage maximum phase of the power converter is connected to the input voltage maximum phase or the input voltage intermediate phase, and the output voltage intermediate phase and the output voltage minimum phase of the power converter are set to the input voltage intermediate phase or the input voltage minimum phase. A second on-duty calculation unit for calculating a switching pattern to be connected;
A control apparatus for an AC-AC direct power converter, comprising: In the control apparatus of the AC-AC direct power converter according to claim 3,
The on-duty calculation means further includes:
Connecting the output voltage maximum phase of the power converter to the input voltage maximum phase, connecting the output voltage intermediate phase of the power converter to the input voltage maximum phase, the input voltage intermediate phase or the input voltage minimum phase, and the power A third on-duty calculation unit for calculating a switching pattern for connecting the output voltage minimum phase of the converter to the input voltage intermediate phase or the input voltage minimum phase;
The output voltage maximum phase of the power converter is connected to the input voltage maximum phase or the input voltage intermediate phase, and the output voltage intermediate phase of the power converter is connected to the input voltage maximum phase, the input voltage intermediate phase, or the input voltage minimum phase. And a fourth on-duty calculation unit for calculating a switching pattern for connecting the output voltage minimum phase of the power converter to the input voltage minimum phase;
A control apparatus for an AC-AC direct power converter, comprising: In the control apparatus of the AC-AC direct power converter according to claim 3 or 4,
An AC-AC direct power converter control device comprising means for selecting and outputting a switching pattern calculated by any on-duty calculation unit. In the control apparatus of the AC-AC direct power converter according to any one of claims 1 to 5,
A control apparatus for an AC-AC direct power converter, wherein a switching pattern is determined so that an average number of times of switching per output phase in one switching cycle is 2 or less.

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