JP2007336665A - Gate driving device and power conversion device equipped with it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect an abnormality of a power conversion device without giving stress to a normal semiconductor element. <P>SOLUTION: A protective circuit 9 includes a voltage detection circuit 3 that detects a collector voltage of a main semiconductor element 10, an XOR circuit 4, and a filter circuit 5. A PWM signal 101, which commands the on/off of the main semiconductor element 10, is outputted from a PWM generation circuit 1. Then, a voltage detection signal 103 corresponding to the collector voltage of the main semiconductor element 10 is outputted from a voltage detection circuit 3. When the semiconductor element 10 is in a short-circuit state, the voltage detection signal 103 of an H level is outputted from the voltage detection circuit 3. When the PWM signal 101 is an off command (an L level), an output of the XOR circuit 104 becomes the H level and an error signal 105 is supplied to the PWM generation circuit 1 through the filter circuit 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a gate drive device of a semiconductor power conversion device, and more particularly to a gate drive device having a short circuit protection function and a power conversion device including the gate drive device.

  Conventionally, provided with a comparator for detecting whether the collector voltage and gate drive signal of the power semiconductor element each exceed a predetermined voltage, when the collector voltage exceeds a predetermined voltage when the gate drive signal is applied, that is, A protection device for a power semiconductor element that interrupts a gate drive signal by an AND signal of both comparator outputs is disclosed (for example, see Patent Document 1).

FIG. 7 is a configuration diagram of a conventional protection device for a power semiconductor element.
In the figure, 71 is a first comparator that detects whether or not the collector voltage of the main semiconductor element 10 exceeds a predetermined voltage, 72 is a second comparator that detects whether or not the gate drive signal exceeds a predetermined voltage, and 73. Is an AND circuit that calculates an AND signal (short circuit detection signal) of the output signals of the first comparator and the second comparator, 74 is a gate drive circuit that supplies a gate drive signal to the main semiconductor element, and 75 is the short circuit detection signal. In response to this, the cutoff command circuit supplies a cutoff signal to the drive circuit 74 and the cutoff transistor M1.

Next, the operation will be described.
When an ON command signal for the main semiconductor element 10 is input from the outside to the drive circuit 74 and the drive circuit 74 outputs a gate drive signal, the second comparator 72 outputs a signal indicating that the gate drive signal has exceeded a predetermined voltage. . At this time, when an overvoltage or overcurrent occurs in the main semiconductor element 10 due to an arm short circuit or a load short circuit, the collector voltage of the main semiconductor element 10 rises, and a signal indicating that the collector voltage is equal to or higher than a predetermined voltage from the first comparator. Is output. The AND circuit 73 receives outputs from the first comparator and the second comparator and outputs a short circuit detection signal. The short-circuit detection signal is input to the cutoff command circuit 75. The cutoff command circuit 75 commands the cutoff of the drive circuit 74 and turns on the transistor M1, thereby preventing the gate drive signal from being supplied to the main semiconductor element 10. .

As described above, the conventional power conversion device having the short-circuit protection function detects an abnormality such as an arm short-circuit or a load short-circuit using the AND signal of the collector voltage and the gate drive signal.
JP 2005-6464 A

FIG. 8 is a main circuit configuration diagram of an inverter device for explaining a problem of a conventional power conversion device.
In the figure, 11 and 12 are main semiconductor elements that form a pair that outputs a U-phase voltage, and 13 and 14 are main semiconductor elements that form a pair that outputs a V-phase voltage.
Since the conventional power converter detects an abnormal state only when the gate drive signal is input, if one of the paired main semiconductor elements fails in a short-circuit state, the normal An abnormal state cannot be detected until one of the main semiconductor elements is driven and an overcurrent flows due to a short circuit between the PN of the DC bus. Therefore, there is a problem that an overcurrent flows through the pair of main semiconductor elements to cause stress, which reduces the reliability of the entire system.

  The present invention has been made in view of such problems, and by detecting an abnormality of the power conversion device without applying stress to a normal semiconductor element, it is possible to prevent the occurrence of a new failure and the entire system. It is an object of the present invention to provide a semiconductor power conversion device capable of improving the reliability of the semiconductor power converter.

In order to solve the above problems, the present invention is configured as follows.
The invention according to claim 1 amplifies a PWM signal for commanding on / off of the main semiconductor element of the power converter, and generates a gate drive signal for driving the main semiconductor element; and In the gate driving device including a protection circuit, the protection circuit is connected to a collector of the main semiconductor element, generates a voltage detection signal of the collector, the PWM signal, and an XOR signal of the voltage detection signal And an XOR circuit that calculates a high frequency component of the XOR signal.
According to a second aspect of the present invention, the protection circuit includes a gate cutoff circuit that cuts off the PWM signal by an output of the filter circuit.
According to a third aspect of the present invention, the protection circuit supplies the XOR signal to a host controller that generates the PWM signal.
According to a fourth aspect of the present invention, the protection circuit supplies the voltage detection signal to a host controller that generates the PWM signal.
According to a fifth aspect of the present invention, a power converter includes the gate driving device according to the first aspect.

According to the first aspect of the present invention, since the protection circuit includes the XOR (exclusive OR) circuit, it is possible to detect an abnormality of the power conversion device when the gate is driven and when the gate is not driven. Therefore, the reliability of the power conversion device is improved.
According to the second aspect of the present invention, if the protection circuit includes a gate cutoff circuit, the gate drive signal can be cut off at high speed in the event of an abnormality. Therefore, the reliability of the power conversion device is further improved.
According to the third aspect of the present invention, when the XOR signal is input to the host controller that generates the PWM signal, the sending of the PWM signal can be stopped when an abnormality is detected. Therefore, the reliability of the power conversion device is further improved.
According to the fourth aspect of the present invention, if the voltage detection signal is supplied to the host device, the control performance of the power converter can be improved.
According to the invention described in claim 5, if the power conversion device includes the gate driving device described in claim 1, it is possible to prevent a new failure of the semiconductor element.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a gate driving apparatus showing a first embodiment of the present invention.
In the figure, reference numeral 1 denotes a PWM generation circuit which generates a PWM signal 101 for instructing an output voltage of the power converter. Reference numeral 2 denotes a gate drive circuit. The gate drive circuit 2 converts the PWM signal 101 into a gate drive signal 102 having a voltage level and a current level that can drive the IGBT 10.

  Reference numeral 9 denotes a protection circuit, which includes a voltage detection circuit 3, an XOR circuit 4, and a filter circuit 5. The voltage detection circuit 3 is connected to the collector of the IGBT 10 and outputs a voltage detection signal 103 corresponding to an on / off state. The XOR circuit 4 outputs the PWM signal 101 and the XOR signal 104 of the voltage detection signal 103. The filter circuit 5 removes a noise pulse contained in the XOR signal 104, and a certain time delay occurs between the PWM signal 101 and the voltage detection signal 103 even in normal operation. The filter circuit 5 removes this noise pulse.

FIG. 2 is a circuit diagram showing an example of a voltage detection circuit in the present embodiment.
In the figure, 31 is a diode, 32 is a Zener diode, 33 and 34 are resistors, and 35 is an inverting element having hysteresis characteristics.
When the IGBT 10 is on, the collector voltage is equal to or lower than the Zener voltage of the Zener diode 32, the input signal of the inverting element 35 is L level, and the voltage detection signal 103 that is the output signal of the inverting element 35 is H level. Further, when the IGBT 10 is turned off or the collector voltage exceeds the Zener voltage of the Zener diode 32 due to the output short circuit of the power converter, etc., the voltage detection signal 103 becomes L level.

Next, the operation will be described.
FIG. 3 is a time chart showing the operation of the present invention. FIG. 3A shows the operation during normal operation, FIG. 3B shows the operation when the output is short-circuited, and FIG. 3-C shows the operation when the IGBT is short-circuited.

First, the operation during normal operation will be described.
In FIG. 3- (a), 101 is a PWM signal, 103 is a voltage detection signal.
As shown in the figure, during the period in which the PWM signal 101 is H, the IGBT 10 is turned on, and the H level voltage detection signal 103 is output from the voltage detection circuit. Further, during the period in which the PWM signal 101 is L, the IGBT 10 is turned off, and the L level voltage detection signal 103 is output from the voltage detection circuit. That is, the PWM signal 101 and the voltage detection signal 103 have substantially the same waveform, although a slight delay occurs in the voltage detection signal 103.
Reference numeral 104 is an XOR signal, and 105 is an error signal. Although a noise pulse is generated in the XOR signal 104 due to the delay of the voltage detection signal 103, it is removed by the filter circuit 5 and the error signal 106 is always at the L level.

Next, the operation when the output is short-circuited will be described.
In FIG. 3B, in the output short-circuit state, the collector voltage of the IGBT 10 does not decrease even though the PWM signal 101 is on (H level), so the voltage detection signal 103 becomes L level. Therefore, the XOR signal 104 becomes H level and the error signal 105 becomes H level. Once the error signal 105 becomes H level, the gate drive signal 102 does not become active, and the gate cutoff state is maintained until the PWM signal 101 is turned off.

Next, the operation when the IGBT is short-circuited will be described.
In FIG. 3C, when the IGBT to be driven is short-circuited, the collector voltage of the IGBT 10 is small even though the PWM signal is off (L level). Become a level. The XOR signal 104 becomes H level during the OFF period of the PWM signal, and an error signal is generated.

  As described above, in this embodiment, since the gate driving device includes the XOR circuit, even if the IGBT is short-circuited, this short-circuit of the IGBT can be detected during the OFF period of the PWM signal. Therefore, a short circuit state can be detected before the paired IGBTs are turned on, and no stress is generated in the paired IGBTs.

FIG. 4 is a block diagram of a gate driving apparatus showing a second embodiment of the present invention.
In the figure, reference numeral 6 denotes a gate cut-off circuit that cuts off the PWM signal by an error signal, and is provided between the PWM generation circuit 1 and the gate drive circuit 2.
The present embodiment is different from the first embodiment in that the gate cutoff circuit 6 is provided in the protection circuit, and the other configurations are the same as those in the first embodiment, so that the description thereof is omitted.

Next, the operation of this embodiment will be described.
FIG. 5 is a circuit diagram showing an example of the gate cutoff circuit in the present embodiment.
In the figure, reference numeral 61 denotes a transistor for blocking the PWM signal.
When the error signal 105 is output from the filter circuit 4, the transistor 61 of the gate cutoff circuit 6 is driven, and the PWM signal 101 input to the gate drive circuit 2 is cut off.

  As described above, in this embodiment, since the error signal is input to the gate cutoff circuit and the supply of the PWM signal is directly blocked, the supply of the gate drive signal is immediately cut off, and the reliability of the power converter is improved.

6 is a block diagram of a gate driving device showing a third embodiment of the present invention.
In the figure, reference numeral 103 denotes a voltage detection signal, and reference numeral 104 denotes an XOR signal, which is input to the host device 110 in which the PWM generation circuit 1 is incorporated. This embodiment is different from the second embodiment in that the XOR signal 104 and the voltage detection signal 103 are supplied to the host device 110.

  As described above, in this embodiment, the XOR signal and the voltage detection signal are supplied to the host device, and by feeding these signals back to the PWM signal generation, a more reliable power control device with good controllability is realized. it can.

The block diagram of the gate drive device which shows 1st Example of this invention The circuit diagram which shows an example of the voltage detection circuit in 1st Example of this invention Time chart showing operation of the present invention Block diagram of a gate driving apparatus showing a second embodiment of the present invention The circuit diagram which shows an example of the gate cutoff circuit in 2nd Example of this invention Block diagram of a gate driving apparatus showing a third embodiment of the present invention. Configuration diagram of conventional power semiconductor element protection device Main circuit configuration diagram of inverter device for explaining problems of conventional power conversion device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 PWM generation circuit 2 Gate drive circuit 3 Voltage detection circuit 31 Diode 32 Zener diode 33, 34 Resistance 35 Inversion element 4 XOR circuit 5 Filter circuit 6 Gate cutoff circuit 61 Transistor 9 Protection circuit 10-14 IGBT
101 PWM signal 102 Gate drive signal 103 Voltage detection signal 104 XOR signal 105 Error signal 110 Host device

Claims (5)

In a gate drive device comprising: a gate drive circuit for amplifying a PWM signal for commanding on / off of a main semiconductor element of a power converter, and generating a gate drive signal for driving the main semiconductor element; and a protection circuit for the main semiconductor element ,
The protection circuit is
A voltage detection circuit connected to a collector of the main semiconductor element and generating a voltage detection signal of the collector;
An XOR circuit for calculating an XOR signal of the PWM signal and the voltage detection signal;
A filter circuit for removing high frequency components of the XOR signal;
A gate driving device comprising:   The gate driving device according to claim 1, wherein the protection circuit includes a gate cutoff circuit that blocks the PWM signal by an output of the filter circuit.   2. The gate driving device according to claim 1, wherein the protection circuit supplies the XOR signal to a host control device that generates the PWM signal.   2. The gate driving device according to claim 1, wherein the protection circuit supplies the voltage detection signal to a host control device that generates the PWM signal.   A power conversion device comprising the gate drive device according to claim 1.

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