JP2004140891A

JP2004140891A - Power converter

Info

Publication number: JP2004140891A
Application number: JP2002301177A
Authority: JP
Inventors: Kenji Takao; 高尾　健志; Hiroshi Masunaga; 益永　博史; Fumio Mizohata; 溝畑　文雄; Hiroshi Nakatake; 中武　浩
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2002-10-16
Filing date: 2002-10-16
Publication date: 2004-05-13
Anticipated expiration: 2022-10-16
Also published as: JP4230190B2

Abstract

<P>PROBLEM TO BE SOLVED: To get a power converter which surely detects short circuit trouble having occurred in some elements in case that the constant voltage elements of a protective circuit against overvoltage are constituted of a plurality of series connection bodies. <P>SOLUTION: An EXOR circuit 50 outputs a signal as long as the tuning delay time of a timing tuning circuit 36 by inputting the signal from an OR circuit 21 and the signal from a delay circuit 20. A time difference judging circuit 51 operates a fault indicator 52 for judging that short circuit fault has occurred in some elements within the constant voltage elements ZD when the above tuning delay time length gets over the specified set time. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
この発明は、自己消弧形半導体素子のオンオフスイッチング動作で電力の変換を行う電力変換装置に係り、特に、上記自己消弧形半導体素子の過電圧抑制の目的で使用される定電圧素子の故障検出に関するものである。
【０００２】
【従来の技術】
自己消弧形半導体素子を使用した電力変換装置では、通例、電圧仕様に応じて、自己消弧形半導体素子、例えば、ＩＧＢＴを複数互いに直列にして直流電圧源に接続し各素子で電圧を分担する構成を採用する。この場合、各ＩＧＢＴは、本来同時にオンオフ動作がなされるが、素子特性のばらつき等により素子間でこのタイミングに差が生じ得る。特に、ターンオフタイミングに差が生じると、早くターンオフした素子に本来の分担電圧以上の電圧が印加されることになり、素子の耐圧が脅かされることになる。
そこで、従来の電力変換装置においては、ＩＧＢＴのコレクタ（正極）とゲート（制御極）との間に定電圧素子ＺＤを含む過電圧保護回路を設け、このＺＤの電圧クランプ動作によりＩＧＢＴの過電圧印加を抑制している。
【０００３】
更に、この電圧クランプ動作が繰り返されることによる損失の増大を防止するため、クランプ動作に応じてＩＧＢＴのターンオフタイミングを調整するタイミング調整回路を設けている（例えば、特許文献１参照）。
【０００４】
【特許文献１】
特開２００１−２３１２４７号公報（第２、３頁、図１、２）
【０００５】
【発明が解決しようとする課題】
従来の電力変換装置は以上のように構成されているが、各ＩＧＢＴの電圧仕様とこれに接続される過電圧保護回路に使用される定電圧素子ＺＤの電圧仕様との関係で、定電圧素子ＺＤを複数の互いに直列に接続した直列接続体で構成することが考えられる。
この回路で、定電圧素子ＺＤが短絡故障した場合を想定すると、その直列接続体の全体が短絡故障とならない限りその一部の素子に短絡故障が発生しても、当該故障が検出されず、過電圧保護回路が過度な電圧抑制を行うなど異常動作が発生し、最悪、ＩＧＢＴを破壊する可能性があるという問題があった。
【０００６】
この発明は、上記のような問題点を解消するためになされたもので、過電圧保護回路の定電圧素子が複数の直列接続体で構成されている場合に、その一部の素子に短絡故障が発生したことを確実に検出することができる電力変換装置を得ることを目的とする。
【０００７】
【課題を解決するための手段】
この発明に係る電力変換装置は、自己消弧形半導体素子のオンオフスイッチング動作で電力の変換を行う電力変換装置であって、
上記自己消弧形半導体素子の正極と制御極との間に定電圧素子を含む過電圧保護回路を設け、上記定電圧素子のクランプ動作により上記自己消弧形半導体素子の正極負極間に印加される過電圧を抑制し、かつ、上記定電圧素子を複数の互いに直列に接続した直列接続体で構成するものにおいて、
上記自己消弧形半導体素子のオフ動作後、上記定電圧素子のクランプ動作に基づき発生する上記自己消弧形半導体素子の制御極負極間電圧の変化を検出し、この変化時間長が所定の設定時間長を越えたとき、上記定電圧素子を構成する直列接続体の一部の素子に短絡故障が発生したと判定する定電圧素子故障検出手段を備えたものである。
【０００８】
【発明の実施の形態】
実施の形態１．
図１〜５は、この発明の実施の形態１を説明するもので、図１は、そのゲートドライブ回路４０の内部構成図、図２は、図１のゲートドライブ回路４０を用いて構成された半導体スイッチ４１の内部構成図、図３は、図２の半導体スイッチ４１を用いて構成された電力変換装置としての３相２レベルインバータを示す回路図、図４は、図１の過電圧保護回路６を説明する図、図５は、図１における定電圧素子の短絡故障の検出動作を説明するタイミングチャートである。
【０００９】
以下、先ず、図１〜４を参照してこの発明の実施の形態１における電力変換装置（３相２レベルインバータ）の構成について説明する。３相２レベルインバータは、直流電圧源Ｅｄに３相ブリッジ結線された半導体スイッチ４１から構成され、直流電圧源Ｅｄの直流電圧を３相交流電圧に変換して出力する（図３）。
ここでは、各半導体スイッチ４１は、互いに直列に接続された２個の自己消弧形半導体素子、ここではＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）２、各ＩＧＢＴ２と逆並列に接続された還流ダイオード３、および各ＩＧＢＴ２をオンオフ駆動するゲートドライブ回路４０から構成される。そして、各ゲートドライブ回路４０は制御信号発生器１からの制御信号に基づき動作する。
【００１０】
次に、ゲートドライブ回路４０の内部構成を図１、図４に基づき説明する。ゲートドライブ回路４０は、過電圧保護回路６と、入力判定回路７と、信号保持回路１３と、パルス成形回路１６とを備えている。
先ず、過電圧保護回路６は２個のＩＧＢＴ２のターンオフタイミングのずれにより印加される過電圧を抑制すると共に、過電圧抑制動作を検出するもので、図４に示すように、一端がＩＧＢＴ２のコレクタＣ（正極）に接続された定電圧素子ＺＤを備えており、ここでは個々の素子ｚｄを複数互いに直列に接続した直列接続体でなる。なお、本願発明の目的は、この直列接続体の任意の素子ｚｄの短絡故障を検出することである。
定電圧素子ＺＤの他端は、ダイオードＤ、更に、ゲートアンプ５、ゲート抵抗４を介してＩＧＢＴ２のゲートＧ（制御極）に接続されている。ダイオードＤのカソードにはＮＰＮトランジスタ２２が接続され定電圧素子ＺＤの電圧クランプ動作による電圧変化により出力し、その出力は、後述するタイミング調整回路３６の入力判定回路７に導出される。
【００１１】
図１に戻り、入力判定回路７は、ディレイ回路１１、ＮＯＴ回路１０およびＯＲ回路９からなるスイッチング過渡状態検出器８とＰＮＰトランジスタ１２とで構成され、制御信号発生器１からの信号と過電圧保護回路６から出力される信号（過電圧保護回路６のＮＰＮトランジスタ２２からの信号で、定電圧素子ＺＤの動作電圧Ｅ１を超える過電圧に対応する信号）とを入力し、過電圧保護回路６から出力される上記信号が、ターンオフ時のスイッチングタイミングずれによってＩＧＢＴ２に過電圧が発生し出力された信号であることを判定する。
即ち、本実施の形態におけるスイッチング過渡状態検出器８は、制御信号発生器１からの信号がターンオフを開始してからディレイ回路１１で定めた時間のみＰＮＰトランジスタ１２を駆動することにより、上記時間に過電圧保護回路６が動作した場合に、過電圧保護回路６から出力される信号を出力してスイッチングタイミングずれによって過電圧が発生したことを判定する。
【００１２】
信号保持回路１３は、コンデンサ（蓄積素子）１５と入力抵抗１４とで構成され、入力判定回路７からの信号（ターンオフ時のスイッチングタイミングずれによって発生する過電圧に対応する信号）を保持する。
パルス成形回路１６は、論理回路１８とＰＮＰトランジスタ１７と抵抗１９とディレイ回路２０とＯＲ回路２１とで構成され、信号保持回路１３のコンデンサ１５に蓄えられた電荷を、複数回のスイッチングに１回の割合でターンオフ時に放電させるとともに、この放電信号と制御信号発生器１からのスイッチング制御信号とにより補正されたスイッチング制御信号を成形する。
即ち、ＯＲ回路２１では入力される放電電圧が予め設定されたしきい値以上の時、オン信号が出力され、最終的には制御信号発生器１からのスイッチング制御信号にこのオン信号が時間的に加算されて出力される、即ち、この加算時間だけターンオフタイミングが遅延調整される。なお、スイッチング制御信号はディレイ回路２０で後述のように所定時間遅延された信号となって加算される。
【００１３】
定電圧素子ｚｄの短絡故障を検出する定電圧素子故障検出手段としての故障検出回路５３は、ＥＸＯＲ回路５０と時間差判定回路５１と故障表示器５２とからなる。そして、ＥＸＯＲ回路５０は、ディレイ回路２０からの出力信号とＯＲ回路２１からの出力信号とを入力して排他的論理和の信号を出力する。即ち、タイミング調整回路３６での調整遅延時間長のパルス信号が出力される。時間差判定回路５１は、この調整遅延時間長が予め設定したマスク時間を越えたとき、定電圧素子ＺＤ内のいずれかの定電圧素子ｚｄに短絡故障が発生したと判定して故障表示器５２を動作させる。
【００１４】
次に、図５を参照して、ターンオフタイミングを調整する動作、および定電圧素子ｚｄの短絡故障を検出する動作について説明する。図５において、（ａ）は信号保持回路１３のコンデンサ１５の電圧、（ｂ）はＰＮＰトランジスタ１７の導通状態、（ｃ）はＯＲ回路２１の入力電圧Ａ、（ｄ）はＩＧＢＴ２のスイッチング状態、（ｅ）はＩＧＢＴ２のコレクターエミッタ間電圧、（ｆ）はＥＸＯＲ回路の出力と時間差判定回路のマスクの関係を示す。図５は２個のＩＧＢＴ２を直列接続した場合の波形を示しており、（ｅ）はターンオフタイミングが早いＩＧＢＴと遅いＩＧＢＴとの両方の電圧波形を示している。また（ａ）〜（ｄ）は早くターンオフするＩＧＢＴに対する波形である。
【００１５】
入力判定回路７は、制御信号発生器１からのスイッチング制御信号がターンオフを開始してからディレイ回路１１で定められた期間だけ、過電圧保護回路６からの信号を通過させる。これにより、早くターンオフしたＩＧＢＴ２のコレクターエミッタ間電圧が過電圧保護回路６の動作電圧Ｅ１を越えた時刻（ｔ１）から、ＩＧＢＴ２のコレクターエミッタ間電圧が過電圧保護回路６の動作電圧Ｅ１より下がった時刻（ｔ２）まで、コンデンサ１５の電圧は上昇する。コンデンサ１５の電圧は過電圧保護回路６の動作量、即ち、動作電圧Ｅ１以上の過電圧のレベル、および過電圧が印加されている時間に応じて上昇する。論理回路１８は制御信号発生器１からのターンオフ信号の複数回に１回の割合（ここでは２回に１回の割合）でＰＮＰトランジスタ１７を駆動する。ＰＮＰトランジスタ１７がオンしたとき（ｔ３）、コンデンサ１５の電圧はコンデンサ１５と抵抗１９の放電回路で放電し低下する。ＯＲ回路２１の入力電圧は、コンデンサ１５の電圧とほぼ等しくなり、ＯＲ回路２１の入力電圧がＯＲ回路２１の入力しきい電圧Ａ１より大きい期間（ｔ３〜ｔ４）、ＩＧＢＴ２のオンは続きスイッチングのタイミングずれは小さくなる。なお、この際、ディレイ回路２０によって、ＰＮＰトランジスタ１７および論理回路１８の時間遅れが補償され、制御信号発生器１からのスイッチング信号と信号保持回路１３からの信号（スイッチングタイミングずれ補正信号）の同期が取られる。
【００１６】
時刻（ｔ５）で定電圧素子ｚｄに短絡故障が発生（過電圧検出部位短絡発生）すると、過電圧保護回路６の動作電圧が正常値のＥ１からＥ２に低下する。そこで、この低下した動作電圧Ｅ２にＩＧＢＴ２のコレクターエミッタ間電圧が達すると、定電圧素子ＺＤによる電圧クランプ動作がその分、長時間（ｔ６〜ｔ７）継続し、コンデンサ１５の電圧が大きく上昇する。この結果、次に論理回路１８からの信号によりＰＮＰトランジスタ１７がオンしてコンデンサ１５が放電すると、その放電電圧が高いため調整遅延時間（ｔ８〜ｔ９）が正常時より長くなり、マスク量を越えて時間差判定回路５１が故障発生と判定して故障表示器５２に出力する。
【００１７】
以上説明したように、過電圧保護回路６の定電圧素子ＺＤ内のいずれかの定電圧素子ｚｄに発生した短絡故障をタイミング調整回路３６による調整遅延時間長から確実に検出することができる。
従って、例えば、この故障検出信号を上位制御回路に送信し装置を停止させるようにすれば、一部の定電圧素子の短絡故障で過度な電圧抑制動作が継続してＩＧＢＴの事故に至るという恐れが無くなり装置の信頼性が向上する。
なお、図１の回路では、調整遅延時間長をＯＲ回路２１の出力信号から求めるようにしたが、ＯＲ回路２１の入力信号、従って、ＰＮＰトランジスタ１７からの信号Ａのパルス時間幅を直接検出するようにしてもよい。
【００１８】
実施の形態２．
図６は、この発明の実施の形態２における電力変換装置のゲートドライブ回路４０を示す回路構成図である。先の実施の形態１の図１と異なるのは、故障検出回路５３のみである。即ち、図６では、電圧レベル判定回路５４を設け、コンデンサ１５の電圧が予め設定した判定レベルを越えると一部の定電圧素子ｚｄに短絡故障が発生したと判定して故障表示器５２を動作させる。
【００１９】
図７に、この故障検出の動作を示す。即ち、時刻（ｔ５）で定電圧素子ｚｄに短絡故障が発生すると、定電圧素子の動作電圧が正常値のＥ１からＥ２に低下する。このため、次に、ターンオフタイミングが早いＩＧＢＴ２のコレクターエミッタ間電圧が上昇して上記動作電圧Ｅ２に達すると、通常より長い時間（ｔ６〜ｔ７）電圧クランプ動作が継続し、結果として、コンデンサ１５への充電時間が増え、図７（ａ）に示すように、コンデンサ１５の電圧が正常時より高くなって設定された判定レベルを越え、電圧レベル判定回路５４が故障を検出する。
【００２０】
以上のように、過電圧保護回路６の定電圧素子ＺＤ内のいずれかの定電圧素子ｚｄに発生した短絡故障をタイミング調整回路３６のコンデンサ１５の電圧から確実に検出することができ、実施の形態１と同様、装置の信頼性が向上する。
【００２１】
実施の形態３．
図８は、この発明の実施の形態３における電力変換装置を示す回路構成図である。ここでは、先の実施の形態で説明したゲートドライブ回路４０の構成を一部簡略化しても定電圧素子の短絡故障を検出できる場合について説明する。
即ち、互いに直列に接続された２個のＩＧＢＴ２の一方に接続されたゲートドライブ回路４０は、先の実施の形態１と同様、定電圧素子ＺＤの電圧クランプ動作に基づきＩＧＢＴ２のターンオフタイミングを遅延調整するタイミング調整回路３６とこの調整遅延時間長がマスク量を越えたことから定電圧素子ＺＤの一部での短絡故障を検出する故障検出回路５３の両回路を備えている（故障検出手段付自己消弧形半導体素子）。これに対し、他方のＩＧＢＴ２に接続されたゲートドライブ回路４０Ａは、タイミング調整回路３６は存在するが故障検出回路５３は存在しない、構成を一部簡略化したものである（故障検出手段無自己消弧形半導体素子）。
【００２２】
次に、定電圧素子ＺＤの一部短絡故障時の動作について説明する。先ず、ゲートドライブ回路４０側で発生した短絡故障は、当該ゲートドライブ回路４０に故障検出回路５３を備えているので、形態１で既述したとおり可能であるのは言うまでもない。
問題は、故障検出回路５３を備えていないゲートドライブ回路４０Ａ側で短絡故障が発生した場合である。この場合、先ず、故障検出回路無しのゲートドライブ回路４０Ａ側でタイミング調整回路３６による調整遅延時間長が増大する。増大するが故障検出回路が無いのでそのＩＧＢＴのターンオフタイミングは調整の結果遅れていく。従って、相対的に故障検出回路付のゲートドライブ回路４０側のＩＧＢＴのターンオフタイミングが早まることになる。そして、この早まり量が大きくなるとゲートドライブ回路４０側での調整遅延時間長が次第に高まり、当該ゲートドライブ回路４０側の定電圧素子ＺＤには異常が無くても調整遅延時間長が設定されたマスク量を越え得ることになり、やがてゲートドライブ回路４０に備えられた故障検出回路５３が故障検出の判定を行うことになる。
【００２３】
複数のＩＧＢＴを直列にして直流電圧源に接続する場合、各素子のターンオフタイミングの相対的ずれにより以上で説明した現象が生じるので、この現象を利用することにより、その複数のゲートドライブ回路の一部で故障検出回路を省略しても、当該故障検出回路を省略したゲートドライブ回路で発生した定電圧素子ＺＤの一部短絡故障を、他のゲートドライブ回路に備えられた故障検出回路５３により検出することが可能になり、全体として、装置の構成を簡便安価にすることができる。
なお、図８のゲートドライブ回路４０として、以上の説明では、実施の形態１の、即ち、調整遅延時間長から定電圧素子の短絡故障を検出する故障検出回路を備えたものとしたが、実施の形態２の、即ち、コンデンサ１５の電圧から短絡故障を検出する故障検出回路を備えたものとしてもよいことは言うまでもない。
【００２４】
実施の形態４．
以上の各実施の形態では、いずれも、ＩＧＢＴは複数直列にして直流電圧源に接続するものであり、かつ、ＩＧＢＴのターンオフタイミングを調整するタイミング調整回路を備えたものを前提にしているが、これらの前提が存在しない場合においても、ＩＧＢＴを過電圧から保護するため、定電圧素子ＺＤを含む過電圧保護回路を設けることがあり、更に、この定電圧素子ＺＤを複数の定電圧素子ｚｄの直列接続体で構成する場合がある。実施の形態４では、このような場合にも、定電圧素子ＺＤの一部の短絡故障を確実に検出することができる電力変換装置を扱うものである。
【００２５】
図９は、この発明の実施の形態４における故障検出回路を含む電力変換装置を示す回路構成図である。図において、ＩＧＢＴのコレクターゲート間に定電圧素子ＺＤとダイオードＤが接続されている。なお、定電圧素子ＺＤは便宜上、単体で図示しているが、実際は定電圧素子ｚｄを複数直列に接続したものである点は、先の実施の形態の図４で示したものと同様である。そして、この実施の形態４は、この定電圧素子ＺＤ内の一部の素子ｚｄの短絡故障を検出するものである。
以下、動作を示す図１０のタイミングチャートを共に参照して説明する。
ここでは、タイミング調整回路が無いので、（制御信号発生器１）からのオン・オフ信号はインターフェイス回路２３を介して直接トランジスタＴＲ１、ＴＲ２に出力される。ＩＧＢＴのオン時は、トランジスタＴＲ１をオン、ＴＲ２をオフしてゲートーエミッタ間電圧ＶＧＥ＝Ｐ１５Ｖとする。ＩＧＢＴのターンオフ時は、トランジスタＴＲ１をオフ、ＴＲ２をオンに操作してＶＧＥ＝Ｎ１５Ｖとする。この状態からＩＧＢＴのコレクターエミッタ間に過電圧が印加されこれが定電圧素子ＺＤのアバランシェ電圧に達すると、定電圧素子ＺＤが電圧クランプ動作をし、定電圧素子ＺＤを介してゲートに漏れ電流ＩＺＤが流れ（図１０（ｂ））、ＶＧＥは順バイアス方向に充電されＩＧＢＴがオンするスレッシホールド電圧（普通＋１０Ｖ程度）に引き上げられる（図１０（ｃ））。これによりＩＧＢＴのコレクターエミッタ間電圧は定電圧素子ＺＤのアバランシェ電圧にクランプされるわけである。
【００２６】
比較器２５は、ＩＧＢＴのゲートーエミッタ間電圧ＶＧＥを入力し、しきい値電圧ＲＥＦ（図１０（ｃ））と比較して前者が大きいときＨレベルの信号を出力する（図１０（ｄ）ＣＭＰ出力）。
ディレイ回路２４は、ＨレベルからＬレベルになるＯＦＦ指令タイミング（図１０（ａ）参照）から所定の時間遅延してＬレベルになる信号を出力する（図１０（ｅ））。この遅延時間は、定電圧素子ＺＤが正常な場合に、ＩＧＢＴがターンオフした後、電圧クランプ動作終了時点までの時間の最大予測値にほぼ近い値に設定される。
ＥＸＯＲ回路２６は、比較器２５からの信号とディレイ回路２４からの信号との排他的論理和を演算する。そして、ＡＮＤ回路２８はこのＥＸＯＲ回路２６からの信号とインバータ回路２７によるディレイ回路２４の反転信号との論理積を演算する。
【００２７】
従って、定電圧素子ＺＤが全て正常で電圧クランプ動作がディレイ回路２４による設定遅延時間までに終了する場合は、ＡＮＤ回路２８からのＡＮＤ信号はＬレベルを維持するが、定電圧素子ＺＤの一部の素子で短絡故障が発生し電圧クランプ動作が上記設定遅延時間を越えて継続すると、図１０（ｈ）に示すように、単パルス信号Ｓを出力し、これにより、定電圧素子ＺＤの一部短絡故障を検出することができ、装置の信頼性が向上する。
なお、図９では、ＡＮＤ回路２８の後段にワンショット回路２９を挿入してＺＤ故障信号としているが、ＡＮＤ回路２８からのＡＮＤ信号が短いときでも、図示しない上位回路でのラッチが可能となるようパルス幅を伸ばすためである。
【００２８】
この実施の形態４は、例えば、ＩＧＢＴを直列接続しない２レベルインバータにおいて、ＩＧＢＴのターンオフ時に発生するサージをスナバ回路ではなくＩＧＢＴに接続した定電圧素子ＺＤでクランプして過電圧から保護する回路に適用した場合に有効であり、定電圧素子ＺＤの一部故障からインバータの故障に進展することを未然に防止することができる。
なお、図９に示した構成に限定されることはなく、要は、ＩＧＢＴのターンオフ後、定電圧素子ＺＤの電圧クランプ動作に基づく、ＩＧＢＴのゲートーエミッタ間電圧の変化時間長を検出するものであれば、上記で説明したと同様の要領で定電圧素子ＺＤの一部短絡故障を検出することができる。
【００２９】
実施の形態５．
図１１は、この発明の実施の形態５における電力変換装置を示し、ここでは、特に、ＩＧＢＴを過電圧から保護する定電圧素子ＺＤの電流定格を低減する方策について説明する。即ち、先の実施の形態４で説明したように、ＩＧＢＴのコレクターエミッタ間に過電圧が印加され、定電圧素子ＺＤがクランプすると、定電圧素子ＺＤを介して電流がゲートに流れるが、この電流値は、それまでのオフ操作で抵抗Ｒｇ（ｏｆｆ）を介してＮ１５Ｖが印加されていたゲートーエミッタ間電圧ＶＧＥをＩＧＢＴがオンするスレッシホールド電圧（普通＋１０Ｖ程度）にまで引き上げるレベルのものである必要がある。Ｒｇ＝１０Ωとすると、（＋１０Ｖ−（−１５Ｖ））／１０Ω＝２．５Ａとなり、定電圧素子ＺＤとして電流定格の大きなものを採用する必要がある。
特に、定電圧素子ＺＤを複数の素子の直列接続体で構成するような高電圧仕様の場合はこの電流定格が大きいことで定電圧素子ＺＤが大容量なものとなる。
【００３０】
図１１の回路は、この定電圧素子ＺＤの電流定格低減を実現するもので、ＮＰＮトランジスタ３２およびＰＦＥＴ３３からなるＡＭＰ部３１を備えている。なお、図１１では、実施の形態１の内容との整合性を図るため、定電圧素子ＺＤの電圧クランプ動作に基づきＩＧＢＴのターンオフタイミングを調整するタイミング調整回路３６を備えたものに適用している。但し、説明の便宜上、図１等ではタイミング調整回路３６内に存在するＰＮＰトランジスタ１２、入力抵抗１４およびコンデンサ１５を外部に引き出して図示している。
【００３１】
次に動作について説明する。トランジスタＴＲ１をオフ、ＴＲ２をオンに操作してＶＧＥ＝Ｎ１５ＶとしＩＧＢＴがターンオフする。この状態からＩＧＢＴのコレクターエミッタ間に過電圧が印加されこれが定電圧素子ＺＤのアバランシェ電圧に達すると、定電圧素子ＺＤに電流が流れてクランプ動作に入るが、その電流値は、図１１の負担抵抗にＮＰＮトランジスタ３２を駆動させるに必要な電圧を誘起させるレベルで足りるので、数ｍＡ〜数十ｍＡ程度でよい。ＮＰＮトランジスタ３２の動作でＰＦＥＴ３３が駆動し、ＩＧＢＴのゲートに必要な電流が供給される。定電圧素子ＺＤのクランプ動作が実行されると定電圧素子ＺＤの電流はなくなり、ＰＦＥＴ３３もオフする。
負担抵抗の電圧変化でＮＰＮトランジスタ２２がオンし、ＰＮＰトランジスタ１２を経てコンデンサ１５が充電され、更に、このコンデンサ１５の充電電圧に基づきＩＧＢＴのターンオフタイミングが調整される動作は先の実施の形態１と同様である。
【００３２】
以上のように、この実施の形態５においては、定電圧素子ＺＤの電流定格を大幅に低減することができ、サイズ、コストの低減が可能となる。
【００３３】
なお、以上の各実施の形態では、自己消弧形半導体素子としてＩＧＢＴを使用した場合について説明したが、他の種類の自己消弧形半導体素子であっても同様に適用でき同等の効果を奏する。また、これら素子を直流電圧源に直列接続した複数の素子で構成する場合、以上の形態例で例示した２個で構成する場合に限られるものではない。
【００３４】
【発明の効果】
以上のように、この発明に係る電力変換装置は、自己消弧形半導体素子のオンオフスイッチング動作で電力の変換を行う電力変換装置であって、
上記自己消弧形半導体素子の正極と制御極との間に定電圧素子を含む過電圧保護回路を設け、上記定電圧素子のクランプ動作により上記自己消弧形半導体素子の正極負極間に印加される過電圧を抑制し、かつ、上記定電圧素子を複数の互いに直列に接続した直列接続体で構成するものにおいて、
上記自己消弧形半導体素子のオフ動作後、上記定電圧素子のクランプ動作に基づき発生する上記自己消弧形半導体素子の制御極負極間電圧の変化を検出し、この変化時間長が所定の設定時間長を越えたとき、上記定電圧素子を構成する直列接続体の一部の素子に短絡故障が発生したと判定する定電圧素子故障検出手段を備えたので、簡単な構成で定電圧素子の一部素子で発生した短絡故障を確実に検出することができ、過電圧保護回路が過度な電圧抑制を行うなど異常動作の発生を未然に防止し、この異常動作に伴い自己消弧形半導体素子が破壊するという恐れもなくなる。
【図面の簡単な説明】
【図１】この発明の実施の形態１の電力変換装置におけるゲートドライブ回路４０の内部構成を示す図である。
【図２】図１のゲートドライブ回路４０を用いて構成された半導体スイッチ４１の内部構成を示す図である。
【図３】図２の半導体スイッチ４１を用いて構成された電力変換装置としての３相２レベルインバータを示す回路図である。
【図４】図１の過電圧保護回路６を説明する図である。
【図５】図１における定電圧素子の短絡故障の検出動作を説明するタイミングチャートである。
【図６】この発明の実施の形態２の電力変換装置におけるゲートドライブ回路４０の内部構成を示す図である。
【図７】図６における定電圧素子の短絡故障の検出動作を説明するタイミングチャートである。
【図８】この発明の実施の形態３における電力変換装置を示す図である。
【図９】この発明の実施の形態４における電力変換装置を示す図である。
【図１０】図９における定電圧素子の短絡故障の検出動作を説明するタイミングチャートである。
【図１１】この発明の実施の形態５における電力変換装置を示す図である。
【符号の説明】
１　制御信号発生器、２　ＩＧＢＴ、６　過電圧保護回路、
７　入力判定回路、１３　信号保持回路、１５　コンデンサ、
１６　パルス成形回路、３０　故障検出回路、３１　ＡＭＰ部、
３６　タイミング調整回路、４０　（故障検出回路付）ゲートドライブ回路、
４０Ａ　故障検出回路無ゲートドライブ回路、４１　半導体スイッチ、
５０　ＥＸＯＲ回路、５１　時間差判定回路、５３　故障検出回路、
５４　電圧レベル判定回路、Ｅｄ　直流電圧源。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power conversion device that converts power by an on / off switching operation of a self-extinguishing semiconductor element, and more particularly, to detect a failure of a constant voltage element used for the purpose of suppressing an overvoltage of the self-extinguishing semiconductor element. It is about.
[0002]
[Prior art]
In power converters using self-extinguishing semiconductor elements, usually, self-extinguishing semiconductor elements, for example, multiple IGBTs are connected in series with each other and connected to a DC voltage source according to the voltage specifications, and each element shares the voltage Adopt the configuration to do. In this case, each IGBT is originally turned on and off at the same time, but there may be a difference in timing between elements due to variations in element characteristics. In particular, when a difference occurs in the turn-off timing, a voltage higher than the original shared voltage is applied to the element that is turned off earlier, and the breakdown voltage of the element is threatened.
Therefore, in the conventional power converter, an overvoltage protection circuit including a constant voltage element ZD is provided between the collector (positive electrode) and gate (control electrode) of the IGBT, and the overvoltage application of the IGBT is performed by the voltage clamping operation of the ZD. Suppressed.
[0003]
Further, in order to prevent an increase in loss due to the repetition of the voltage clamping operation, a timing adjustment circuit that adjusts the turn-off timing of the IGBT according to the clamping operation is provided (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP 2001-231247 A (2nd and 3rd pages, FIGS. 1 and 2)
[0005]
[Problems to be solved by the invention]
The conventional power conversion device is configured as described above, but the constant voltage element ZD is related to the voltage specification of each IGBT and the voltage specification of the constant voltage element ZD used in the overvoltage protection circuit connected thereto. It is conceivable to form a plurality of serially connected bodies connected in series.
In this circuit, assuming that the constant voltage element ZD has a short-circuit failure, even if a short-circuit failure occurs in some of the elements unless the entire series-connected body becomes a short-circuit failure, the failure is not detected, An abnormal operation such as excessive voltage suppression by the overvoltage protection circuit occurs, and there is a problem that the IGBT may be destroyed in the worst case.
[0006]
The present invention has been made to solve the above-described problems. When the constant voltage element of the overvoltage protection circuit is composed of a plurality of serially connected bodies, a short circuit failure occurs in some of the elements. It aims at obtaining the power converter device which can detect reliably having generate | occur | produced.
[0007]
[Means for Solving the Problems]
A power conversion device according to the present invention is a power conversion device that performs power conversion by an on / off switching operation of a self-extinguishing semiconductor element,
An overvoltage protection circuit including a constant voltage element is provided between the positive electrode and the control electrode of the self-extinguishing semiconductor element, and is applied between the positive and negative electrodes of the self-extinguishing semiconductor element by a clamping operation of the constant voltage element. In what constitutes a series connection body in which overvoltage is suppressed and the constant voltage elements are connected in series to each other,
After the self-extinguishing semiconductor element is turned off, a change in the voltage between the control pole and negative electrode of the self-extinguishing semiconductor element generated based on the clamping operation of the constant voltage element is detected, and the change time length is set to a predetermined value. When the time length is exceeded, there is provided a constant voltage element failure detecting means for determining that a short circuit failure has occurred in some elements of the series connection body constituting the constant voltage element.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
1 to 5 illustrate the first embodiment of the present invention. FIG. 1 is an internal configuration diagram of the gate drive circuit 40, and FIG. 2 is configured using the gate drive circuit 40 of FIG. FIG. 3 is a circuit diagram showing a three-phase two-level inverter as a power conversion device configured using the semiconductor switch 41 of FIG. 2, and FIG. 4 is an overvoltage protection circuit 6 of FIG. FIG. 5 is a timing chart for explaining the detection operation of the short-circuit fault of the constant voltage element in FIG.
[0009]
Hereinafter, first, the configuration of the power conversion device (three-phase two-level inverter) in the first embodiment of the present invention will be described with reference to FIGS. The three-phase two-level inverter includes a semiconductor switch 41 that is three-phase bridge-connected to the DC voltage source Ed, and converts the DC voltage of the DC voltage source Ed into a three-phase AC voltage and outputs the converted voltage (FIG. 3).
Here, each semiconductor switch 41 includes two self-extinguishing semiconductor elements connected in series with each other, here, an IGBT (Insulated Gate Bipolar Transistor) 2, a free-wheeling diode 3 connected in antiparallel with each IGBT 2, and The gate drive circuit 40 is configured to drive each IGBT 2 on and off. Each gate drive circuit 40 operates based on a control signal from the control signal generator 1.
[0010]
Next, the internal configuration of the gate drive circuit 40 will be described with reference to FIGS. The gate drive circuit 40 includes an overvoltage protection circuit 6, an input determination circuit 7, a signal holding circuit 13, and a pulse shaping circuit 16.
First, the overvoltage protection circuit 6 suppresses an overvoltage applied due to a shift in the turn-off timing of the two IGBTs 2 and detects an overvoltage suppression operation. As shown in FIG. 4, one end is a collector C (positive electrode) of the IGBT 2. And a constant voltage element ZD connected to each other). Here, a plurality of individual elements zd are connected in series. The object of the present invention is to detect a short-circuit fault of an arbitrary element zd of this series connection body.
The other end of the constant voltage element ZD is connected to the gate G (control pole) of the IGBT 2 via the diode D, the gate amplifier 5 and the gate resistor 4. An NPN transistor 22 is connected to the cathode of the diode D, and output by a voltage change caused by the voltage clamping operation of the constant voltage element ZD. The output is led to the input determination circuit 7 of the timing adjustment circuit 36 described later.
[0011]
Returning to FIG. 1, the input determination circuit 7 includes a switching transient state detector 8 including a delay circuit 11, a NOT circuit 10, and an OR circuit 9 and a PNP transistor 12, and a signal from the control signal generator 1 and overvoltage protection. A signal output from the circuit 6 (a signal from the NPN transistor 22 of the overvoltage protection circuit 6 and corresponding to an overvoltage exceeding the operating voltage E1 of the constant voltage element ZD) is input and output from the overvoltage protection circuit 6 It is determined that the signal is a signal that is output because an overvoltage is generated in the IGBT 2 due to a switching timing deviation at the time of turn-off.
That is, the switching transient state detector 8 in the present embodiment drives the PNP transistor 12 only for the time determined by the delay circuit 11 after the signal from the control signal generator 1 starts to turn off. When the overvoltage protection circuit 6 is operated, a signal output from the overvoltage protection circuit 6 is output to determine that an overvoltage has occurred due to a switching timing deviation.
[0012]
The signal holding circuit 13 includes a capacitor (storage element) 15 and an input resistor 14, and holds a signal from the input determination circuit 7 (a signal corresponding to an overvoltage generated due to a switching timing deviation at turn-off).
The pulse shaping circuit 16 includes a logic circuit 18, a PNP transistor 17, a resistor 19, a delay circuit 20, and an OR circuit 21, and charges accumulated in the capacitor 15 of the signal holding circuit 13 once for a plurality of switching operations. At the time of turn-off, the switching control signal corrected by the discharge signal and the switching control signal from the control signal generator 1 is formed.
That is, in the OR circuit 21, when the input discharge voltage is equal to or higher than a preset threshold value, an ON signal is output, and this ON signal is finally added to the switching control signal from the control signal generator 1 over time. In other words, the turn-off timing is delayed and adjusted by this addition time. The switching control signal is added as a signal delayed by a predetermined time in the delay circuit 20 as described later.
[0013]
A failure detection circuit 53 as a constant voltage element failure detection means for detecting a short-circuit failure of the constant voltage element zd includes an EXOR circuit 50, a time difference determination circuit 51, and a failure indicator 52. The EXOR circuit 50 receives the output signal from the delay circuit 20 and the output signal from the OR circuit 21 and outputs an exclusive OR signal. That is, a pulse signal having an adjustment delay time length in the timing adjustment circuit 36 is output. When the adjustment delay time length exceeds a preset mask time, the time difference determination circuit 51 determines that a short circuit failure has occurred in any one of the constant voltage elements zd in the constant voltage element ZD, and displays the failure indicator 52. Make it work.
[0014]
Next, an operation for adjusting the turn-off timing and an operation for detecting a short-circuit failure of the constant voltage element zd will be described with reference to FIG. 5, (a) is the voltage of the capacitor 15 of the signal holding circuit 13, (b) is the conduction state of the PNP transistor 17, (c) is the input voltage A of the OR circuit 21, (d) is the switching state of the IGBT 2, (E) shows the collector-emitter voltage of the IGBT 2, and (f) shows the relationship between the output of the EXOR circuit and the mask of the time difference determination circuit. FIG. 5 shows a waveform when two IGBTs 2 are connected in series, and (e) shows voltage waveforms of both an IGBT with early turn-off timing and a later IGBT. Further, (a) to (d) are waveforms for the IGBT that turns off early.
[0015]
The input determination circuit 7 allows the signal from the overvoltage protection circuit 6 to pass for a period determined by the delay circuit 11 after the switching control signal from the control signal generator 1 starts to turn off. As a result, the collector-emitter voltage of the IGBT 2 that is turned off earlier exceeds the operating voltage E1 of the overvoltage protection circuit 6 (t1), and the time when the collector-emitter voltage of the IGBT2 falls below the operating voltage E1 of the overvoltage protection circuit 6 ( Until t2), the voltage of the capacitor 15 rises. The voltage of the capacitor 15 increases according to the operation amount of the overvoltage protection circuit 6, that is, the level of the overvoltage equal to or higher than the operation voltage E1 and the time during which the overvoltage is applied. The logic circuit 18 drives the PNP transistor 17 at a rate of once per a plurality of turn-off signals from the control signal generator 1 (here, once every two times). When the PNP transistor 17 is turned on (t3), the voltage of the capacitor 15 is discharged by the discharge circuit of the capacitor 15 and the resistor 19 and decreases. The input voltage of the OR circuit 21 is substantially equal to the voltage of the capacitor 15, and during the period (t3 to t4) when the input voltage of the OR circuit 21 is greater than the input threshold voltage A1 of the OR circuit 21, the IGBT2 continues to be turned on and the switching timing. Deviation is reduced. At this time, the delay circuit 20 compensates for the time delay of the PNP transistor 17 and the logic circuit 18, and synchronizes the switching signal from the control signal generator 1 and the signal (switching timing deviation correction signal) from the signal holding circuit 13. Is taken.
[0016]
When a short-circuit failure occurs in the constant voltage element zd at time (t5) (overvoltage detection site short-circuit occurrence), the operating voltage of the overvoltage protection circuit 6 decreases from the normal value E1 to E2. Therefore, when the collector-emitter voltage of the IGBT 2 reaches the lowered operating voltage E2, the voltage clamping operation by the constant voltage element ZD is continued for a long time (t6 to t7), and the voltage of the capacitor 15 is greatly increased. As a result, when the PNP transistor 17 is next turned on by the signal from the logic circuit 18 and the capacitor 15 is discharged, the adjustment delay time (t8 to t9) becomes longer than normal because the discharge voltage is high, exceeding the mask amount. Thus, the time difference determination circuit 51 determines that a failure has occurred and outputs it to the failure indicator 52.
[0017]
As described above, it is possible to reliably detect a short-circuit failure occurring in any one of the constant voltage elements zd in the constant voltage element ZD of the overvoltage protection circuit 6 from the adjustment delay time length by the timing adjustment circuit 36.
Therefore, for example, if this failure detection signal is sent to the host control circuit to stop the apparatus, excessive voltage suppression operation may continue due to a short-circuit failure of some constant voltage elements, leading to an IGBT accident. And the reliability of the device is improved.
In the circuit of FIG. 1, the adjustment delay time length is obtained from the output signal of the OR circuit 21, but the input signal of the OR circuit 21, and therefore the pulse time width of the signal A from the PNP transistor 17 is directly detected. You may do it.
[0018]
Embodiment 2. FIG.
FIG. 6 is a circuit configuration diagram showing a gate drive circuit 40 of the power conversion device according to Embodiment 2 of the present invention. Only the failure detection circuit 53 is different from FIG. 1 of the first embodiment. That is, in FIG. 6, a voltage level determination circuit 54 is provided, and when the voltage of the capacitor 15 exceeds a predetermined determination level, it is determined that a short circuit failure has occurred in some constant voltage elements zd and the failure indicator 52 is operated. Let
[0019]
FIG. 7 shows this failure detection operation. That is, when a short-circuit failure occurs in the constant voltage element zd at time (t5), the operating voltage of the constant voltage element decreases from the normal value E1 to E2. Therefore, when the collector-emitter voltage of the IGBT 2 whose turn-off timing is early rises and reaches the operating voltage E2, the voltage clamping operation continues for a longer time (t6 to t7) than usual, and as a result, to the capacitor 15. As shown in FIG. 7A, the voltage of the capacitor 15 is higher than normal and exceeds the set determination level, and the voltage level determination circuit 54 detects a failure.
[0020]
As described above, it is possible to reliably detect a short-circuit failure occurring in any one of the constant voltage elements zd in the constant voltage element ZD of the overvoltage protection circuit 6 from the voltage of the capacitor 15 of the timing adjustment circuit 36. As in 1, the reliability of the apparatus is improved.
[0021]
Embodiment 3 FIG.
FIG. 8 is a circuit configuration diagram showing a power conversion device according to Embodiment 3 of the present invention. Here, a case will be described in which a short-circuit fault of a constant voltage element can be detected even if the configuration of the gate drive circuit 40 described in the previous embodiment is partially simplified.
That is, the gate drive circuit 40 connected to one of the two IGBTs 2 connected in series with each other delays the turn-off timing of the IGBT 2 based on the voltage clamping operation of the constant voltage element ZD, as in the first embodiment. And a failure detection circuit 53 for detecting a short-circuit failure in a part of the constant voltage element ZD because the adjustment delay time length exceeds the mask amount (self-with failure detection means). Arc extinguishing type semiconductor device). On the other hand, the gate drive circuit 40A connected to the other IGBT 2 has a partially simplified configuration in which the timing adjustment circuit 36 is present but the failure detection circuit 53 is not present (no failure detection means self-extinguishing). Arc-shaped semiconductor device).
[0022]
Next, the operation at the time of a partial short-circuit failure of the constant voltage element ZD will be described. First, it is needless to say that a short circuit failure occurring on the gate drive circuit 40 side is possible as described in the first embodiment because the gate drive circuit 40 includes the failure detection circuit 53.
The problem is when a short-circuit failure occurs on the side of the gate drive circuit 40A that does not include the failure detection circuit 53. In this case, first, the adjustment delay time length by the timing adjustment circuit 36 increases on the gate drive circuit 40A side without the failure detection circuit. Although there is no failure detection circuit, the IGBT turn-off timing is delayed as a result of adjustment. Accordingly, the turn-off timing of the IGBT on the gate drive circuit 40 side with the failure detection circuit is relatively advanced. When the amount of advance is increased, the adjustment delay time length on the gate drive circuit 40 side gradually increases, and the constant delay element ZD on the gate drive circuit 40 side is set with the adjustment delay time length even if there is no abnormality. As a result, the failure detection circuit 53 provided in the gate drive circuit 40 determines the failure detection.
[0023]
When a plurality of IGBTs are connected in series to a DC voltage source, the phenomenon described above occurs due to the relative shift of the turn-off timing of each element. By utilizing this phenomenon, one of the plurality of gate drive circuits is used. Even if the failure detection circuit is omitted in the part, a partial short-circuit failure of the constant voltage element ZD generated in the gate drive circuit in which the failure detection circuit is omitted is detected by the failure detection circuit 53 provided in another gate drive circuit. As a whole, the configuration of the apparatus can be simplified and made inexpensive.
In the above description, the gate drive circuit 40 of FIG. 8 is provided with the failure detection circuit that detects the short-circuit failure of the constant voltage element from the adjustment delay time length in the first embodiment. It goes without saying that a failure detection circuit for detecting a short-circuit failure from the voltage of the capacitor 15 may be provided.
[0024]
Embodiment 4 FIG.
In each of the above-described embodiments, it is assumed that a plurality of IGBTs are connected in series to a DC voltage source and have a timing adjustment circuit that adjusts the turn-off timing of the IGBT. Even when these preconditions do not exist, an overvoltage protection circuit including a constant voltage element ZD may be provided in order to protect the IGBT from overvoltage, and the constant voltage element ZD is connected in series with a plurality of constant voltage elements zd. May consist of body. In the fourth embodiment, even in such a case, a power conversion device that can reliably detect a short-circuit failure in a part of the constant voltage element ZD is handled.
[0025]
FIG. 9 is a circuit configuration diagram showing a power conversion device including a failure detection circuit according to Embodiment 4 of the present invention. In the figure, a constant voltage element ZD and a diode D are connected between the collector gate of the IGBT. Note that the constant voltage element ZD is shown as a single unit for convenience, but the fact that a plurality of constant voltage elements zd are connected in series is the same as that shown in FIG. 4 of the previous embodiment. . In the fourth embodiment, a short circuit failure of a part of the elements zd in the constant voltage element ZD is detected.
Hereinafter, the operation will be described with reference to the timing chart of FIG.
Here, since there is no timing adjustment circuit, the ON / OFF signal from (control signal generator 1) is directly output to the transistors TR1 and TR2 via the interface circuit 23. When the IGBT is on, the transistor TR1 is turned on and TR2 is turned off so that the gate-emitter voltage VGE = P15V. When the IGBT is turned off, the transistor TR1 is turned off and TR2 is turned on so that VGE = N15V. From this state, when an overvoltage is applied between the collector and emitter of the IGBT and this reaches the avalanche voltage of the constant voltage element ZD, the constant voltage element ZD performs a voltage clamping operation, and a leakage current IZD flows to the gate via the constant voltage element ZD. (FIG. 10 (b)), VGE is charged in the forward bias direction and raised to a threshold voltage (usually about + 10V) that turns on the IGBT (FIG. 10 (c)). Thereby, the collector-emitter voltage of the IGBT is clamped to the avalanche voltage of the constant voltage element ZD.
[0026]
The comparator 25 receives the gate-emitter voltage VGE of the IGBT, and outputs an H level signal when the former is larger than the threshold voltage REF (FIG. 10C) (FIG. 10D). CMP output).
The delay circuit 24 outputs a signal that becomes L level after a predetermined time delay from the OFF command timing (see FIG. 10A) that changes from H level to L level (FIG. 10E). When the constant voltage element ZD is normal, this delay time is set to a value that is substantially close to the maximum predicted value of the time from when the IGBT is turned off to when the voltage clamping operation ends.
The EXOR circuit 26 calculates an exclusive OR of the signal from the comparator 25 and the signal from the delay circuit 24. The AND circuit 28 calculates a logical product of the signal from the EXOR circuit 26 and the inverted signal of the delay circuit 24 by the inverter circuit 27.
[0027]
Accordingly, when all the constant voltage elements ZD are normal and the voltage clamping operation is completed by the set delay time by the delay circuit 24, the AND signal from the AND circuit 28 maintains the L level, but a part of the constant voltage element ZD. When a short-circuit failure occurs in the element and the voltage clamping operation continues beyond the set delay time, a single pulse signal S is output as shown in FIG. 10 (h), whereby a part of the constant voltage element ZD is output. Short circuit faults can be detected, improving the reliability of the device.
In FIG. 9, a one-shot circuit 29 is inserted after the AND circuit 28 to generate a ZD fault signal. However, even when the AND signal from the AND circuit 28 is short, it can be latched by an upper circuit (not shown). This is for extending the pulse width.
[0028]
The fourth embodiment is applied to, for example, a circuit that protects from overvoltage by clamping a surge generated at IGBT turn-off with a constant voltage element ZD connected to the IGBT instead of a snubber circuit in a two-level inverter without IGBTs connected in series. In this case, it is effective to prevent the constant voltage element ZD from progressing partially to inverter failure.
9 is not limited to the configuration shown in FIG. 9. The point is to detect the change time length of the gate-emitter voltage of the IGBT based on the voltage clamping operation of the constant voltage element ZD after the IGBT is turned off. If so, a partial short-circuit fault of the constant voltage element ZD can be detected in the same manner as described above.
[0029]
Embodiment 5. FIG.
FIG. 11 shows a power conversion apparatus according to Embodiment 5 of the present invention, and here, in particular, a measure for reducing the current rating of the constant voltage element ZD that protects the IGBT from overvoltage will be described. That is, as described in the fourth embodiment, when an overvoltage is applied between the collector and emitter of the IGBT and the constant voltage element ZD is clamped, a current flows to the gate via the constant voltage element ZD. Is a level that raises the gate-emitter voltage VGE, to which the N15V has been applied via the resistor Rg (off), until the threshold voltage (usually about + 10V) at which the IGBT is turned on by the off-operation until then. There is a need. When Rg = 10Ω, (+ 10V − (− 15V)) / 10Ω = 2.5A, and it is necessary to employ a constant voltage element ZD having a large current rating.
In particular, in the case of a high voltage specification in which the constant voltage element ZD is constituted by a series connection body of a plurality of elements, the constant voltage element ZD has a large capacity due to the large current rating.
[0030]
The circuit shown in FIG. 11 realizes a reduction in the current rating of the constant voltage element ZD, and includes an AMP unit 31 including an NPN transistor 32 and a PFET 33. In FIG. 11, in order to achieve consistency with the contents of the first embodiment, the present invention is applied to a device including a timing adjustment circuit 36 that adjusts the turn-off timing of the IGBT based on the voltage clamping operation of the constant voltage element ZD. . However, for convenience of explanation, in FIG. 1 and the like, the PNP transistor 12, the input resistor 14, and the capacitor 15 existing in the timing adjustment circuit 36 are drawn out to the outside.
[0031]
Next, the operation will be described. The transistor TR1 is turned off and TR2 is turned on so that VGE = N15V and the IGBT is turned off. From this state, when an overvoltage is applied between the collector and emitter of the IGBT and this reaches the avalanche voltage of the constant voltage element ZD, a current flows through the constant voltage element ZD to enter a clamping operation. Therefore, it is sufficient to induce a voltage necessary for driving the NPN transistor 32, so that it may be several mA to several tens mA. The PFET 33 is driven by the operation of the NPN transistor 32, and a necessary current is supplied to the gate of the IGBT. When the clamping operation of the constant voltage element ZD is executed, the current of the constant voltage element ZD disappears and the PFET 33 is also turned off.
The operation in which the NPN transistor 22 is turned on by the voltage change of the burden resistance, the capacitor 15 is charged via the PNP transistor 12, and the turn-off timing of the IGBT is adjusted based on the charging voltage of the capacitor 15 is the same as in the first embodiment. It is the same.
[0032]
As described above, in the fifth embodiment, the current rating of the constant voltage element ZD can be greatly reduced, and the size and cost can be reduced.
[0033]
In each of the above embodiments, the case where an IGBT is used as a self-extinguishing semiconductor element has been described. However, other types of self-extinguishing semiconductor elements can be applied in the same manner and have equivalent effects. . Further, the case where these elements are constituted by a plurality of elements connected in series to a DC voltage source is not limited to the case of being constituted by two elements exemplified in the above embodiment.
[0034]
【The invention's effect】
As described above, the power conversion device according to the present invention is a power conversion device that converts power in the on / off switching operation of the self-extinguishing semiconductor element,
An overvoltage protection circuit including a constant voltage element is provided between the positive electrode and the control electrode of the self-extinguishing semiconductor element, and is applied between the positive and negative electrodes of the self-extinguishing semiconductor element by a clamping operation of the constant voltage element. In what constitutes a series connection body in which overvoltage is suppressed and the constant voltage elements are connected in series to each other,
After the self-extinguishing semiconductor element is turned off, a change in the voltage between the control pole and negative electrode of the self-extinguishing semiconductor element generated based on the clamping operation of the constant voltage element is detected, and the change time length is set to a predetermined value. Since there is a constant voltage element failure detection means for determining that a short circuit fault has occurred in some elements of the series connection body constituting the constant voltage element when the time length is exceeded, a simple configuration of the constant voltage element Short circuit faults that occur in some elements can be reliably detected, and overvoltage protection circuit prevents excessive operation such as excessive voltage suppression. There is no fear of destruction.
[Brief description of the drawings]
FIG. 1 is a diagram showing an internal configuration of a gate drive circuit 40 in a power conversion device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an internal configuration of a semiconductor switch 41 configured using the gate drive circuit 40 of FIG.
3 is a circuit diagram showing a three-phase two-level inverter as a power conversion device configured using the semiconductor switch 41 of FIG. 2. FIG.
4 is a diagram illustrating the overvoltage protection circuit 6 of FIG. 1. FIG.
5 is a timing chart for explaining a short-circuit fault detection operation of the constant voltage element in FIG. 1; FIG.
6 is a diagram showing an internal configuration of a gate drive circuit 40 in the power conversion device according to the second embodiment of the present invention. FIG.
7 is a timing chart for explaining an operation for detecting a short-circuit fault of the constant voltage element in FIG. 6;
FIG. 8 is a diagram showing a power conversion device according to Embodiment 3 of the present invention.
FIG. 9 is a diagram showing a power conversion device according to Embodiment 4 of the present invention.
10 is a timing chart for explaining an operation for detecting a short-circuit fault of the constant voltage element in FIG. 9;
FIG. 11 is a diagram showing a power conversion device according to a fifth embodiment of the present invention.
[Explanation of symbols]
1 control signal generator, 2 IGBT, 6 overvoltage protection circuit,
7 input determination circuit, 13 signal holding circuit, 15 capacitor,
16 pulse shaping circuit, 30 failure detection circuit, 31 AMP part,
36 timing adjustment circuit, 40 (with failure detection circuit) gate drive circuit,
40A failure detection circuit no gate drive circuit, 41 semiconductor switch,
50 EXOR circuit, 51 Time difference judgment circuit, 53 Fault detection circuit,
54 Voltage level determination circuit, Ed DC voltage source.

Claims

A power conversion device that converts power in an on / off switching operation of a self-extinguishing semiconductor element,
An overvoltage protection circuit including a constant voltage element is provided between the positive electrode and the control electrode of the self-extinguishing semiconductor element, and is applied between the positive and negative electrodes of the self-extinguishing semiconductor element by a clamping operation of the constant voltage element. In what constitutes a series connection body in which overvoltage is suppressed and the constant voltage elements are connected in series to each other,
After the self-extinguishing semiconductor element is turned off, a change in the voltage between the control pole and negative electrode of the self-extinguishing semiconductor element generated based on the clamping operation of the constant voltage element is detected, and the change time length is set to a predetermined value. A power converter comprising: a constant voltage element failure detection means for determining that a short circuit fault has occurred in some of the elements of the series connection body constituting the constant voltage element when the time length is exceeded.

A power conversion device in which a plurality of self-extinguishing semiconductor elements are connected in series to a direct-current voltage source and perform power conversion by an on / off switching operation of each of the self-extinguishing semiconductor elements,
An overvoltage protection circuit including a constant voltage element is provided between the positive electrode and the control electrode of each self-extinguishing semiconductor element, and is applied between the positive and negative electrodes of the self-extinguishing semiconductor element by the clamping operation of the constant voltage element. In which the overvoltage is suppressed, and the constant voltage element is composed of a plurality of serially connected bodies connected in series with each other,
A capacitor charged with an amount of charge proportional to the clamp operation time length of the constant voltage element after the self-extinguishing semiconductor element is turned off, and the self-extinguishing semiconductor element for a time determined according to the voltage of the capacitor With a timing adjustment circuit that delays the off operation start timing of
Constant voltage element failure detection for determining that a short circuit fault has occurred in some elements of the series connection body constituting the constant voltage element when the adjustment delay time length in the timing adjustment circuit exceeds a predetermined set time length A power conversion device comprising means.

A power conversion device in which a plurality of self-extinguishing semiconductor elements are connected in series to a direct-current voltage source and perform power conversion by an on / off switching operation of each of the self-extinguishing semiconductor elements,
An overvoltage protection circuit including a constant voltage element is provided between the positive electrode and the control electrode of each self-extinguishing semiconductor element, and is applied between the positive and negative electrodes of the self-extinguishing semiconductor element by the clamping operation of the constant voltage element. In which the overvoltage is suppressed, and the constant voltage element is composed of a plurality of serially connected bodies connected in series with each other,
A capacitor charged with an amount of charge proportional to the clamp operation time length of the constant voltage element after the self-extinguishing semiconductor element is turned off, and the self-extinguishing semiconductor element for a time determined according to the voltage of the capacitor With a timing adjustment circuit that delays the off operation start timing of
When the voltage value of the capacitor exceeds a predetermined set voltage value, a constant voltage element failure detection means is provided for determining that a short circuit failure has occurred in some elements of the series connection body constituting the constant voltage element. The power converter characterized by this.

Among the plurality of self-extinguishing semiconductor elements connected in series to the DC voltage source, some include the constant voltage element failure detection means according to claim 2 or 3 (hereinafter referred to as self-extinguishing with failure detection means). The remainder is assumed to be obtained by omitting only the constant voltage element failure detection means from the configuration of claim 2 or 3 (hereinafter referred to as failure detection means self-extinguishing semiconductor element),
When a short-circuit fault occurs in the constant voltage element in the failure detection means self-extinguishing semiconductor element, the failure is detected based on an increase in the adjustment delay time length of the off operation start timing in the failure detection means self-extinguishing semiconductor element. In the self-extinguishing semiconductor element with a detecting means, the failure detecting means self-extinguishing semiconductor element is obtained by utilizing the phenomenon that the constant voltage failure detecting means operates by increasing the clamp operation time length of the constant voltage element. A power conversion device characterized in that the short-circuit fault of the constant voltage element generated in step 1 can be detected by the constant voltage fault detection means of the self-extinguishing semiconductor element with the fault detection means.

The overvoltage protection circuit includes an amplifying unit that amplifies a current generated by the clamping operation of the constant voltage element and supplies the current between the control pole and negative electrode of the self-extinguishing semiconductor element. The current rating of the self-extinguishing semiconductor element can be reduced from the current value that needs to be supplied between the control electrode and the negative electrode in order to suppress the overvoltage applied between both electrodes by causing a leakage current to flow between the electrode and the negative electrode. The power conversion device according to claim 1, wherein the power conversion device is a power conversion device.